Abstract: A method is provided. The method includes: assigning a buffer to a first wafer lot comprising a plurality of wafers according to a first trigger event associated with an equipment; and assigning a transporter to a second wafer lot comprising a plurality of wafers according to a second trigger event associated with the equipment.

Abstract: A non-transitory computer readable medium including instructions which, when executed by a processor, cause the processor to: store a design metric and a design metric variation from the simulation of the design metric for a subset of a plurality of conditions in an inner loop and an outer loop, wherein in the outer loop is a sample set of design dimensions and their respective values, while the inner loop varies a plurality of variation conditions of the subset; model the design metric and design metric variation using a response surface; and optimize the design metric or the design metric variation for the subset of a plurality of design dimensions using the response surface to generate an optimized design. In other aspects, a system and a method for design variation and optimization are provided.

Abstract: There is provided a substrate processing method including: supplying a developing liquid to a surface of an exposed substrate to form a resist pattern; supplying a cleaning liquid to the surface of the substrate to remove a residue generated in the developing step from the substrate; supplying a replacing liquid to the surface of the substrate to replace the cleaning liquid existing on the substrate with the replacing liquid, the replacing liquid having a surface tension of 50 mN/m or less and containing a percolation inhibitor for restraining the replacing liquid from percolating into a resist wall portion constituting the resist pattern; and forming a dry region by supplying a gas to a central portion of the substrate while rotating the substrate so as to dry the surface of the substrate by expanding the dry region to a peripheral edge portion of the substrate with a centrifugal force.

Abstract: Provided are a cutting information determination method that can use a simpler process to improve yield, and a strip-shaped polarizing sheet manufacturing method using such a method, an optical display unit manufacturing method using such a method, a strip-shaped polarizing sheet, and a polarizing sheet material. A cutting position in the width direction A2, in which a polarizing sheet material MP is to be cut along its longitudinal direction A1, is determined based on the numbers of defects counted with respect to plural points in the width direction A2 of the polarizing sheet material MP. This makes it possible to determine the cutting position in such a way that a region with many defects does not fall within the cut width, so that a higher-yield cutting position can be determined. The cutting position can also be determined using a simple process in which defects are counted with respect to plural points in the width direction A2.

Abstract: A method of manufacturing a semiconductor device includes performing a cycle a predetermined number of times, the cycle including supplying a first precursor containing a specific element and a halogen group to form a first layer and supplying a second precursor containing the specific element and an amino group to modify the first layer into a second layer. A temperature of the substrate is set such that a ligand containing the amino group is separated from the specific element in the second precursor, the separated ligand reacts with the halogen group in the first layer to remove the halogen group from the first layer, the separated ligand is prevented from being bonded to the specific element in the first layer, and the specific element from which the ligand is separated in the second precursor is bonded to the specific element in the first layer.

Abstract: A method and apparatus for process control in the processing of a substrate is disclosed in the present invention. Embodiments of the present invention utilize a first analysis tool to determine changes in a substrate's geometry. The substrate geometry data is used to generate sampling plan that will be used to check areas of the substrate that are likely to have errors after processing. The sampling plan is fed forwards to a second analysis tool that samples the substrate after it has been processed. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: Systems, methods and computer program products for DDL replication are described herein. An embodiment includes a replication agent to instantiate one or more DDL triggers in a primary database and a replication server to provide DDL command text to a replicate database based on said DDL triggers. The replication agent uses the DDL trigger(s) to capture one or more DDL events and retrieve a transaction log associated with the DDL events. The replication agent processes the transaction log to obtain DDL command text. The DDL command text is then sent to a replicate database by the replication server where it is executed in an appropriate user context. In this way, DDL commands in may be replicated using DDL trigger(s) and session context switching.

Abstract: Methods and systems for generating a defect sample for a wafer are provided. One method includes separating defects detected on a wafer into bins having diversity in values of a first set of one or more first attributes of the defects. The method also includes selecting, independently from one or more of the bins, defects within the bins based on diversity in a second set of one or more second attributes of the defects. The selected defects are then used to create a defect sample for the wafer. In this manner, defects having diverse values of multiple attributes can be easily selected.

Abstract: A method for controlling a semiconductor fabrication process includes the steps of analyzing process-data related to an intermediate-process-step in the fabrication process and adjusting a metal-layer-parameter corresponding to the metal layer based on the process-data.

Abstract: A computer-implemented system and method for attribute-based manufacturing quality control is provided. A specification for manufacturing a part feature is maintained in a database, the specification including a nominal. Also maintained in the database are one or more measurements for the feature on a plurality of parts manufactured in accordance with the specification, each of the measurements associated with one or more attributes, each of the attributes identifying at least one of a circumstance relating to how that measurement was made and how the feature was manufactured. A user selection of one or more of the attributes is received. Each of the measurements that is associated with all of the selected attributes is identified. A score indicative of how close the identified measurements are to the nominal is calculated and displayed.

Abstract: Methods and systems for multiple manufacturing line qualification are provided. A method includes establishing a product template and producing products on one or more manufacturing lines. The products include product macros placed on a chip. The method also includes establishing allowed parametric match from line to line. The method further includes determining that products from the one or more manufacturing lines meet the allowed parametric match.

Abstract: Methods and systems for detecting defects on a wafer are provided. One method includes acquiring output for a wafer generated by an inspection system. Different dies are printed on the wafer with different process conditions. The different process conditions correspond to different failure modes for the wafer. The method also includes comparing the output generated for a first of the different dies printed with the different process conditions corresponding to a first of the different failure modes with the output generated for a second of the different dies printed with the different process conditions corresponding to a second of the different failure modes opposite to the first of the different failure modes. In addition, the method includes detecting defects on the wafer based on results of the comparing step.

Abstract: A system to, and a method to, select a metrology target for use on a substrate including performing a lithographic simulation for a plurality of points on a process window region for each proposed target, identifying a catastrophic error for any of the plurality of points for each proposed target, eliminating each target having a catastrophic error at any of the plurality of points, performing a metrology simulation to determine a parameter over the process window for each target not having a catastrophic error at any of the plurality of points, and using the one or more resulting determined simulated parameters to evaluate target quality.

Abstract: A method of forming a wire loop in connection with a semiconductor package is provided. The method includes the steps of: (1) providing package data related to the semiconductor package to a wire bonding machine; (2) providing at least one looping control value related to a desired wire loop to the wire bonding machine, the at least one looping control value including at least a loop height value related to the desired wire loop; (3) deriving looping parameters, using an algorithm, for forming the desired wire loop; (4) forming a first wire loop on the wire bonding machine using the looping parameters derived in step (3); (5) measuring actual looping control values of the first wire loop formed in step (4) corresponding to the at least one looping control value; and (6) comparing the actual looping control values measured in step (5) to the at least one looping control value provided in step (2).

Abstract: Techniques for compiling an integrated circuit (IC) design with an electronic design automation (EDA) tool are provided. The IC design may be compiled for different IC devices. When the IC design is compiled for a selected integrated circuit device, the EDA tool may analyze the IC design to determine whether the design is compatible with the selected IC device. If the IC design contains elements that are incompatible with the selected IC device, the EDA tool may compile the design based on a simulated removal of the incompatible elements. In some instances, the EDA tool may identify optimization opportunities in the IC design and may compile the design based on an optimized version of the IC design. The EDA tool may generate a compilation output (e.g., a performance analysis report) based on the simulated removal of the incompatible elements (or the optimized version of the IC design.

Abstract: A method of semiconductor fabrication is provided. The method includes providing a model for a device parameter of a wafer as a function of first and second process parameters. The first and second process parameters correspond to different wafer characteristics, respectively. The method includes deriving target values of the first and second process parameters based on a specified target value of the device parameter. The method includes performing a first fabrication process in response to the target value of the first process parameter. The method includes measuring an actual value of the first process parameter thereafter. The method includes updating the model using the actual value of the first process parameter. The method includes deriving a revised target value of the second process parameter using the updated model. The method includes performing a second fabrication process in response to the revised target value of the second process parameter.

Abstract: A method to determine the usefulness of an alignment mark of a first pattern in transferring a second pattern to a substrate relative to the first pattern already present on the substrate includes measuring the position of the alignment mark, modeling the position of the alignment mark, determining the model error between measured and modeled position, measuring a corresponding overlay error between first and second pattern and comparing the model error with the overlay error to determine the usefulness of the alignment mark. Subsequently this information can be used when processing next substrates thereby improving the overlay for these substrates. A lithographic apparatus and/or overlay measurement system may be operated in accordance with the method.

Abstract: Disclosed are a plasma processing method and a plasma processing apparatus which collectively perform etching under the same etching conditions while suppressing a shape abnormality. The multilayer film material has a polysilicon layer, a first metal layer formed on the polysilicon layer, and a hard mask layer which contains a tungsten layer formed on the first metal layer. In the method, plasma is generated by a mixed gas of a chloride-containing gas which contains a compound containing chlorine and silicon, a compound containing chlorine and boron, or a compound containing chlorine and hydrogen, a chlorine-containing gas which contains chlorine, and a processing gas which contains carbon and fluorine, and the hard mask layer is used as an etching mask so as to perform the etching from a top surface of the first metal layer to a bottom surface of the polysilicon layer.

Abstract: A per-chip equivalent oxide thickness (EOT) circuit sensor resides in an integrated circuit. The per-chip EOT circuit sensor determines electrical characteristics of the integrated circuit. The measured electrical characteristics include leakage current. The determined electrical characteristics are used to determine physical attributes of the integrated circuit. The physical attributes, including EOT, are used in a reliability model to predict per-chip failure rate.

Abstract: A substrate cartridge includes a cartridge main body that houses a substrate and an information-maintaining section that is housed in the cartridge main body and maintains information that includes at least specification information of specification values of the substrate housed in the cartridge main body.

Abstract: A metrology pattern layout for a circuit structure is provided, the metrology pattern layout including a plurality of quadrants, in which quadrants a first wafer measurement pattern, a second wafer measurement pattern, a reticle registration pattern, and a reticle measurement pattern may be arranged to facilitate correlation of reticle metrology data with wafer metrology data. The reticle registration pattern may further include one or more outermost structural elements designed to protect other structural elements within the reticle measurement pattern from being modified in an optical proximity correction process. A method of optical proximity correction process is provided, in which a reticle measurement pattern may be obtained and classified to add or modify a rule set of the optical proximity correction process.

Abstract: Scheduling and dispatching jobs for a plurality of different entities. A method includes receiving at a work coordinator, one or more actions associated with a job. The method further includes storing in a log at the work coordinator, keyed on a job key, state for the one or more actions and a list of the one or more actions. The method further includes making calls to one or more worker processes to cause the worker process to perform actions associated with the job. As a result of making calls to one or more worker processes, the method further includes receiving at least one of a change to the list of remaining actions or the state.

Abstract: A recipe management system associates a selected process recipe with a recipe group and checks to see if other recipes of the recipe group have been updated since the selected recipe was last run. If another recipe of the recipe group has been run and adjustments have been made to the other recipe based on an analysis of a manufacturing or test run, the recipe management system identifies the selected recipe as requiring an update. The recipe management system sends error reports noting the discrepancy between a parameter setting changed in the test run and needing adjustment in the selected run. The recipe management system also effectuates the needed adjustments to the selected recipe before the selected recipe is allowed to be used in the manufacturing environment.

Abstract: Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.

Abstract: A computer system iteratively executes a decision tree-based prediction model using a set of input variables. The iterations create corresponding rankings of the input variables. The computer system generates overall variables contribution data using the rankings of the input variables and identifies key input variables based on the overall variables contribution data.

Abstract: A statistical process control method for monitoring and controlling semiconductor manufacturing processing operations is provided. For a chosen processing operation, multiple measurement sites are used to generate data of a measurable characteristic that is impacted by and associated with the processing operation. The data from the sites is compared over time and one or more outlier sites are identified. The outlier sites are the sites at which the data values are most divergent from the rest of the data. Algorithms are used to mathematically compare the outlier sites to the other sites to produce a comparative index. The comparative index is monitored graphically or otherwise to identify changes in the processing operation, and corrective actions are taken.

Abstract: A system and method for mounting and charging a portable electronic device on or in contiguity to a wireless charging device. The wireless power transferring and charging device includes a suction pump that provides a suction vacuum to mount/hold a portable electronic device onto an induction charging surface of the wireless charging device in a vertical or semi-vertical position to be wirelessly powered and/or charged.

Abstract: Disclosed is a singulation apparatus for cutting a workpiece. The singulation apparatus comprises: i) a processor; ii) at least one chuck device for securing the workpiece to be cut; iii) a cutting device spaced from the at least one chuck device by a separation distance, the cutting device being for cutting the workpiece secured to the at least one chuck device; and iv) an imaging device operable to capture one or more images comprising the cutting device and a reference feature. In particular, the processor is configured to determine a separation distance between the cutting device and the reference feature based on the one or more images as captured by the imaging device, to thereby determine the separation distance between the cutting device and the workpiece as secured to the at least one chuck device.

Abstract: A method for operating a vacuum processing apparatus, the vacuum processing apparatus including: a plurality of cassette stands on which a cassette capable of housing a plurality of wafers therein can be placed; a plurality of vacuum processing vessels each having a processing chamber arranged therein, wherein the wafer is arranged and processed in the processing chamber; and at least one transport robot transporting the wafer on a transport path between either one of the plurality of cassettes and the plurality of vacuum processing vessels, the vacuum processing apparatus sequentially transporting in a predetermined transport order the plurality of wafers from either one of the plurality of cassettes to a predetermined one of the plurality of vacuum processing vessels and processing the plurality of wafers. The method includes a number determining step, a remaining-time determining step and a transport order skip step.

Abstract: The embodiments of mechanisms for monitoring thermal budget of an etch process of a cyclic deposition/etch (CDE) process to form an epitaxially grown silicon-containing material are descried to enable and to improve process control of the material formation. The monitoring is achieved by measuring the temperature of each processed wafer as a function of process time to calculate the accumulated thermal budget (ATB) of the wafer and to compare the ATB with a reference ATB (or optimal accumulated thermal budget, OATB) to see if the processed wafer is within an acceptable range (or tolerance). The results are used to determine whether to pass the processed wafer or to reject the processed wafer.

Abstract: A semiconductor device in related art has a problem that security on confidential information stored is insufficient. A semiconductor device of the present invention has a unique code which is unique to a device and generates unique code corresponding information from the unique code. The semiconductor device has a memory region in which specific information obtained by encrypting confidential information is stored in a region associated with the unique code corresponding information. The specific information read from the memory region is encrypted with the unique code corresponding information to generate the confidential information.

Abstract: To provide a substrate processing apparatus, including a control unit that performs control to transfer a prescribed substrate into each chamber, wherein when error is detected during transfer of the substrate, the control unit performs control to: specify a place where the error is generated; select a fallback operation table according to a processing status of the substrate, which is the table defining a processing content for each part of the substrate processing apparatus including the place where the error is generated; and transfer the substrate based on the selected fallback operation table.

Abstract: A method of controlling polishing includes polishing a substrate, monitoring the substrate during polishing with an in-situ spectrographic monitoring system to generate a sequence of measured spectra, selecting less than all of the measured spectra to generate a sequence of selected spectra, generating a sequence of values from the sequence of selected spectra, and determining at least one of a polishing endpoint or an adjustment for a polishing rate based on the sequence of values.

Abstract: A substrate cartridge includes a cartridge main body that houses a substrate and an information-maintaining section that is housed in the cartridge main body and maintains information that includes at least specification information of specification values of the substrate housed in the cartridge main body.

Abstract: Methods for providing run to run process control using a dynamic tuner are provided. Once such method includes receiving a data point for a process output parameter, determining whether the data point is within a desired range for the process output parameter, setting, when the data point is within the desired range, a dynamic lambda value equal to a preselected base lambda value, setting, when the data point is not within the desired range, the dynamic lambda value equal to a value based on the preselected base lambda value, a degree of difference between the data point and a target for the process output parameter, and a scale factor, calculating an exponentially weighted moving average using the dynamic lambda value, and adjusting the process control parameter in accordance with the exponentially weighted moving average.

Abstract: A grinding machine control method and a control system employing the method is disclosed. The grinding machine control method includes the step of providing a plurality of sub processing procedures each dominating a grinding machine to execute a respective processing step, the step of providing a processing scheduling processing to link the sub processing procedures into a main processing procedure, and the step of executing the main processing procedure to enable the grinding machine to run subject to the processing steps executed by the respective sub processing procedures.

Abstract: Throughput of manufacturing thin-film solar panels by inline technique is made substantially independent from the time extent of different surface treatment steps by accordingly subdividing treatment steps in sub-steps performed in inline subsequent treatment stations. Treatment duration in each of the subsequent treatment stations is equal(?).

Abstract: A method includes etching a low-k dielectric layer on a wafer to form an opening in the low-k dielectric layer. An amount of a detrimental substance in the wafer is measured to obtain a measurement result. Process conditions for baking the wafer are determined in response to the measurement result. The wafer is baked using the determined process conditions.

Abstract: Several embodiments of photolithography systems and associated methods of overlay error correction are disclosed herein. In one embodiment, a method for correcting overlay errors in a photolithography system includes measuring a plurality of first overlay errors that individually correspond to a microelectronic substrate in a first batch of microelectronic substrates. The method also includes determining a relationship between the first overlay errors and a first sequence of the microelectronic substrates in the first batch. The method further includes correcting a second overlay error of individual microelectronic substrates in a second batch based on a second sequence of the microelectronic substrates in the second batch and the determined relationship.

Abstract: Provided is a method for manufacturing a three-dimensional molded model that can reproduce the feel of an organ. A three-dimensional shape of a body site subject to molding is extracted from brightness information of two-dimensional data obtained from medical diagnostic devices, and three-dimensional molding data of the body site and the internal structure site thereof is created. The three-dimensional shape data is edited using a modeling function. Respective touch equivalent parameter tables are created. The material type and the formulation ratio of the modeling material used for molding each body site and internal structural site are defined, and added to the touch equivalent parameter tables. Primitive shape data is generated from the parameters of the touch equivalent parameter tables, and a Boolean operation is performed on the body site data and internal structure site data as well as on the primitive shape data. Molding is performed using the defined materials.

Abstract: A plasma processing system and method includes a processing chamber, and a plasma processing volume included therein. The plasma processing volume having a volume less than the processing chamber. The plasma processing volume being defined by a top electrode, a substrate support surface opposing the surface of the top electrode and a plasma confinement structure including at least one outlet port. A conductance control structure is movably disposed proximate to the at least one outlet port and capable of controlling an outlet flow through the at least one outlet port between a first flow rate and a second flow rate, wherein the conductance control structure controls the outlet flow rate and an at least one RF source is modulated and at least one process gas flow rate is modulated corresponding to a selected processing state set by the controller during a plasma process.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) fabrication method to form an IC structure having one or more through silicon via (TSV) features. The IC fabrication method includes performing a plurality of processing steps; collecting physical metrology data from the plurality of processing steps; collecting virtual metrology data from the plurality of processing steps based on the physical metrology data; generating a yield prediction to the IC structure based on the physical metrology data and the virtual metrology data; and identifying an action at an earlier processing step based on the yield prediction.

Abstract: A data analyzing method includes receiving monitor data from the substrate processing apparatus; producing representative value data based on the monitor data; associating apparatus condition information indicating a condition of the substrate processing apparatus at the time of production of the monitor data, with the representative value data; storing the representative value data and the apparatus condition information associated with the representative value data and in a database; retrieving the representative value data and the apparatus condition information associated with the representative value data from the database; comparing an exclusion parameter with the retrieved apparatus condition information, the exclusion parameter including information indicating whether the retrieved representative value data should be included in analysis processing targets; and determining whether the retrieved representative value data should be included in the analysis processing targets, based on the comparison res

Abstract: Embodiments of the present invention provide an approach for monitoring electrical disturbance (e.g., surges, outages, etc.) possibilities, and then automatically isolating electronic devices (also referred to herein as electronics) for the duration of the disturbance (or threat thereof). In a typical embodiment, a probability of an electrical disturbance occurring at a specified location will be determined. Then, a set of device protection profiles will be accessed. The set of device protection profiles comprises a set of thresholds and a corresponding set of device topologies associated with a set of electronic devices positioned. The set of thresholds in the set of device protection profiles will then be compared to the probability to identify a matching device topology from the set of device topologies. According to the matching device topology, at least one electronic device will be isolated from an electrical power source.

Abstract: A thin film deposition apparatus includes: a chamber; a mask stage in the chamber and configured to support a mask; a jig in the chamber and above the mask stage, the jig being configured to move in a direction of the mask stage; and a rail in the chamber and configured to support the movement of the jig. Another thin film deposition apparatus includes a chamber, a mask stage positioned within the chamber and configured to support a mask, a camera part proximate to a side of the mask stage, and a jig above the mask stage and configured to move in a direction of the mask stage and over the camera part. The jig is further configured to radiate laser beams in a downward direction from the jig to obtain first scanning data regarding the mask stage and second scanning data regarding the camera part.

Abstract: A method, computer program product, and system for a quality-of-service history database is described. A first input associated with a change to a component of a graphical user interface is received, wherein a portion of the component is represented as a first node of a tree structure representing a portion of the graphical user interface. A first characteristic of the change is determined. The first characteristic of the change is associated with a second node of the topic tree structure. The associated first characteristic is transmitted to a first computing device, wherein transmission of the associated first characteristic allows one or more of the first computing device and a second computing device to determine a first aspect of the change based upon, at least in part, the topic tree structure.

Abstract: A data lineage system is provided that traces a data lineage of a data warehouse. The data lineage system maps a target data element to one or more source data elements. The data lineage system further stores one or more source surrogate keys within one or more auxiliary columns of a target data record. The data lineage system further stores, for each source data element, a data lineage mapping system record within a data lineage mapping system table that represents the mapping of the target data element and the corresponding source data element. The data lineage system further maps a source data element to one or more target data elements. The system further stores, for each target data element, a shadow system record within a shadow system table that represents the mapping of the source data element and the corresponding target data element.

Abstract: A process for determining a root cause problem for an out-of-tolerance component manufactured by a plurality of operations performed on the component. The process can include providing manufacturing data from at least a subset of plurality of operations performed on a plurality of components and discovering an out-of-tolerance measurement on at least a subset of the plurality of manufactured components downstream from the plurality of operations. An auto-regression analysis between the out-of-tolerance measurement and the plurality of upstream operations can also be performed using the manufacturing data. A correlation between at least one of the upstream operations and the out-of-tolerance measurement can be found and the correlation can result in the identification of at least one upstream operation that is the root cause of the out-of-tolerance measurement.

Abstract: The disclosed embodiments are directed to systems and method for floorplanning an integrated circuit design using a mix of 2D and 3D blocks that provide a significant improvement over existing 3D design methodologies. The disclosed embodiments provide better floorplan solutions that further minimize wirelength and improve the overall power/performance envelope of the designs. The disclosed methodology may be used to construct new 3D IP blocks to be used in designs that are built using monolithic 3D integration technology.

Abstract: A statistical process control method for monitoring and controlling semiconductor manufacturing processing operations is provided. For a chosen processing operation, multiple measurement sites are used to generate data of a measurable characteristic that is impacted by and associated with the processing operation. The data from the sites is compared over time and one or more outlier sites are identified. The outlier sites are the sites at which the data values are most divergent from the rest of the data. Algorithms are used to mathematically compare the outlier sites to the other sites to produce a comparative index. The comparative index is monitored graphically or otherwise to identify changes in the processing operation, and corrective actions are taken.