Integrated Circuit Production Or Semiconductor Fabrication Patents (Class 700/121)
  • Patent number: 9056421
    Abstract: A manufacturing method is adapted for materials that are susceptible to deformation during the manufacturing process, such as composite parts that change shape during curing. The method includes modifying a part design to compensate for changes in the shape of the part that occur during a curing phase of the manufacturing process. A manufacturing mold is created according to the modified part design, then a part is formed in the mold and cured in the mold. While the part is still in the mold after the curing phase, the part is finished according to the modified part design wherein excess material is removed and apertures are created. While the part is still in the mold after the finishing phase, the finished part is inspected using automated inspection equipment to confirm that the finished part conforms to the modified part design.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: June 16, 2015
    Assignee: Spirit AeroSystems, Inc.
    Inventor: Blaise Francis Bergmann
  • Patent number: 9046982
    Abstract: A method, computer program product, and system for a quality-of-service history database is described. A first input associated with a change to a component of a graphical user interface is received, wherein a portion of the component is represented as a first node of a tree structure representing a portion of the graphical user interface. A first characteristic of the change is determined. The first characteristic of the change is associated with a second node of the topic tree structure. The associated first characteristic is transmitted to a first computing device, wherein transmission of the associated first characteristic allows one or more of the first computing device and a second computing device to determine a first aspect of the change based upon, at least in part, the topic tree structure.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: June 2, 2015
    Assignee: International Business Machines Corporation
    Inventors: Steven John Horsman, Matthew John Kockott, Jonathan Christopher Mace, Andrew Moger
  • Publication number: 20150148934
    Abstract: Necessary unit data indicative of the type and number of equipment units used in component mounting operation is obtained on the basis of production plan data, mounting data, and component library for each of production lots in advance. New allocation processing for allocating an equipment unit necessary for production execution of a new production lot to be newly produced on an electronic component mounting line for the new production lot on the basis of the necessary unit data is executed, and component reservation processing for registering the allocation result as the inventory data is conducted by a unit reservation unit.
    Type: Application
    Filed: February 21, 2013
    Publication date: May 28, 2015
    Inventors: Yasuhiro Maenishi, Norihasa Yamasaki, Yuji Nakamura
  • Publication number: 20150148935
    Abstract: A substrate processing system includes a substrate processing apparatus for generating apparatus data on substrate processing and a management apparatus connected to at least one substrate processing apparatus via a network for receiving and storing the apparatus data periodically reported from the substrate processing apparatus. The substrate processing apparatus includes a storage unit for storing the apparatus data a report cycle or the number of reports of the apparatus data to the management apparatus, and a degree of importance of the apparatus data in association with a data type of the apparatus data, and a control unit for, when changing a report cycle of the apparatus data, determining a data type of the report cycle of which is to be changed based on the report cycle or the number of reports and the degree of importance per data type stored in the storage unit.
    Type: Application
    Filed: June 21, 2013
    Publication date: May 28, 2015
    Applicant: Hitachi Kokusai Electric Inc.
    Inventor: Toshiro Koshimaki
  • Publication number: 20150148933
    Abstract: A method for monitoring a process in a semiconductor processing facility and a monitor system are provided. A plurality of wafers are processed according to a process. Data on the processing is collected, and the collecting includes, for each wafer of the plurality of wafers, determining that a processing event has occurred, and recording a time associated with the processing event. An amount of time between the recorded times is calculated for consecutively processed wafers. A set of control limits for the process is determined based on the calculated amounts of time. The set of control limits define a range of acceptable values for the amount of time. Second wafers are processed according to the process. A problem in the processing of the second wafers is identified based on the set of control limits. The problem is identified as the second wafers are being processed.
    Type: Application
    Filed: November 27, 2013
    Publication date: May 28, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: CHIH-WEI HUANG, FENG-NING LEE
  • Publication number: 20150142161
    Abstract: The present invention provides apparatus for a mobile cleanspace fabrication facility. Various methods relating to moving a mobile cleanspace fabrication facility and to the locations that a mobile cleanspace fabrication facility may be moved to are discussed.
    Type: Application
    Filed: November 17, 2014
    Publication date: May 21, 2015
    Inventor: Frederick A. Flitsch
  • Publication number: 20150142162
    Abstract: A multi-client multi-protocol equipment server includes: a host interface that facilitates communication with a manufacturing execution system (MES); a plurality of client interfaces, wherein each client interface facilitates communication with a client based on a Common Equipment Model (CEM) for a semiconductor manufacturing tool; and a plurality of tool interfaces, wherein each tool interface facilitates communication with a semiconductor manufacturing tool, wherein at least one of the interfaces is a Semi Equipment Communications Standard/Generic Model for Communications and Control of Manufacturing Equipment (SECS/GEM) interface that is configured in a single XML file that defines attributes of the CEM for the semiconductor manufacturing tool which uses the SECS/GEM interface, and wherein a computer executes the multi-client multi-protocol server.
    Type: Application
    Filed: January 24, 2015
    Publication date: May 21, 2015
    Inventors: Charles M. Bayliss, Raymond W. Ellis, Toni Guckert, Timothy Yoas
  • Patent number: 9037279
    Abstract: A first embodiment is a method for semiconductor process control comprising clustering processing tools of a processing stage into a tool cluster based on processing data and forming a prediction model for processing a semiconductor wafer based on the tool cluster. A second embodiment is a method for semiconductor process control comprising providing cluster routes between first stage tool clusters and second stage tool clusters, assigning a comparative optimization ranking to each cluster route, and scheduling processing of wafers. The comparative optimization ranking identifies comparatively which cluster routes provide for high wafer processing uniformity.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Francis Ko, Tzu-yu Wang, Kewei Zuo, Henry Lo, Jean Wang, Chih-Wei Lai
  • Patent number: 9037280
    Abstract: Computer-implemented methods for performing one or more defect-related functions are provided. One method for identifying noise in inspection data includes identifying events detected in a number of sets of inspection data that is less than a predetermined number as noise. One method for binning defects includes binning the defects into groups based on defect characteristics and the sets of the inspection data in which the defects were detected. One method for selecting defects for defect analysis includes binning defects into group(s) based on proximity of the defects to each other and spatial signatures formed by the group(s). A different method for selecting defects for defect analysis includes selecting defects having the greatest diversity of defect characteristic(s) for defect analysis. One method includes classifying defects on a specimen using inspection data generated for the specimen combined with defect review data generated for the specimen.
    Type: Grant
    Filed: June 6, 2005
    Date of Patent: May 19, 2015
    Assignee: KLA-Tencor Technologies Corp.
    Inventors: Mark Dishner, Chris W. Lee, Sharon McCauley, Patrick Huet, David Wang
  • Patent number: 9031685
    Abstract: A method and apparatus for atomic layer deposition (ALD) is described. In one embodiment, an apparatus comprises a vacuum chamber body having a contiguous internal volume comprised of a first deposition region spaced-apart from a second deposition region, the chamber body having a feature operable to minimize intermixing of gases between the first and the second deposition regions, a first gas port formed in the chamber body and positioned to pulse gas preferentially to the first deposition region to enable a first deposition process to be performed in the first deposition region, and a second gas port formed in the chamber body and positioned to pulse gas preferentially to the second deposition region to enable a second deposition process to be performed in the second deposition region is provided.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: May 12, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Barry L. Chin, Alfred W. Mak, Lawrence C. Lei, Ming Xi, Hua Chung, Ken Kaung Lai, Jeong Soo Byun
  • Patent number: 9031684
    Abstract: A method and system for integrated circuit fabrication is disclosed. In an example, the method includes determining a first process parameter of a wafer and a second process parameter of the wafer, the first process parameter and the second process parameter corresponding to different wafer characteristics; determining a variation of a device parameter of the wafer based on the first process parameter and the second process parameter; constructing a model for the device parameter as a function of the first process parameter and the second process parameter based on the determined variation of the device parameter of the wafer; and performing a fabrication process based on the model.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nai-Han Cheng, Chin-Hsiang Lin, Chi-Ming Yang, Chun-Lin Chang, Chih-Hong Hwang
  • Publication number: 20150127133
    Abstract: A positioning system having a flat base comprising (i) a X-axis assembly having a X-axis linear actuator means arranged orthogonal to the Y-axis; (ii) a Y-axis assembly having a pair of Y-axis linear actuator means mounted onto the flat base forming a H-configuration; (iii) a Z-axis assembly having an aerostatic bearing mechanism that floats on thin film of externally pressurized air on top of the flat base; and a ?-axis actuator anchored from the X-axis to drive the Z-axis assembly which carries a workpiece, wherein the Z-axis assembly is rotated with the rotary axis for the ?-axis perpendicular to the flat base.
    Type: Application
    Filed: January 30, 2013
    Publication date: May 7, 2015
    Applicant: Akribis Systems Pte Ltd
    Inventors: Sastra Budiman, Yong Peng Leow, Mun Hoon Ng
  • Patent number: 9026558
    Abstract: A connection to an item of equipment is detected. An equipment class of the item of equipment is determined. A selection of an attribute associated with the item of equipment is received. An attribute record corresponding to the equipment class of the item of equipment and the selected attribute is retrieved from a database, wherein the attribute record enables a retrieval of a value of the selected attribute from the item of equipment.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: May 5, 2015
    Assignee: Applied Materials, Inc.
    Inventor: Mark Vandevert Dunkle
  • Patent number: 9026241
    Abstract: The present disclosure relates to semiconductor tool monitoring system having multiple sensors configured to concurrently and independently monitor processing conditions of a semiconductor manufacturing tool. In some embodiments, the disclosed tool monitoring system comprises a first sensor system configured to monitor one or more processing conditions of a semiconductor manufacturing tool and to generate a first monitoring response based thereupon. A redundant, second sensor system is configured to concurrently monitor the one or more processing conditions of the manufacturing tool and to generate a second monitoring response based thereupon. A comparison element is configured to compare the first and second monitoring responses, and if the responses deviate from one another (e.g., have a deviation greater than a threshold value) to generate a warning signal. By comparing the first and second monitoring responses, errors in the sensor systems can be detected in real time, thereby preventing yield loss.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: May 5, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Cheng Yang, Chung-En Kao, You-Hua Chou, Ming-Chih Tsai, Chen-Chia Chiang, Bo-Hung Lin, Chin-Hsiang Lin
  • Patent number: 9013684
    Abstract: Microlithographic illumination system includes individually drivable elements to variably illuminate a pupil surface of the system. Each element deviates an incident light beam based on a control signal applied to the element. The system also includes an instrument to provide a measurement signal, and a model-based state estimator configured to compute, for each element, an estimated state vector based on the measurement signal. The estimated state vector represents: a deviation of a light beam caused by the element; and a time derivative of the deviation. The illumination system further includes a regulator configured to receive, for each element: a) the estimated state vector; and b) target values for: i) the deviation of the light beam caused by the deviating element; and ii) the time derivative of the deviation.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: April 21, 2015
    Assignee: Carl Zeiss SMT GmbH
    Inventors: Stefan Xalter, Yim-Bun Patrick Kwan, Andras G. Major, Manfred Maul, Johannes Eisenmenger, Damian Fiolka, Jan Horn, Markus Deguenther, Florian Bach, Michael Patra, Johannes Wangler, Michael Layh
  • Publication number: 20150105895
    Abstract: Described herein are methods and systems for chamber matching in a manufacturing facility. A method may include receiving a first chamber recipe advice for a first chamber and a second chamber recipe advice for a second chamber. The chamber recipe advices describe a set of tunable inputs and a set of outputs for a process. The method may further include adjusting at least one of the set of first chamber input parameters or the set of second chamber input parameters and at least one of the set of first chamber output parameters or the set of second chamber output parameters to substantially match the first and second chamber recipe advices.
    Type: Application
    Filed: March 24, 2014
    Publication date: April 16, 2015
    Applicant: Applied Materials, Inc.
    Inventors: James Robert Moyne, Jimmy Iskandar
  • Patent number: 9003338
    Abstract: One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: William Wu Shen, Yun-Han Lee, Chin-Chou Liu, Hsien-Hsin Lee, Chung-Sheng Yuan, Chao-Yang Yeh, Wei-Cheng Wu, Ching-Fang Chen
  • Patent number: 9002497
    Abstract: Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the wafer in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: April 7, 2015
    Assignee: KLA-Tencor Technologies Corp.
    Inventors: William Volk, James Wiley, Sterling Watson, Sagar A. Kekare, Carl Hess, Paul Frank Marella, Sharon McCauley, Ellis Chang
  • Patent number: 9002498
    Abstract: The present disclosure relates to a process tool system that utilizes tool sensor data and an embedded or built-in tool model to facilitate semiconductor fabrication. The process tool system includes a sensor data component, the tool model, and an execution system. The sensor data component is configured to provide the tool sensor data. The tool model is built in a process tool and is configured to generate model outputs based on model inputs. The manufacturing execution system is configured to provide tool process data, including actual metrology and previous process data, to the sensor data component. Additionally, the execution system provides the model inputs to the tool model and receives the model outputs from the tool model. The execution system provides one or more execution system outputs based on the sensor data and the model outputs. The sensor data can include measured semiconductor device characteristics.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yung-Cheng Chang
  • Patent number: 9002494
    Abstract: There is provided a substrate transfer method capable of preventing fine particles from adhering to a wafer. A substrate processing system 10 includes process modules 12 to 17 each having therein an inner space S1; a transfer module 11, having an inner space S2, connected to the process modules 12 to 17; and opening/closing gate valves 30 each partitioning the inner space S1 and the inner space S2. The transfer module 11 includes in the inner space S2 a transfer arm device 21 for holding a wafer W and for loading/unloading the wafer W into/from the process modules 12 to 17. The transfer arm device 21 holds the wafer W at a retreated position deviated from a facing position facing the gate valve 30 during an opening motion of the gate valve 30.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: April 7, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Eiki Endo, Tatsuya Ogi
  • Patent number: 8987645
    Abstract: Provided are a substrate processing apparatus and a method of manufacturing a semiconductor device that are capable of uniformly heating a substrate while reducing an increase in substrate temperature to reduce a thermal budget. The substrate processing apparatus includes a process chamber configured to process a substrate; a substrate support unit installed in the process chamber to support the substrate; a microwave supply unit configured to supply a microwave toward a process surface of the substrate supported by the substrate support unit, the microwave supply unit including a microwave radiating unit radiating the microwave supplied from a microwave source to the process chamber while rotating; a partition installed between the microwave supply unit and the substrate support unit; a cooling unit installed at the substrate support unit; and a control unit configured to control at least the substrate support unit, the microwave supply unit and the cooling unit.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: March 24, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Unryu Ogawa, Masahisa Okuno, Tokunobu Akao, Shinji Yashima, Atsushi Umekawa, Kaichiro Minami
  • Patent number: 8989890
    Abstract: In polishing a substrate having a layer of GST disposed over an underlying layer, during polishing, a non-polarized light beam is directed onto the layer of GST. The non-polarized light beam reflects from the first substrate to generate a reflected light beam having an infra-red component. A sequence of measurements of intensity of the infra-red component of the reflected light beam are generated, and, in a processor, a time at which the sequence of measurements exhibits a predefined feature is determined.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: March 24, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Kun Xu, Feng Liu, Dominic J. Benvegnu, Boguslaw A. Swedek, Yuchun Wang, Wen-Chiang Tu, Laksh Karuppiah
  • Publication number: 20150081081
    Abstract: Among other things, one or more systems and techniques for retuning a semiconductor fabrication component are provided. The semiconductor fabrication component, such as an advanced process control (APC) component, is configured to evaluate or adjust various fabrication parameters associated with semiconductor fabrication processing. Processing data associated with the semiconductor fabrication component is evaluated to formulate performance indices used to evaluate performance of parameters used by the semiconductor fabrication component. One or more fabrication process change simulations are performed to generate a component operating behavior data structure indicating how different values for the parameters result in improved or degraded performance by the semiconductor fabrication component. In this way, the component operating behavior data structure is evaluated to identify tuning values for the parameters that are used to retune the semiconductor fabrication component.
    Type: Application
    Filed: September 18, 2013
    Publication date: March 19, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Keung Hui, Cheng Yen-Wei, Jong-I Mou
  • Patent number: 8983644
    Abstract: A manufacturing execution system (MES) with virtual-metrology capabilities and a manufacturing system including the MES are provided. The MES is built on a middleware architecture (such as an object request broker architecture), and includes an equipment manager, a virtual metrology system (VMS), a statistical process control (SPC) system, an alarm manager and a scheduler. The manufacturing system includes a first process tool, a second process tool, a metrology tool, the aforementioned MES, a first R2R (Run-to-Run) controller and a second R2R controller.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: March 17, 2015
    Assignee: National Cheng Kung University
    Inventors: Fan-Tien Cheng, Chi-An Kao, Hsien-Cheng Huang, Yung-Cheng Chang
  • Patent number: 8983631
    Abstract: A process-level troubleshooting architecture (PLTA) configured to facilitate substrate processing in a plasma processing system is provided. The architecture includes a process module controller. The architecture also includes a plurality of sensors, wherein each sensor of the plurality of sensors communicates with the process module controller to collect sensed data about one or more process parameters. The architecture further includes a process-module-level analysis server, wherein the process-module-level analysis server communicates directly with the plurality of sensors and the process module controller. The process-module-level analysis server is configured for receiving data, wherein the data include at least one of the sensed data from the plurality of sensors and process module and chamber data from the process module controller.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: March 17, 2015
    Assignee: Lam Research Corporation
    Inventors: Chung Ho Huang, Vijayakumar C. Venugopal, Connie Lam, Dragan Podlesnik
  • Publication number: 20150073581
    Abstract: Provided is a system for reducing energy consumption and fraction defective when producing a PCB based on a USN, which provides the optimal environment information in PCB production by acquiring, accumulating, and analyzing the environment information in each process when producing the PCB.
    Type: Application
    Filed: September 11, 2013
    Publication date: March 12, 2015
    Applicant: Advanced Consulting Services Corp.
    Inventors: Suk Keun CHA, Gyu Bong LEE
  • Patent number: 8977379
    Abstract: In one aspect, a method of polishing includes polishing a substrate, and receiving an identification of a selected spectral feature and a characteristic of the selected spectral feature to monitor during polishing. The method includes measuring a sequence of spectra of light reflected from the substrate while the substrate is being polished, where at least some of the spectra of the sequence differ due to material being removed during the polishing. The method of polishing includes determining a value of a characteristic of the selected spectral feature for each of the spectra in the sequence of spectra to generate a sequence of values for the characteristic, fitting a function to the sequence of values, and determining either a polishing endpoint or an adjustment for a polishing rate based on the function.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: March 10, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Jeffrey Drue David, Harry Q. Lee, Dominic J. Benvegnu, Boguslaw A. Swedek
  • Publication number: 20150066183
    Abstract: A method of making a semiconductor device includes collecting process control parameters during operation of a processing tool processing a product. The method further includes calculating a processing tool offset for the processing tool based on the collected process control parameters and calculating a product offset based on the collected process control parameters. The method further includes determining whether the product offset is stable and calculating an offset time for processing the product using the processing tool based on the calculated processing tool offset if the product offset is stable.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 5, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Hsi NAN, Yu-Hsiu FU, Chia Jung CHANG
  • Patent number: 8972036
    Abstract: Only a wafer for QC check may be transferred and a production wafer may prevent from being transferred into an assigned process chamber whose QC check is not completed after a maintenance task, and the production wafer may be processed the assigned process chamber after the completion of the QC check. The wafer for QC check is transferred while inhibiting a transfer of the production wafer into the assigned process chamber, and the production wafer is transferred into each of the process chambers of the plurality except the assigned process chamber.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: March 3, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventor: Makoto Nomura
  • Patent number: 8972029
    Abstract: Software for controlling processes in a heterogeneous semiconductor manufacturing environment may include a wafer-centric database, a real-time scheduler using a neural network, and a graphical user interface displaying simulated operation of the system. These features may be employed alone or in combination to offer improved usability and computational efficiency for real time control and monitoring of a semiconductor manufacturing process. More generally, these techniques may be usefully employed in a variety of real time control systems, particularly systems requiring complex scheduling decisions or heterogeneous systems constructed of hardware from numerous independent vendors.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: March 3, 2015
    Assignee: Brooks Automation, Inc.
    Inventors: Patrick D. Pannese, Vinaya Kavathekar, Peter van der Meulen
  • Patent number: 8972909
    Abstract: The present disclosure relates to a method of performing an optical proximity correction (OPC) procedure that provides for a high degree of freedom by using an approximation design layer. In some embodiments, the method is performed by forming an integrated chip (IC) design having an original design layer with one or more original design shapes. An approximation design layer, which is different from the original design layer, is generated from the original design layer. The approximation design layer is a design layer that has been adjusted to remove features that may cause optical proximity correction (OPC) problems. An optical proximity correction (OPC) procedure is then performed on the approximation design layer. By performing the OPC procedure on the approximation design layer rather than on the original design layer, characteristics of the OPC procedure can be improved.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Cheng Chang, Jau-Shian Liang, Wen-Chen Lu, Chin-Min Huang, Ming-Hui Chih, Cherng-Shyan Tsay, Chien-Wen Lai, Hua-Tai Lin
  • Patent number: 8965550
    Abstract: A wafer fabrication outcome, such as wafer yield or wafer lifetime, is predicted by excluding uncontrollable but measurable internal/external noises of a DOE system, and by rendering relations between wafer design variables and wafer outcome outputs to be more causal, as well as the relations between variances for each of the wafer design variables and the wafer outcome outputs. With the aid of a wafer fabrication outcome predicting model formed by the more causal relations, precision of predicting wafer outcomes can be raised, and performance of wafer fabrication can be thus raised as a result.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: February 24, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Hsin-Ming Hou, Ji-Fu Kung
  • Patent number: 8962448
    Abstract: A computer readable medium is provided that is encoded with a program comprising instructions for performing a method for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Robert Hannon, Subramanian S. Iyer, Steven J. Koester, Fei Liu, Sampath Purushothaman, Albert M. Young, Roy R. Yu
  • Patent number: 8966410
    Abstract: A method for fabricating a semiconductor layout includes providing a first layout having a plurality of line patterns and a second layout having a plurality of connection patterns, defining at least a first to-be-split pattern overlapping with the connection pattern among the line patterns, splitting the first to-be-split pattern at where the first to-be-split pattern overlapping with the connection pattern, decomposing the first layout to form a third layout and a fourth layout, and outputting the third layout and the further layout to a first mask and a second mask respectively.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: February 24, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chia-Wei Huang, Ming-Jui Chen, Chun-Hsien Huang
  • Patent number: 8965572
    Abstract: In recent years, frames have gotten larger in size and thinner, and warping of the frames has posed a problem. If a warp of a frame is large, there is a high possibility that fetching the frame may fail. If fetching the frame fails, that is, if the frame cannot be fetched, the lead time of mounting gets longer. Further, the frame that cannot be fetched has to be manually removed by an operator. Therefore, a man-hour increases. According to the present invention, before a loader feeder fetches a frame from a frame magazine, a loader lifter is moved in a Y direction. Thereafter, the loader feeder fetches the frame from the frame magazine.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: February 24, 2015
    Assignee: Hitachi High-Tech Instruments Co., Ltd.
    Inventors: Tatsuyuki Ohkubo, Mitsuo Yoda
  • Publication number: 20150045937
    Abstract: A conveyance system includes storage racks that are provided near or adjacent to semiconductor manufacturing devices and store therein objects to be conveyed, a stacker crane that carries the objects into and out of the storage racks, vehicles that convey the objects, an ID tag reader that is provided to the stacker crane and reads ID tags of the objects; and a controller that is configured or programmed to, when identification information acquired by the ID tag reader R coincides with identification information contained in a conveyance command of an object, control the stacker crane to convey the object to a destination specified in the conveyance command. At least one section of each storage rack allows a gripper of each vehicle to take in and out the objects.
    Type: Application
    Filed: March 7, 2013
    Publication date: February 12, 2015
    Inventor: Makoto Yamamoto
  • Publication number: 20150045936
    Abstract: A system includes a head board with a first head processor, a first carrier board, and a first junction. The first carrier board includes a first plurality of connectors configured to communicatively couple the head board to one or more first acquisition modules with a first attachment pattern. The first carrier board is configured in a first simplex or a first redundant configuration based at least in part on the first attachment pattern. The first junction is configured to removably couple the first carrier board with a terminator or to removably couple the first carrier board with a second carrier board.
    Type: Application
    Filed: August 8, 2013
    Publication date: February 12, 2015
    Applicant: General Electric Company
    Inventors: Daniel Milton Alley, Alan Carroll Lovell, Christopher Todd Moore
  • Patent number: 8954184
    Abstract: System(s) and method(s) are provided for adjustment and analysis of performance of a tool through integration of tool operational data and spectroscopic data related to the tool. Such integration results in consolidated data that enable, in part, learning at least one relationship amongst selected portions of the consolidated data. Learning is performed autonomously without human intervention. Adjustment of performance of the tool relies at least in part on a learned relationship and includes generation of process recipe parameter(s) that can adjust a manufacturing process in order to produce a satisfactory tool performance in response to implementation of the manufacturing process. A process recipe parameter can be generated by solving an inverse problem based on the learned relationship.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: February 10, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Sanjeev Kaushal, Sukesh Janubhai Patel, Kenji Sugishima
  • Patent number: 8948899
    Abstract: Provided are a substrate processing apparatus, a display method thereof, and a substrate processing system capable of detecting any change in the condition of each component of a substrate processing apparatus. In the substrate processing system including the substrate processing apparatus for processing a substrate and a group management apparatus connected thereto, the substrate processing apparatus is configured to acquire monitor data representing at least the condition of each component of the substrate processing apparatus, aggregate a plurality of the monitor data to generate package data including at least one of a maximum value, an average value, and a minimum value of the monitor data, and transmit the package data to the group management apparatus. The group management apparatus is configured to receive the package data from the substrate processing apparatus and readably store the same therein.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: February 3, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventor: Kazuhide Asai
  • Patent number: 8948900
    Abstract: A component mounting apparatus includes: an operational sequence supervision unit which is created in compiler language determining an operational sequence specifying a series of sequence operations of suctioning, recognizing and mounting a component; and a second memory unit which stores a custom program, created in interpreter language and specifying an operation different from the series of sequence operations, and custom program designation information that designates execution of the custom program. The operational sequence supervision unit controls a switching process for switching from the series of sequence operations to an interpreter language processing execution routine for executing the custom program, during, or before or after, the series of sequence operations in accordance with the custom program designation information.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: February 3, 2015
    Assignee: Yamaha Hatsudoki Kabushiki Kaisha
    Inventor: Yasushi Miyake
  • Publication number: 20150032245
    Abstract: A method includes receiving a voltage and current measured at an output of an RF generator of a first plasma system and calculating a first model etch rate based on the voltage and current, and a power. The method further includes receiving a voltage and current measured at an output of the RF generator of a second plasma system, determining a second model etch rate based on the voltage and current at the output of the RF generator of the second plasma system, and comparing the second model etch rate with the first model etch rate. The method includes adjusting a power at the output of the RF generator of the second plasma system to achieve the first model etch rate associated with the first plasma system upon determining that the second model etch rate does not match the first model etch rate. The method is executed by a processor.
    Type: Application
    Filed: April 2, 2014
    Publication date: January 29, 2015
    Applicant: Lam Research Corporation
    Inventors: John C. Valcore, JR., Harmeet Singh, Henry Povolny
  • Publication number: 20150032246
    Abstract: An energy-consumption monitoring system for a substrate processing apparatus includes a data collection device which collects process implementation data of a process to be executed according to each recipe in a substrate processing apparatus, a memory device which stores energy consumption data that indicate relationship between an individual energy-consuming event in the process and an amount of energy consumed per unit time by the individual energy-consuming event, and a computation device which detects an occurrence of the individual energy-consuming event and virtually calculate a cumulative energy consumption based on a duration of the individual energy-consuming event and the energy consumption data of the individual energy-consuming event stored in the memory device.
    Type: Application
    Filed: September 9, 2014
    Publication date: January 29, 2015
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Taku Mizutani, Ichiro Namioka, Kazushi Mori
  • Patent number: 8940365
    Abstract: A device to form a coating film which can quickly coat a substrate of a follow-up lot after coating a preceding lot. The device is configured such that nozzles for a preceding lot and a following lot are integrated into a common movement mechanism and moved between an upper side of a liquid processing unit and a standby area. A coating method includes sucking air into the nozzle for the preceding lot to form an upper gas layer, sucking a solvent for the preceding lot in the standby area to form a thinner layer, and sucking air into the nozzle for the preceding lot to form a lower gas layer within the nozzle, and thus forming a state that a solvent layer is interposed between the upper gas layer and the lower gas layer.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: January 27, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Akira Miyata, Yoshitaka Hara, Kouji Fujimura
  • Patent number: 8942840
    Abstract: A system and method for manufacturing semiconductor devices is disclosed. An embodiment comprises using desired device parameters to choose an initial manufacturing recipe. Once chosen, the initial manufacturing recipe may be modified by determining and applying an offset adjustment based on previous manufacturing to tune the recipes for the particular equipment to be utilized in the manufacturing process.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Long Chen, Hui-Yun Chao, Chia-Tong Ho
  • Patent number: 8937355
    Abstract: Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: January 20, 2015
    Assignee: International Business Machines Corporation
    Inventors: Choongyeun Cho, Daeik Kim, Jonghae Kim, Moon J. Kim, Jean-Olivier Plouchart, Robert E. Trzcinski
  • Patent number: 8938314
    Abstract: A method for optimizing energy efficiency in a manufacturing process includes monitoring power consumption of each of a plurality of manufacturing entities of the manufacturing process using a power metering device assigned thereto; collecting, from the power metering devices, a first data stream that includes information about the power consumption; collecting a second data stream that includes information about the manufacturing entity and process; determining an optimized product routing of products to be manufactured by the manufacturing process from one manufacturing entity to another manufacturing entity, based on the collected first and second data streams, by simulating different product routings and determining the optimal product routing with respect to the overall energy consumption of the manufacturing process; and adjusting, via a manufacturing control system, the manufacturing process based on the optimized product routing.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: January 20, 2015
    Assignee: International Business Machines Corporation
    Inventor: Rainer K. Krause
  • Publication number: 20150012124
    Abstract: The present disclosure provides a maintenance system, installed in a substrate processing device, is comprised of an equipment control unit, a sensor acquisition unit and determination unit and control signal generation unit. The equipment control unit operates the monitored equipment within the substrate processing device. The sensor acquisition unit and determination unit can detect when a person has entered the substrate processing device. The control signal generation unit outputs a signal to stop the monitored equipment when a person is detected within the substrate processing device.
    Type: Application
    Filed: September 24, 2014
    Publication date: January 8, 2015
    Inventor: Tsutomu HIROKI
  • Publication number: 20150011091
    Abstract: Provided is a substrate processing method of filling a recess of a predetermined uneven pattern formed on a substrate with a film forming material by performing a first film forming processing, a first etching processing and a second film forming processing on the substrate, using a vertical substrate processing apparatus and a control apparatus controlling operations of the vertical substrate processing apparatus. The method includes calculating a first film forming condition, a first etching condition, and a second film forming condition by the control apparatus such that the film forming material is filled in the recess without any void after the second film forming processing; and performing the first film forming processing, the first etching processing and the second film forming processing on the substrate based on the calculated first film forming condition, first etching condition and second film forming condition.
    Type: Application
    Filed: July 1, 2014
    Publication date: January 8, 2015
    Inventors: Yuichi Takenaga, Katsuhiko Komori
  • Publication number: 20150011088
    Abstract: Methods are disclosed for depositing material onto and/or etching material from a substrate in a surface processing tool having a processing chamber, a controller and one or more devices for adjusting the process parameters within the chamber. The method comprises: the controller instructing the one or more devices according to a series of control steps, each control step specifying a defined set of process parameters that the one or more devices are instructed to implement, wherein at least one of the control steps comprises the controller instructing the one or more devices to implement a defined set of constant process parameters for the duration of the step, including at least a chamber pressure and gas flow rate through the chamber, which duration is less than the corresponding gas residence time (Tgr) of the processing chamber for the step.
    Type: Application
    Filed: February 27, 2013
    Publication date: January 8, 2015
    Inventors: Mark Edward McNie, Michael Joseph Cooke, Leslie Michael Lea
  • Patent number: 8925190
    Abstract: It is intended to provide an electronic component mounting device and an operation performing method for mounting electronic components so that both the operation quality and the productivity can be improved. In operation performing procedures, when an electronic component belongs to the first division, an operating head is made to move up and down based on an approximate operation position height derived from an approximate curved surface of the top surface of a board which is calculated by using the height measurement result obtained by measuring a plurality of height measuring points on the surface of the board, and when the electronic component belongs to the second division, the operating head is made to move up and down based on an individual operation position height obtained by individually measuring the board height at the operation position.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: January 6, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Tadashi Endo, Hiroshi Ogata, Tomohiro Kimura, Takaaki Yokoi