Abstract: Provided is a simulation technique that allows the program verification to be more efficiently performed. A simulation system includes: a simulator that executes simulation of an operation of one or more devices; a data input unit that obtains one or more execution times in the simulation, positional information of each one of objects in the simulation, and a value of each one of one or more variables referred to by a program to operate the devices; a data recorder that stores, as a first log, positional information of the objects and value of the variables for each of the one or more execution times in a manner that positional information and value are associated with each other; and a displayer that displays positional information of the objects and value of the variables for each of the one or more execution times included in first log.

Abstract: A method for estimating a status of a system includes performing independent measurements on the system, associating a value P(?) with a Monte Carlo calculated probability measure P(?), which depends on (1) a preset threshold Nu of unfavorable events, and (2) a total number Ñtot(?) of the independent measurements for collecting the preset threshold Nu, setting a threshold level ? requiring that a critical value ?c of a power related metric ? makes a value P(?c) of the probability measure P to be substantially equal to the threshold level ?, comparing the total number Ñtot(?) to a ratio of (1) a product of a control parameter ? the preset threshold Nu, and (2) the threshold level ?, and interrupting the independent measurements if Ñtot(?) is larger than the ratio, or increasing an output of the system if Ñtot(?) is smaller than or equal to the ratio.

Abstract: An approach is disclosed herein for dynamic design switching for high performance mixed signal simulation. Disclosed herein is a new approach to simulation processes that allows for different segments of a design to be swapped out without requiring re-elaboration. This is an improvement over current techniques and decreases the amount of time need to simulate a design. In some embodiments, the technique illustrated herein is combined with an automated triggering mechanism that controls the selection of alternate representations for the same element base on those triggers. In some embodiments a new multiplexor structure is provided that is specifically tailored to solving the present issue.

Abstract: A Multi-Phase Simulation Environment (“MPSE”) is provided. In one embodiment, a simulation environment controller is configured to select a waveform from a waveform playlist and initiate a trigger signal to one or more waveform generators of a plurality of waveform generators to generate the waveform. The plurality of waveform generators are configured to generate the waveform under a phase lock.

Abstract: A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.

Abstract: Embodiments include herein are directed towards a system and method for estimating glitch power associated with an emulation process is provided. Embodiments may include accessing, using a processor, information associated with an electronic design database and generating cycle accurate waveform information at each node of a netlist based upon, at least in part, a portion of the electronic design database. Embodiments may further include generating a probability-based model for a plurality of inputs associated with the netlist and determining one or more partial glitch transitions from each probability-based model. Embodiments may also include combining the one or more partial glitch transitions with the cycle accurate waveform information to obtain a glitch power estimation.

Abstract: System for Knowledge Creation with the Living Machine for the Manufacture of Living Knowledge where Living Trust is being built and advanced.

Abstract: Disclosed are methods, systems, and non-transitory computer-readable medium for a contextual transformation of an analytical model for an industrial internet of things (IIoT) edge node. For instance, the method may include receiving the analytical model from a cloud service; obtaining local data of the IIoT edge node; analyzing the local data to determine a situational context of the IIoT edge node; determining whether to transform the analytical model based on a fit between the analytical model and the situational context; and in response to determining to transform the analytical model, transforming the analytical model based on the situational context to derive a transformed analytical model.

Abstract: A Multi-Phase Simulation Environment (“MPSE”) is provided which simulates the conductor current and voltage or electric field of multiple phases of an electrical power distribution network to one or more sensing or measuring devices and includes independent control of wireless network connectivity for each sensing or measuring device, independent control of GPS RF to each device, and interface to a back-end analytics and management system.

Abstract: The technology disclosed relates to verifying metastability for a clock domain crossing (CDC) in a circuit design. The technology disclosed may include, for a destination clock domain in the circuit design, creating a circuit graph based, at least in part, on the circuit design. The circuit graph includes start points and stop points. The start points may be data inputs, clocks, and enables of the destination clock domain. The stop points may be synchronizer outputs of the destination clock domain and a source clock domain in the circuit design. The technology disclosed may also include traversing the circuit graph to mark all graph nodes that reside in a source-destination path of the CDC. Based on the marked graph nodes, the start points, and the stop points, the technology disclosed may also include propagating destination domain qualifiers on the circuit graph within an allowed sequential depth.

Abstract: Apparatus and associated methods relate to authenticating a back-to-front-built configuration image. In an illustrative example, a circuit may include memory configured to store a signature S, a second hash H2, and a first data chunk C1. Signature S may be signed on a first hash H1. H1 may be the hash for H2 and C1. If signature S passes verification, a hash engine may perform hash functions on C1 and H2 to generate a hash H1?. H1? may be compared with H1 to indicate whether C1 has been tampered with or not. By using the incremental authentication, a signature that appears at the beginning of the image may be extended to the entire image while only using a small internal buffer. Advantageously, internal buffer may only need to store two hashes Hi, Hi+1, and a data chunk Ci, or, a signature S, a hash Hi, and a data chunk Ci.

Abstract: An emulation processor may be configured to support emulating unknown binary logic based on non-arbitrariness of the unknown binary logic. For example, an unknown binary logic signal may take the finite binary values of 0 and 1. The circuitry in the emulation processor is configured to generate and propagate outputs based on the interactions of known input binary signals with the unknown input binary signals having non-arbitrary states. The emulation processor may support the both combinational and sequential operations associated with the unknown binary logic.

Abstract: A Multi-Phase Simulation Environment (“MPSE”) is provided which simulates the conductor current and voltage or electric field of multiple phases of an electrical power distribution network to one or more sensing or measuring devices and includes independent control of wireless network connectivity for each sensing or measuring device, independent control of GPS RF to each device, and interface to a back-end analytics and management system.

Abstract: A method, system, and apparatus provide the ability to design a circuit. A behavior of the circuit is authored by dragging nodes from side panels and connecting them in an authoring canvas. Multiple circuit designs that satisfy the behavior are generated. A data grid table is generated and displays the circuit designs with each row representing a design, and the table is sortable based on columns that represent computed metrics. Upon selection of a design in the table, a computer generated circuit diagram is rendered. Interactive assembly instructions are generated and displayed. The interactive assembly instructions provide a text-based step-by-step guide to wire the circuit. Further, upon selection of an assembly instruction step, a corresponding element in the computer generated circuit diagram is highlighted.

Abstract: Disclosed are methods, systems, and non-transitory computer-readable medium for a contextual transformation of an analytical model for an industrial internet of things (IIoT) edge node. For instance, the method may include receiving the analytical model from a cloud service; obtaining local data of the IIoT edge node; analyzing the local data to determine a situational context of the IIoT edge node; determining whether to transform the analytical model based on a fit between the analytical model and the situational context; and in response to determining to transform the analytical model, transforming the analytical model based on the situational context to derive a transformed analytical model.

Abstract: An embedded logic analyzer of an integrated circuit includes a comparison block configured to generate a capture data signal and a plurality of comparison enable signals based on an input data signal from one of function blocks included in the integrated circuit such that the comparison enable signals are activated respectively based on different comparison conditions; an operation block configured to perform a logic operation on the comparison enable signals to generate a data enable signal indicating a data capture timing; and packer circuitry configured to generate a packer data signal including capture data and capture time information based on the capture data signal, the data enable signal and a time information signal.

Abstract: A method for implementing a distributed hardware system includes retrieving a hardware design described in a hardware description language, where the hardware design includes a plurality of modules. The method includes sending modules of the design to software engines, where the runtime software maintains for each module being simulated an update queue and evaluate queue. The update queue contains events that update stateful objects in the module and cause evaluation events to be enqueued onto the evaluate queue, while the evaluate queue contains evaluate events that update stateless objects and cause update events to be enqueued onto the update queue. Having a update and evaluate queues for each module permits the runtime to manage module simulations so that the executions of each module run concurrently with each other.

Abstract: Systems and methods for generating design verification test cases using a restricted randomization process are provided. According to one embodiment, a processor of a hardware design verification system receives a set of restrictions and defines a scenario involving the values that is to be excluded from the test case. The processor also receives pre-assigned values for one or more variables. For each variable other than the one or more variables, the processor assigns a first random value to the variable that is within a valid range for the variable. The processor then identifies a conflict between a first pair of variables, and resolves the conflict by assigning a second random value to a first variable or a second variable of the first pair of variables within their respective valid ranges.

Abstract: Techniques for performing a database search using a rewritten and annotated query are disclosed herein. In example embodiments, a profile lexicon is generated from a set of raw user profiles. A click-through lexicon is generated from a raw query log. A machine-learning model is trained for entity prediction using selected data. Query tagger data is generated using the profile lexicon, the click-through lexicon, and the machine-learning model. A raw query is received. The raw query is rewritten as an annotated query based on the generated query tagger data. A search of a database is performed using the annotated query. Results of the search are returned in response to the receiving of the raw query for presentation in a user interface.

Abstract: Using a high-level language (HLL) callable library for multiple instances of a core includes detecting, using computer hardware, a reference to an HLL library for a core within an HLL application, determining, using the computer hardware, a plurality of instances of the core by detecting function calls within the HLL application correlated to each of the plurality of instances of the core, and generating, using the computer hardware, interface code within the HLL application for each of the plurality of instances of the core using the HLL library. An executable version of the HLL application is generated, using the computer hardware, wherein the interface code for each of the plurality of instances of the core is bound to the respective instance of the core. The function calls can specify different parameterization files corresponding to the plurality of instances of the core.

Abstract: A child component ID module identifies child components connected to a parent component in response to selection of the parent component for placement on a PCB. The child components identified from component connections of a logic design. A child placement module places the child components around the parent component after placement of the parent component, where each child component is placed in compliance with constraints of the child components. A constraint highlight module identifies, on a PCB layout, an allowable area for component placement and prohibited areas for non-placement after selection of the component. The component is a parent component or a child component identified from component connections of a logic design of an electronic circuit design. The apparatus includes a constraint de-highlight module that removes identification on the PCB layout of the allowable area and the one or more prohibited areas in response to placement of the component.

Abstract: A computer-implemented method for manufacturing an integrated circuit chip is disclosed. The method includes selecting cell-based circuit representations to define an initial circuit design. The initial circuit design is partitioned into multiple sub-design blocks to define a partitioned design. Circuit representations of local clock sources are inserted into the partitioned design. Each local clock source is for clocking a respective sub-design block and based on a global clock source. A timing analysis is performed to estimate skew between each local clock source and the global clock source. The partitioned design is automatically modified based on the estimated skew.

Abstract: The invention is suited for use by a hardware designer for the purpose of logic synthesis and/or logic simulation. It can be used in the design of integrated circuits (ASICs) and programmable logic devices (PLDs), such as field-programmable gate arrays (FPGAs). The invention also relates to the field of hardware description languages (HDLs). Embodiments of the invention provide a computer-implemented system and method for facilitating the design of a digital circuit which comprises a plurality of logical constructs. The system is configured such that each time each logical construct is executed during a software simulation pass it is associated with a unique tag, wherein each tag can correspond to a physical aspect of a hardware representation of the design. The simulation is performed by repeated execution passes through code which implements the design, preferably wherein the same tags are associated with corresponding executions of the logical constructs during different simulation passes.

Abstract: The independent claims of this patent signify a concise description of embodiments. Each component of a testbench configured to test a DUT is associated at compile time with a different hardware transactor. The testbench is partitioned at compile time into a plurality of independent partitioned testbenches, where each independent partitioned testbench comprises at least one component of the testbench. At run time, each of the plurality of partitioned testbenches is simulated in parallel. The simulating of a partitioned testbench includes execution of its at least one component on its at least one associated hardware transactor using the hardware emulation system. This Abstract is not intended to limit the scope of the claims.

Abstract: A method for verification of a design of an electronic circuit is provided. The method includes executing test runs of the design. The method further includes increasing a fail counter if the executing of a test run of the test runs failed. The method further includes increasing a pass counter if the executing of the test run of the test runs passed. The method further includes halting the executing of the test runs of the design if the current ratio of the fail counter versus the pass counter exceeds a predetermined threshold.

Abstract: Provided are a method of generating a functional coverage model from a hardware description language (HDL) code for a circuit design and performing verification of the circuit design by using the functional coverage model, and a computing system in which the method is performed.

Abstract: Techniques and systems for solving a Boolean satisfiability (SAT) problem are described. Specifically, embodiments solve the SAT problem by generating an extended resolution proof. It is well-known that many technological problems can be modeled as SAT problems, and that solving an underlying SAT problem effectively solves the original technological problem. Therefore, embodiments described herein can be used to solve any technological problem that can be modeled as a SAT problem.

Abstract: An integrated circuit having an integrated logic analyzer can include a match circuit including at least one match cell, wherein each match cell is programmable at runtime to detect a signal state from a plurality of signal states for a probed signal. The integrated circuit can include a combine circuit configured to generate a first match signal indicating an occurrence of a first trigger condition based upon the detected signal state of each match cell, a capture and control circuit configured to determining addressing for storing trace data corresponding to the probed signal, and a trace storage memory configured to the store trace data at addresses determined by the capture and control circuit.

Abstract: A system and method for hardware implementations of policy-based secure computing environments for Internet enabled devices. The present invention facilitates a secure computing environment for any Internet enabled device where policy rules can be described as hardware components that allow or deny access to resources on the device. A compiler produces a hardware description language (HDL) of the hardware components based on given policy rules for that component. The system may be partially or completely implemented in hardware to address inherent limitations of a software only solution. The invention provides greater flexibility to the overall system in terms of performance, security, and expressiveness of the policy rules that must be executed.

Abstract: A method for verification of a design of an electronic circuit is provided. The method includes executing test runs of the design. The method further includes increasing a fail counter if the executing of a test run of the test runs failed. The method further includes increasing a pass counter if the executing of the test run of the test runs passed. The method further includes halting the executing of the test runs of the design if the current ratio of the fail counter versus the pass counter exceeds a predetermined threshold.

Abstract: A database is constructed based on a batch PBA performed on a plurality of paths of an integrated circuit. A local PBA is performed on a portion of a selected path. A selected optimization move is identified on the portion of the selected path, based on a result of the local PBA that best meets a set of constraints. A path-wide PBA is performed for an updated path that is based on the selected path incorporating the selected optimization move. The selected optimization move is committed in a netlist associated with the integrated circuit.

Abstract: Systems and methods for performing asynchronous input/output (I/O) operations. An example method comprises: initializing a list of sockets that are ready for performing I/O operations; traversing the list of sockets, wherein a traversal operation of the list includes, for each socket referenced by the list: performing I/O operations using the socket, updating a state flag associated with the socket to reflect a state of the socket, updating one or more observed I/O performance statistics of the socket; and responsive to detecting less than a threshold number of I/O operation errors during the traversal operation, updating the list of sockets based on updated endpoint state flags and observed I/O performance statistics.

Abstract: The inertia system provides a common platform and application-programming interface (API) for applications to extend the input received from various multi-touch hardware devices to simulate real-world behavior of application objects. To move naturally, application objects should exhibit physical characteristics such as elasticity and deceleration. When a user lifts all contacts from an object, the inertia system provides additional manipulation events to the application so that the application can handle the events as if the user was still moving the object with touch. The inertia system generates the events based on a simulation of the behavior of the objects. If the user moves an object into another object, the inertia system simulates the boundary characteristics of the objects. Thus, the inertia system provides more realistic movement for application objects manipulated using multi-touch hardware and the API provides a consistent feel to manipulations across applications.

Abstract: Solutions for integrating manufacturing feedback into an integrated circuit design are disclosed. In one embodiment, a computer-implemented method is disclosed including: defining an acceptable yield requirement for a first integrated circuit product; obtaining manufacturing data about the first integrated circuit product; performing a regression analysis on data representing paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data; determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement; and modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings.

Abstract: Embodiments of the present disclosure provide a method, a system and a computer readable storage medium for circuit simulation, comprising: partitioning circuit into a subcircuit-1 and a subcircuit-2 which are connected through at least one port; generating equivalent circuit of subcircuit-1 based on port current/port voltage, subcircuit-1 port voltage under port open-circuit condition/subcircuit-1 port current under port short-circuit condition, and impulse-response of subcircuit-1 port voltage to port current/impulse-response of subcircuit-1 port current to port voltage; simulating a simplified circuit comprising the subcircuit-2 and the equivalent circuit. Comparing with prior art, this disclosure reduces circuit scale by equivalence of linear portion of circuit. Thereby computation amount for circuit simulation is reduced and the computation time for circuit simulation is shortened.

Abstract: A circuit device includes an oscillation circuit that generates an oscillation signal by using an resonator, a clocking circuit that generates clocking data which is real-time clock information based on the oscillation signal, a verification data generation circuit that generates verification data for verifying the clocking data based on the oscillation signal, and an interface circuit that outputs the clocking data and the verification data.

Abstract: A first circuit design description may have registers and combinational gates. Circuit design computing equipment may perform register retiming on the first circuit design description, whereby registers are moved across combinational gates during a first circuit design implementation. An engineering-change-order (ECO) of the first circuit design may result in a second circuit design. The differences between the first and second circuit designs may be confined to a region-of-change. The circuit design computing equipment may preserve the results from the first circuit design implementation and re-use portions of these results during the implementation of the second circuit design.

Abstract: Systems and methods are described for creating a netlist abstraction that provides full-chip context for performing circuit design floorplanning. The netlist abstraction can include a top-level netlist abstraction that corresponds to the top-level portion of the netlist, and a physical block netlist abstraction for each physical block in the circuit design. Each physical block netlist abstraction can retain macros that are in the physical block.

Abstract: Methods, systems, and computer-readable storage media for receiving data representative of the temporal graph, the data representing vertices, edges between vertices, and temporal features, determining a set of earliest-arrival dependencies, each earliest arrival dependency including an earliest feasible edge between vertices from a list of edges of the temporal graph, providing data representative of an edge-scan-dependency graph (ESD-graph) based on the data representative of the temporal graph, and the set of earliest-arrival dependencies, the ESD-graph including vertices representing edges of the temporal graph, and edges representing earliest-arrival dependencies between vertices, providing data representative of a level-assigned ESD-graph including a level assigned to each vertex of the ESD-graph, and determining earliest-arrival times between a source vertex, and each vertex of the temporal graph by executing a parallel edge scan of the level-assigned ESD-graph.

Abstract: A method for designing a system on a target device includes performing speculative register retiming with speculative changes made to a design of the system after an initial compilation of the design. A strategy is generated for an actual register retiming in response to user specified preferences on the speculative changes.

Abstract: A power verification system requires a combination of design and its power intent. A power intent (PI) input specifies the power architecture of a design through specification of power/voltage domains, their corresponding power supplies and a collection of power management devices. Power state tables (PSTs) specified in PI capture the legal combinations of power states (voltage values) for the various sets of supply nets or supply ports of a design. A power verification system requires determining the power supply relationships of voltage/power domains which requires merging of PSTs. The system described efficiently merges PSTs by iteratively selecting only a subset of PSTs that are relevant to the supply pair of interest, that are pruned initially and as the merge progresses. This provides orders of magnitude speedup and resource reduction.

Abstract: An approach is provided in which an information handling system creates a printed circuit board (PCB) layout based upon a set of packaged components. The information handling system modifies the PCB layout based upon an adjustment of the set of packaged components and generates board design data based on the modified PCB layout. In turn, the information handling system simulates the PCB layout using the board design data.

Abstract: In one embodiment of the present invention, a thread is scheduled for execution by a processor, and the thread includes instructions for testing functionality of a feature of the processor. A workload location on the thread is determined. A hook is placed on the determined workload location. The thread is executed by the processor. In response to encountering the hook during the execution of the thread, a workload is selected from a pool, and the pool includes two or more workloads.

Abstract: A method performed by a processor, the method including preparing a netlist describing a first circuit including an active component; obtaining an original electrical characteristic of the active component, wherein an electrical characteristic of the active component is the original electrical characteristic in a condition that the active component has not been operated; obtaining an aged data describing a variation in the original electrical characteristic, wherein the variation is caused by operating the first circuit under a first mode and a second mode different from the first mode during a time period; providing a simulation result by simulating, based on an aged electrical characteristic, the first circuit operating under the first mode and the second mode during the time period, wherein the aged electrical characteristic is a combination of the original electrical characteristic and the variation.

Abstract: The present invention relates to a simulation method and device. According to the present invention, a simulation method using a plurality of blocks comprises: a dividing step of dividing a simulation into computation operations for performing unique operations on the blocks and communication operations for data exchanges between different blocks; a grouping step of performing a grouping between the interdependent computation and communication operations; and a simulation performing step of performing an operation included in each group using the blocks according to whether or not the level of interdependency between the computation and communication operations is resolved.

Abstract: A method includes identifying a design area for a microelectronic device, where the design area includes a plurality of sub-units, each sub-unit from the plurality of sub-units capable of receiving a control signal. The method places a central latch in a center of the design area, where the central latch presents a connection point on a first level of the design area. Responsive to determining a sub-unit of the plurality of sub-units does not include a latch, the method creates a horizontal and vertical axis through the central latch, where the horizontal and vertical axis are bound by a perimeter of the design area. The method places a first set of latches for tiles created by the horizontal axis and the vertical axis on a second level of the design area, where each latch of the first set of latches is placed in a center of a single tile.

Abstract: A design efficiency is improved by enabling existing design resources to be utilized.

Abstract: A method for verification of a design of an electronic circuit is provided. The method includes executing test runs of the design. The method further includes increasing a fail counter if the executing of a test run of the test runs failed. The method further includes increasing a pass counter if the executing of the test run of the test runs passed. The method further includes halting the executing of the test runs of the design if the current ratio of the fail counter versus the pass counter exceeds a predetermined threshold.

Abstract: A system, method, and computer program product for modeling a receiver load in static timing analysis of digital circuits. Embodiments separate total receiver charge into static and dynamic components, and extract both from an improved library model. The receiver load is effectively modeled with a static capacitance and a current source connected in parallel. A method of extracting load model characteristics from a standard timing library is also provided. The improved receiver model reflects the physical phenomena not currently modeled, and enables a more accurate description of circuit behavior while still using a simple approximation of the transistor level circuit. The complete circuit switching response is found through a perturbative approach, combining a linear response using constant capacitance values with a correction having time-dependent charges for modeling physical phenomena such as the back-Miller effect.

Abstract: A method for designing a system on a target device is disclosed. The system is synthesized. The system is partitioned into a plurality of logical sections utilizing information derived from synthesizing the system and prior to performing placement of the system on the target device. Other embodiments are described and claimed.