Abstract: A computer-implemented method for interconnect redundancy of a circuit design comprises the steps of setting Manhattan distance being less than or equal to three pitches; placing a plurality of dummy micro bumps on at least one side of a die including a signal bump formed on the at least one side; determining an interconnecting candidate by selecting from the dummy micro bumps, which is distant from the signal bump by the Manhattan distance; and providing a routing path between the at least one interconnecting candidate and the signal bump.

Abstract: A method for implementing a single file format for power-related information for an IC comprising: providing a circuit design in at least one design file in a non-transitory computer readable storage device; providing power-related design information in a file in the computer readable storage device that is separate from the at least one design file and that specifies multiple power domains within the circuit design, each power domain including one or more design object instances from within the circuit design and that specifies multiple power modes each power mode corresponding to a different combination of on/off states of the multiple specified power domains and that specifies isolation behavior relative to respective power domains; and using a computer to add power control circuitry to the circuit design that implements the power domains and power modes and isolation behavior specified in the power specification information.

Abstract: The invention relates to a method and a system for repartitioning a formalized hardware description of a hierarchically structured electronic circuit design unit comprising a plurality of macros in terms of latch macros and combinatorial macros. In a first step, each macro is dissected into latch macros and signal cones in such a way that each signal cone comprises signals linking macro input/output to a latch output/input, and each latch macro comprises at least one latch, each primary input an output of said latch macro coinciding with an input or an output of a latch within said latch macro. Subsequently, combinatorial macros are created by merging combinatorial signal cones along unit signal paths.

Abstract: A relational database may be integrated into an integrated circuit design and analysis environment as the persistent data store for data associated with the design. This design data may include two or more abstractions of the design, such as layout data models and timing data models, in some embodiments. Design data may be partitioned in the database and indexed according to various attributes. The use of a relational database may facilitate cross-probing of design data corresponding to different abstractions of the design. The relational database may be queried to produce design reports and to identify design errors or weaknesses. Reports may be graphical or tabular, and may be displayed, printed, stored, or posted for viewing. Proposed modifications to a design may be investigated by modifying data in the relational database, rather than in the actual design. Design reports may be re-generated and compared with corresponding reports for the un-modified design.

Abstract: A transaction level (TL) system power estimation method and system are provided. The method includes inserting at least a characteristic extractor into an electronic device of a target system. The characteristic extractor extracts at least a power characteristic of the electronic device when a TL simulation is proceeding. The power characteristic provided from the characteristic extractor is converted to at least a power consumption value by using a power model. The power consumption value is recorded into a power database, for analyzing power consumption of the whole target system. In some embodiments, the TL system power estimation method and system can be applied in the target system with dynamic power management. The TL system power estimation method and system also can be used with a high-level synthesizer to develop the power-aware electronic device in a short time.

Abstract: A simulation apparatus that performs simulation of design data of a verification target circuit including a logic circuit that operates as a multi-cycle path of N cycles in synchronization with a clock signal, the simulation apparatus includes a design data generation section that generates design data of a multi-cycle verification circuit for selectively providing an undefined value signal in place of a signal in a multi-cycle part in the verification target circuit; a logical simulation section that performs logical simulation, without delay, on the basis of design data of the verification target circuit and the design data of the multi-cycle verification circuit; and a comparison section that compares the signal of the verification target circuit with a signal of an expected value in the verification target circuit in the logical simulation.

Abstract: A method of preparing a set of target layout data for the application of a photolithographic friendly design (LFD) analysis or other photolithographic analysis. The target layout data is revised to remove areas or features prior to performing the LFD analysis. The features removed include features that have been determined to print correctly, duplicate features and features that are not sensitive to variations in process conditions. The revised target layout is analyzed to determine if the features that remain will print correctly on a wafer.

Abstract: As to a plurality of components in a system, a state transition path covering transitions defined by a behavioral specification of a component is specified to satisfy an input restriction of the component. Action sequences are acquired from the state transition path. By selecting a pair of components connected in the system, it is verified whether an output action sequence of a first component as one of the pair satisfies an input restriction of a second component as the other of the pair. If unsatisfied, the input restriction of the second component is relaxed to satisfy the output action sequence of the first component, or an input restriction of the first component is tightened to acquire a new output action sequence satisfying the input restriction of the second component. Above processing is repeated for each pair of components, so that output action sequences of one and the other of a pair satisfies input restrictions of the other and the one of the pair respectively.

Abstract: A method and an apparatus for tracking uncertain signals in the simulation of chip design are provided. The method comprises: generating a directed graph which contains sequential logic devices and IO devices from the netlist of chip design, wherein the directed graph illustrates the signal association among the sequential logic devices and IO devices; obtaining the signals related with the sequential logic devices and IO devices from the simulation results, wherein the signals contain a plurality of uncertain signals; and back tracing at least a part of the plurality of uncertain signals along the directed graph to determine the device which firstly generates an uncertain signal. The corresponding apparatus is also provided. With the above method and apparatus, uncertain signals can be traced and their source can be determined, which improves the debugging efficiency.

Abstract: A method for designing a system on a target device is disclosed. Extraction is performed on a first version of the system during synthesis in a first compilation resulting in a first netlist. Optimizations are performed on the first version of the system during synthesis in the first compilation resulting in a second netlist. Placement and routing are performed on the first version of the system in the first compilation. Extraction is performed on a second version of the system having a changed portion during synthesis in a second compilation resulting in a third netlist. The first version of the system in the first netlist and the second version of the system in the third netlist are differentiated to identify identical regions, wherein at least one of the performing and differentiating is performed by a processor.

Abstract: The compositional event based modeling of integrated applications (CINEMA) tool provides a way to extend a modeling environment using legacy event based applications, such as Graphical User Interface (GUI) APplications (GAPs). CINEMA allows modelers to extend the toolbox of the modeling environment by creating modeling elements that represent GUI objects of GAPs. CINEMA generates source code that allows an integrated system to control and manipulate the GUI objects of GAPs represented by the modeling elements used to create a model of the integrated system.

Abstract: A mechanism is provided in an integrated circuit simulator for tracking array data contents across three-value read and write operations. The mechanism accounts for write operations with data values and address values having X symbols. The mechanism performs writes to a tree data structure that is used to store the three-valued contents to the array. The simulator includes functionality for updating the array contents for a three-valued write and to read data for a three-valued read. The simulator also includes optimizations for dynamically reducing the size of the data structure when possible in order to save memory in the logic simulator.

Abstract: Software for controlling processes in a heterogeneous semiconductor manufacturing environment may include a wafer-centric database, a real-time scheduler using a neural network, and a graphical user interface displaying simulated operation of the system. These features may be employed alone or in combination to offer improved usability and computational efficiency for real time control and monitoring of a semiconductor manufacturing process. More generally, these techniques may be usefully employed in a variety of real time control systems, particularly systems requiring complex scheduling decisions or heterogeneous systems constructed of hardware from numerous independent vendors.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for emulating a mass storage device and a file system of a mass storage device. In a first aspect, a human-portable data processing device that includes one or more data processors that perform operations in accordance with machine-readable instructions, an incoming message classifier configured to classify an incoming read command according to an address of the data requested by the incoming read command, and an emulation data generation component connected to respond to the classification of the incoming read command by the incoming message classifier to generate emulation data emulating that which would have been read by the incoming read command were the human-portable data processing device a mass storage device; and a bus controller configured to respond to the incoming read command with the emulation data generated by the emulation data generation component.

Abstract: Mechanisms are provided for controlling a fidelity of a simulation of a computer system. A model of the system is received that has a plurality of components. A representation of the plurality of individual components of the system is generated. A component is assigned to be a fidelity center having a highest possible associated fidelity value. Fidelity values are assigned to each other component in the plurality of individual components based on an affinity of the other component to the fidelity center. The system is simulated based on assigned fidelity values to the components in the plurality of individual components.

Abstract: Methods and apparatuses for designing at least one integrated circuit (IC). In one embodiment, the method comprises partitioning a circuit into portions that represent a partitioning solution and assigning traces to interconnect the portions to generate a trace assignment solution. The method further comprises optimizing the circuit through a modification of at least one of the partitioning solution and the trace assignment solution, the optimizing based on evaluating a design parameter which is based at least in part on the trace assignment solution.

Abstract: Various embodiments related to identifying regions including physical defects in semiconductor devices are disclosed. For example, one embodiment includes receiving an electrical test mismatch reported for a scan chain; identifying a suspect logical region including a plurality of logic cones electrically connected with the scan chain; adjusting a scope of the suspect logical region by simulating data flow within the logic cones, generating simulated scan chain output based on the simulated data flow within the logic cones, and excluding at least one of the logic cones from the suspect logical region based on a comparison of the electrical test mismatch and the simulated scan chain output; after adjusting the scope of the suspect logical region, generating a candidate defect region, the candidate defect region being defined to include physical instantiations of logical cells and logical interconnections included in the suspect logical region; and displaying the candidate defect region.

Abstract: Estimating the latency time of the clock tree of an ASIC including: providing a netlist and a placement related to the clock tree of the ASIC; extracting a number of the load timing devices connected by the clock tree according to the netlist related to the clock tree; extracting a physical distribution area of the load timing devices connected by the clock tree according to the placement related to the clock tree; estimating a latency time of the clock tree according to the relationship between the number of the load timing devices, the physical distribution area of the load timing devices and latency time of the clock tree in design data related to the ASIC design.

Abstract: Methods and systems for modeling a multiprocessor system in a graphical modeling environment are disclosed. The multiprocessor system may include multiple processing units that carry out one or more processes, such as programs and sets of instructions. Each of the processing units may be represented as a node at the top level of the model for the multiprocessor system. The nodes representing the processing units of the multiprocessor system may be interconnected to each other via a communication channel. The nodes may include at least one read element for reading data from the communication channel into the nodes. The node may also include at least one write element for writing data from the nodes into the communication channel. Each of the processing unit can communicate with other processing unit via the communication channel using the read and write elements.

Abstract: Disclosed are improved methods, systems, and computer program products for implementing an I/O ring structure to generate an I/O ring arrangement for an electronic design, and for performing chip planning and estimation based upon the I/O ring arrangement. Nodes in the I/O ring structure are used to track objects in the I/O ring.

Abstract: Methods, circuits, and systems for converting reset mechanisms in a synchronous circuit design into a corresponding asynchronous representation are described. These may operate to convert synchronous state holding blocks that include reset signals to corresponding asynchronous dataflow logic blocks. A replicated reset token at a fraction of the operational frequency of the reset signal may be distributed to the locations of the asynchronous dataflow logic blocks. Additional methods, circuits, and systems are disclosed.

Abstract: A exemplary aspect of the present invention is a simulation method for a semiconductor circuit that includes: a semiconductor resistor; a plurality of contacts arranged at regular intervals in a longitudinal direction and in a width direction of the semiconductor resistor on a terminal region of the semiconductor resistor; and a wiring line formed on the plurality of contacts, the simulation method including: defining a ratio of a parasitic-resistance by the semiconductor resistor between two of the contacts neighboring in the longitudinal direction to a resistance of one of the plurality of contacts as a constant k; and modeling a parasitic-resistance net by using the constant k, the parasitic-resistance net including the terminal region of the semiconductor resistor and the plurality of contacts.

Abstract: A simulation parameter extracting method of a MOS transistor according to an exemplary aspect of the present invention includes evaluating a measured value that includes a true gate-overlap capacitance by measuring a capacitance between the gate and the drain in each of a plurality of layout patterns at a predetermined bias voltage, only the number of contact plugs being different for each layout pattern, evaluating a gate-overlap capacitance calculation value of each layout pattern by subtracting a contact parasitic capacitance between the contact plug and the gate from the measured value, the contact parasitic capacitance being obtained by a simulation with varying a model parameter for evaluating a parasitic capacitance between the contact plug and the gate, and extracting the gate-overlap capacitance calculation value as the true gate-overlap capacitance at the model parameter when the gate-overlap capacitance calculation value is about constant regardless of the number of the contact plugs.

Abstract: A method and semiconductor structure to avoid latch-up is disclosed. The method includes identifying at least one high voltage device on a semiconductor chip, identifying a circuit on the semiconductor chip separated from the identified at least one high voltage device by a guard ring, evaluating the circuit for a latch-up condition, and when the latch-up condition occurs, adjusting the contact-circuit spacing in the circuit.

Abstract: A system and method are described for converting a circuit description into transaction-based description at a higher level of abstraction. Thus, a designer can readily view a series of transactions that occurred in the simulation of a circuit. In one aspect, the simulated signals are analyzed and converted into messages of a protocol used by the design. A combination of the messages represents a transaction. Thus, the simulated signals are then converted into a series of protocol transactions. In another aspect, a message recognition module performs the analysis of the simulated signals and converts the simulated signals into messages (e.g., request for bus, bus acknowledge, etc.). A transaction recognition module analyzes the messages and converts the messages into transactions (e.g., Read, Write, etc.). Using both the system and method the circuit description is converted into a higher level of abstraction that allows more comprehensive system-level analysis.

Abstract: A method for designing masks adapted to the forming of integrated circuits, including the steps of: (a) forming a first test file including a set of configurations of integrated circuit elements; (b) forming a second test file comprising the elements of the first test file, less the elements corresponding to configurations forbidden by design rule manuals; (c) trans-forming the second test file by means of a set of logical operations implemented by computing means to obtain a mask file; (d) testing the mask file and, if the test is negative, modifying the design rule manuals; and (e) repeating steps (a) to (d) until the test of step (d) is positive.

Abstract: A method of increasing an initial threshold voltage (Vt) of selected devices. The method includes designing devices with desired antenna effects and adjusting an increase in Vt of some devices to specific values. The desired antenna effects produce a desired threshold voltage of the devices.

Abstract: A method of producing a hierarchical power information structure for a circuit design, the method comprising traversing a circuit design hierarchy from a top design level to a bottom design level to identify any intermediate design levels, associating identified power nets with ground nets to produce one or more power domains, producing one or more power domains using the identified power nets and ground nets, identifying an instance of one or more special cells that are associated with a power related property and creating constructs for the special cells in the hierarchical power information structure, generating power rules for the intermediate level design using the special cell constructs, mapping higher design level power domains to lower design level power domains within the intermediate design level, and storing the power domains and power rules as power intent within an information structure associated with a schematic for the intermediate level design.

Abstract: A leak current calculation apparatus includes an acquiring section for acquiring partial circuit information, and a grouping section for forming a plurality of groups each comprising a part of the partial circuits connected with each other and for generating group information. The apparatus includes a leak difference value calculating section for calculating a leak difference value, which is a difference between a provisional maximum value acquired by adding up the maximum values of the leak current values of all the partial circuits and a sum of maximum values of the leak current values contained in the group information of the groups, and a maximum leak current calculating section for calculating the maximum leak current value of the integrated circuit by adjusting the provisional maximum value with the leak difference value.

Abstract: A technique for reliably replaying operations in electronic-design-automation (EDA) software is described. In this technique, the EDA software stores operations performed by a user during a design session, as well as any replay look-ahead instructions, in a log file. When repeating the first operation, the replay look-ahead instruction ensures that the same state is obtained in the EDA environment as was previously obtained. For example, if an interrupt occurred when the first operation was previously performed, the replay look-ahead instruction may specify when the interrupt occurred during the performance of the operation so that the effect of the interrupt may be simulated when replaying the first operation.

Abstract: Systems and methods for testing a component by using encapsulation are described. The systems and methods facilitate communication between two components that use two different languages in a test environment. Such communication is allowed by encapsulating an identifier of a function to create a call message, encapsulating an identifier of an event to create an event message, or encapsulating an identifier of the function to create a return message.

Abstract: A verification tool receives a finite precision definition for an approximation of an infinite precision numerical function implemented in a processor in the form of a polynomial of bounded functions. The verification tool receives a domain for verifying outputs of segments associated with the infinite precision numerical function. The verification tool splits the domain into at least two segments, wherein each segment is non-overlapping with any other segment and converts, for each segment, a polynomial of bounded functions for the segment to a simplified formula comprising a polynomial, an inequality, and a constant for a selected segment. The verification tool calculates upper bounds of the polynomial for the at least two segments, beginning with the selected segment and reports the segments that violate a bounding condition.

Abstract: In one embodiment, a method is provided for determining a level of resilience of a circuit to single event upsets based on a layout of a circuit design. A set of locations in the layout of the circuit design is selected. A respective maximum level of linear energy transfer (LET) that is tolerable for each location in the selected set is determined. For each determined maximum level of LET, cross-section values at locations having the maximum level of LET are summed to determine a respective total cross-section value for the maximum level of LET. For each determined maximum level of LET, the total cross-section value is divided by the determined maximum level of LET to produce respective intermediate values. The respective intermediate values are summed to determine a level of resilience.

Abstract: Disclosed are improved methods, systems, and computer program products for generating an I/O ring arrangement for an electronic design, and for performing chip planning and estimation based upon the I/O ring arrangement.

Abstract: Disclosed is a behavioral synthesis apparatus for generating a test bench where the same test vector can be used in both the behavioral simulation and the RTL simulation. The apparatus includes input application/output signal observation timing signal generation means that generates an input application timing signal, an output observation timing signal, and logic circuits for the input application timing signal and the output observation timing signal; and test bench generation means that generates a test bench that observes the signals, applies inputs, and observes outputs.

Abstract: A verification system determines proof of the absence of a deadlock condition or other data-transport property in a multi-system SoC using helper assertions derived from a transaction definition. The verification system receives the circuit design information along with a transaction definition for one or more ports of the SoC. Once specified, the transaction definition is instantiated into the full system or subsystem RTL, generating an expanded RTL and a deadlock property. Data flow through the RTL is analyzed to extract helper assertions describing how the data flowed through the RTL. Helper assertions are automatically extracted to aid in the verification of the absence of a deadlock condition. Using the helper assertions, the formal engine applies one or more techniques to formally analyze the circuit design to prove the absence of a deadlock condition.

Abstract: Disclosed are embodiments of a method and program storage device for modeling the resistance of a multi-contacted diffusion region of a semiconductor device, such as a metal oxide semiconductor field effect transistor (MOSFET), a metal oxide semiconductor capacitor (MOS capacitor), a bipolar transistor, etc. The embodiments provide a formula for determining the total parasitic resistance (Rtot) of the diffusion region based on a sum of contributions of wire resistance, contact resistance, diffusion resistance and electric current flow from each of multiple partitions of the diffusion region. This formula allows the position of each dividing line separating adjacent partitions (i.e., between adjacent contacts) to be arbitrary. The embodiments adjust the position of each dividing line to minimize the total parasitic resistance (Rtot). This minimized total parasitic resistance (Rtot) value can then be used to more accurately model semiconductor device performance.

Abstract: Local clock modeling for a discrete event simulator is described. A local clock generator provides realistic clock characteristics in terms of clock precision and clock drift and clock mapping utilities provide API for other modules and/or protocols in the discrete event simulator to schedule events on local clocks instead of global clock of the simulator.

Abstract: An improved method and system for performing extraction on an integrated circuit design is disclosed. Extraction may be performed at granularities much smaller than the entire IC design, in which a halo is used to identify a geometric volume surrounding an object of interest to identify neighboring objects and generate an electrical model. The extraction approach can be taken for Islands, Nets, as well as other granularities within the design. Re-extraction of a design can occur at granularities smaller than a net. Some approaches utilize Island-stitching to replace an island within a net. An approach is also described for improving cross-references for cross-coupled objects.

Abstract: A method, system and computer program product for implementing enhanced clock tree distributions to decouple across N-level hierarchical entities of an integrated circuit chip. Local clock tree distributions are constructed. Top clock tree distributions are constructed. Then constructing and routing a top clock tree is provided. The local clock tree distributions and the top clock tree distributions are independently constructed, each using an equivalent local clock distribution of high performance buffers to balance the clock block regions.

Abstract: A dynamic reconfigurable interconnect network architecture in a logic simulation system that interconnects a plurality of simulation engines together, providing a high degree of interconnectivity in an efficient manner. The logic simulation system may create and manage linkable sub-programs for execution by a simulation engine. The logic simulation system may schedule various tasks in a design to be simulated, including horizontal and vertical partitioning of the design and determination of an order in which events such as clock edges and asynchronous signals are to be implemented by a logic simulation system.

Abstract: A method of assisting failure mode and effects analysis of a system having a plurality of components includes obtaining data associated with a component, or a group of components, of the system. The component or the group is associated with component type data or group type data, respectively, that includes data relating to at least one failure feature common to all components or groups, respectively, of that type. The component/group data and the component/group type data can then be stored and/or transferred for use in a failure mode and effects analysis of the system.

Abstract: Aspects of the present invention are directed to improving the speed of event-driven simulation by manipulating delta delays in a system model to reduce delta cycle executions. The manipulation is performed in a manner that preserves delta cycle accurate timing on selected signals of the system, which may be of interest to a designer. Methods and systems are provided for identifying the signals of interest, and for determining portions of the design that may have delta delays retimed. Preserving the timing on the signals of interest ensures that race conditions and glitches present in the design on the signals of interest are still viewable by the designer. To reduce simulation time, delta delays may be moved from high activity signals to low activity signals, the total number of delta delays may be reduced, or a number of processes executed may be reduced.

Abstract: The present invention is directed to a capacitive decoupling module and method for an integrated circuit that features providing multiple capacitive elements to decouple the power rails from the integrated circuit. The multiple capacitive elements are spaced-apart, along a first direction, from the integrated circuit. A first set of capacitive elements is closer to the integrated circuit than a second set of capacitive elements. The first set has a smaller capacitance than the second set.

Abstract: A computer-readable medium encoded with an instruction check program for making a computer to check a status of execution of an instruction by an I/O simulator that performs an operation simulation according to a structure of an I/O area of a microcomputer, the instruction check program when executed by a computer causes the computer to perform a method including obtaining specification information of the microcomputer describing an input and an output condition of a hardware resource in the I/O area, detecting a simulation of a reference instruction to the hardware resource executed by the I/O simulator, determining correctness of the reference instruction by comparing a content of the simulation of the reference instruction detected by the detecting with the input and output condition of the hardware resource included in the obtained specification information, and outputting an error signal when it is determined that the reference instruction is incorrect.

Abstract: A method for digital circuit design. The first step of the process is the step of providing a circuit design in the form of a hardware definition language. Then, the process produces a binary simulation of the design by setting out for each unit of time during execution of the hardware design the a control state and a program state of the design and assigns a symbol to each signal of the design. The process proceeds by executing a symbolic simulation of the design, concluding with identifying and capturing the combinational logic expression of the simulation output and the next state functions of the simulation.

Abstract: Iterative repair problems are generally solved using a combinatorial search method such as simulated annealing are addressed with a FPGA-based coarse-grain pipelined architecture to accelerate a simulated annealing based iterative repair-type event scheduling application. Over 99% of the work done by any simulated annealing algorithm is the repeated execution of three high-level steps: (1) generating, (2) evaluating, and (3) determining the acceptability of a new problem solution. A pipelined processor is designed to take advantage of these steps.

Abstract: A method for designing a system on a target device is disclosed. A first netlist with a first set of functionally invariant boundaries (FIBs) is generated after performing extraction during synthesis of a first version of the system in a first compilation. One or more of the FIBs is invalidated from the first set after performing optimizations during synthesis in the first compilation resulting in a second netlist with a second set of FIBs. A third netlist with a third set of FIBs is generated after performing extraction during synthesis of a second version of the system having a changed portion in a second compilation. Connectivity of matching nodes from the first netlist and the third netlist reaching FIBs is traversed to identify equivalent nodes associated with identical regions. The identical region in the third netlist is replaced with an optimized synthesized region from the second netlist.

Abstract: An apparatus for verifying an operation of a hardware descriptor program under test includes a lexical analyzer, a parsing engine and a generator. The lexical analyzer receives input/output (I/O) information of hardware descriptor language code that represents a circuit description of an integrated circuit to be tested. The lexical analyzer performs lexical analysis on the I/O information of the hardware descriptor language code so as to generate a stream of tokens. The parsing engine interprets the stream of tokens representing the I/O information of the hardware descriptor language code based on an interpretation of rules required to test a plurality of functions capable of being executed by the integrated circuit. The generator generates verification module code based on the interpretation of the stream of tokens representing the I/O information of the hardware descriptor language code and the rules interpretation.

Abstract: A design support program stored in a computer readable recording medium and executed by the computer includes computer readable program code stored thereon for causing a computer to execute operations of: selecting a first hierarchy which has different first characteristic information included in wiring layer structure information in a storage device; generating second characteristic information including the first characteristic information; copying wiring layer structure information; and converting the first characteristic information included in the copied wiring layer structure information into the second characteristic information to obtain a converted wiring layer structure information.