Abstract: Disclosed is an improved method and system for processing the tasks performed by an EDA tool in parallel. The IC layout is divided into a plurality of layout windows and one or more of the layout windows are processed in parallel. Sampling of one or more windows may be performed to provide dynamic performance estimation.

Abstract: There is provided a set of methods for generating state space models of general VLSI interconnect and transmission lines, trees and nets by closed forms with exact accuracy and low computation complexity. The state space model is built by three types of models: the branch model, the connection model and the non-connection model, that are block matrices in closed forms, arranged with topology. The main features are the topology structure, simplicity and accuracy of the closed forms of the state space models {A,B,C,D} or {A,B,C}, computation complexity of O(N) in sense of scalar multiplication times, where N is the total system order, practice of the modeling, ELO model simplification, and their optimization. For evenly distributed interconnect and transmission lines, trees and nets, the closed forms of state space model have the computation complexity of O(1), i.e., only a fixed constant of scalar multiplication times.

Abstract: A method for detecting and reporting changes in functional features of a simulation model caused by a software revision is disclosed. In one aspect, the method is independent of simulation model architecture. One performs regression testing with a plurality of feature-specific modules. The feature-specific modules are configured to generate a first set of information with the simulation model and compare the first set of information to a second set of corresponding information from the simulation model. In the above-described testing, the first set of information postdates the software revision and the second set of information predates the software revision.

Abstract: Broadly speaking, the embodiments of the present invention fill the need for a method of designing semiconductor device chips with reduced power consumption. The embodiments describe methods that are activity-based and are used for power optimization. The embodiments provide methods of selecting instances of a block of a chip to be replaced by either gate-length bias (GBIAS) cells or high-threshold-voltage (HVT) cells with minimal impact (little or no impact) on the overall performance of the chip. Only instances not on the critical path(s) are selected. Instances with low activities and high slack thresholds are chosen to be replaced by either GBIAS cells or HVT cells. By replacing the instances with low activities and high slack threshold, the performance impact on the block and chip is minimized. The replacement results in net power reduction, which is critical to advanced device technologies.

Abstract: In an embodiment, data in a first processor-based system is captured and serialized into an XML format. The XML-formatted data is transmitted to a second processor-based system, it is deserialized into a non-XML format, and it is processed in the second processor-based system. The second processor-based system is substantially similar to the first processor-based system, and the processing of the deserialized data on the second processor-based system relates to a support of the first processor-based system.

Abstract: A configuration manager identifies a first device and a second device within a simulated system. Each device within the simulated system includes an inbound port and an outbound port. Next, the configuration manager injects a simulation only packet, at an “outbound time,” on the first device's outbound port and detects that the second device's inbound port receives the simulation only packet at an “inbound time.” As such, the configuration manager identifies a direct connection between the first device and the second device and computes a latency time for the connection. In turn, the configuration manager configures one or more first device configuration registers and one or more second device configuration registers based upon the computed latency time.

Abstract: A digital system design method uses a higher programming language. In order to realize a digital system, an algorithm is verified based on a program written by the higher programming language and a program is programmed considering the higher programming language-hardware characteristics before the program is written in the lower programming language, and thus conversion into the lower programming language may be easily performed.

Abstract: A method and a device for simulating an automation system are disclosed. The aim of the invention is to allow an automation system to be simulated in such a way that simulation components operating at very different computing speeds can be combined into an overall simulation. Said aim is achieved by a method comprising a control component that can be clocked using an external timing source and at least one simulation component which can be clocked using an external timing source. A coordinated clock system is provided for the control component and the at least one simulation component by means of a control component-independent timing coordinator.

Abstract: Various tools and techniques are provided for reducing an original circuit network into a simpler, realizable RCLM circuit network. Branches of the original network are merged to reduce its total number of nodes. More particularly, the branches of the original circuit are merged so that the resulting reduced circuit approximately replicates the timing characteristics of the original circuit over the desired operating frequency range. The determination whether to merge two branches is made based upon one or more circuit characteristics associated with the node connecting the branches.

Abstract: A sequential cell is characterized using interdependent setup/hold time pairs to produce associated clock-to-Q delay values, and then identifying setup/hold time pairs that produce a selected clock-to-Q delay value (e.g., 10% of failure). The identified setup/hold time pairs (or a piecewise linear (PWL) approximation thereof) are then stored in a cell library for use in static timing analysis (STA). During STA, the setup and hold skews calculated for each synchronous circuit are compared with a selected setup/hold time pair stored in the cell library (e.g., a pair having a relatively low hold value). If at least one of the setup and hold skews violates the selected setup/hold time pair, then the remaining identified setup/hold time pairs (or the PWL approximation) are utilized to determine if the synchronous circuit is violates established constraints, and if not, to identify the setup and hold times required to remove the violation.

Abstract: A hardware accelerator includes hardware support for a combinational only cycle and a latch only cycle in a simulation model with a single partition of latches and combinational logic. Preferred embodiments use a special 4-input 1-output function unit in the hardware accelerator in place of the normal latch function that write back the old latch value for combinational only cycles. Other embodiments include hardware support for separate array write disables for arrays and transparent latches depending on whether the cycle is a combinational only cycle and a latch only cycle. A conditional array write disable dependent on the occurrence of a hardware breakpoint is also included that supports switching from a latch plus combinational cycle to a latch only cycle, to give control to the user before evaluating the combinational logic if a breakpoint occurs on a latch.

Abstract: A design tool for reducing half-cycle common path pessimism includes program instructions storable on a computer readable medium. The program instructions may be executable by a processor to receive a timing report for the IC. For each source clock path and destination clock path of each half-cycle timing path, the design tool may identify common circuit elements, and determine a process, voltage, and temperature (PVT) path delay value corresponding to PVT scaling of each identified common circuit element. The design tool may sum together the PVT path delay values of each identified common circuit element to obtain a total PVT compensation value. The design tool may also generate a new total skew value by subtracting the total PVT compensation value from a total compensated skew value, and generate a corrected timing report that includes the new total skew values.

Abstract: Various approaches are provided for generating an implementation of an electronic circuit design. In one embodiment, a processor-based method implements a design in an integrated circuit or IC (e.g., a programmable logic device. The method includes storing performance-variation data that represents location-based performance variations between logically-equivalent-programmable resources of the IC. The respective stored performance-variation data of at least two logically-equivalent-programmable resources of the IC are compared. The logic of the design is mapped, placed and routed on resources of the IC. The mapping, placing and routing includes, for an implementation of at least one subset of the logic of the design, selecting between the at least two logically-equivalent-programmable resources of the IC based on a result of the step of comparing respective stored performance-variation data of the at least two logically-equivalent-programmable resources.

Abstract: A partitioning method for an integrated circuit (IC) design includes providing a textual file representing the design as library-specific cells and interconnections, including timing data for the cells and timing data derived from the design after placement and routing. The design is flattened to cell level. Edge-triggered flip-flops (ETFF's) are selected and divided into two groups by communications attributes. First group is subdivided into the number of subsets in the partition. The ETFF's in each subset are analyzed by their communications attributes, and divided into those that connect to circuit elements outside the particular subset, and those that do not, reducing intersubset communications and placing them under external clock control. The partition is electrically equivalent to the design. The design is simulated by placing each subset on its own computer with simulator software. The computers are interconnected. User interventions may be allowed.

Abstract: Simulation of the operation of a data processing apparatus having a number of master logic units and slave logic units coupled via a bus is provided. The data processing apparatus performs data transfers between the master logic units and the slave logic units over the bus. Anticipated timing information for each successive data transfer over the bus is generated by assuming that each successive data transfer can occur with exclusive access to the bus, determining whether the anticipated timing information indicates that two or more concurrent data transfers would occur on the bus, and in the event that the anticipated timing information indicates that two or more concurrent data transfers would occur on the bus, generating revised timing information for those data transfers, the revised timing information being generated using bus status information until those data transfers have been completed.

Abstract: A method for clustering logic units in a field programmable integrated chip to generate a set of clusters is disclosed. The clustering step for forming a super cluster comprises a first logic element and a second logic unit a first logic unit and a super cluster, or a first super cluster and a second super cluster. The method includes generating all possible configurations by enumerating all possible two-way relationships combining a driver-and-receiver relationship from a pool of a finite number of dedicated connections. The set of all possible configurations is reduced to a subset of configurations based on one or more multi-dimension criteria. Each dimension in the multi-dimensional criteria is represented by a parameter. The method involves prioritizing a collection of parameters so that a set of selected parameters or a set of selected criteria is used to generate a desirable number of subsets of configurations.

Abstract: A system, such as hardware or software system having a number of modules, is simulated using multi-tasking computer code. Simulation computer code launches tasks simulating system execution, where each task corresponds to a module. Each task requests a processing delay to a common scheduler. Upon the common scheduler receiving a processing delay request, the common scheduler instructs a scheduling method processor to update a task-remaining time for at least one task. The scheduling method processor updates the task-remaining time for at least one task based at least on a scheduling approach. The common scheduler sends a wait request to a preexisting simulation system to delay a module that corresponds to the task by a length of time, based on the task-remaining time for the task and the scheduling approach. The preexisting simulation system delays the module that corresponds to the task by the length of time of the wait request.

Abstract: A leakage power recovery system and method, and a electronic design automation (EDA) tool incorporating either or both of the system and the method.

Abstract: Static timing analysis attempts to exhaustively analyze all critical paths of a design. With ever decreasing geometries and ever increasing design complexity, manually identifying timing violations with standard static timing analysis can be very complex and time consuming. A static timing analysis tool can advantageously manage multiple runs having different modes and corners and automatically merge the results generated by the runs. The STA tool can perform the runs either in parallel or in series. Advantageously, the STA tool can save the full timing analysis generated by each run and then extract information from these saved results to form merged results for the design. These merged results can provide different levels of analysis coverage, supply path information at various levels of detail, allow selectable accessibility to information, and highlight propagation of timing changes/violations in the design.

Abstract: Roughly described, signal propagation delay values are estimated for a plurality of interconnects in a circuit design. For each interconnect, the propagation delay value(s) are estimated in dependence upon a preliminary approximate determination of whether the signal propagation delay is dominated more by an interconnect capacitance term or by an interconnect capacitance and resistance product term. If it is dominated more by the interconnect capacitance term, then the parameter values used for a minimum propagation delay calculation are obtained assuming a smallest capacitance process variation case and the parameter values used for a maximum propagation delay calculation are obtained assuming a largest capacitance process variation case. If the signal propagation delay is dominated more by the interconnect capacitance and resistance product term, then the opposite assumptions are made. Preferably the approximate determination is made by comparing Rint to k*Rd.

Abstract: A hardware emulation system is disclosed which reduces hardware cost by time multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The hardware emulation system comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces through the use of multiplexing.

Abstract: A circuit analyzing device includes: a peripheral input signal setting part configured to make a signal setting by a predetermined requirement for a peripheral input which does not logically affect operation of the predetermined circuit part, upon analyzing a signal delay in operation of a predetermined circuit part, and wherein: analysis is made for a signal propagation operation delay in operation of the predetermined circuit part, in consideration of influence of the signal input from the signal setting.

Abstract: For the purpose of providing a simulation model allowing gate simulation but is capable of keeping the circuit information on the functional block (IP) secret, a method of generating a simulation model provided herein by the present invention comprises a step of generating a net list containing circuit information of an electronic circuit using a functional block; and a step of deleting the circuit information based on the net list, and generating a gate simulation model carrying out a timing simulation, including logic information and delay information between input/output of the functional block.

Abstract: Various techniques and tools are disclosed for providing an osculating model of a circuit, which can be used to more accurately predict the circuit's operation. The parameters for a general model of the circuit are determined such that the general model matches desired circuit characteristics at one or more points. The parameters for the general model are determined such that the slopes of the general model at those points also match desired circuit characteristics. These determined parameters are used to create an osculating model specific to the circuit. The osculating model of the circuit can be employed to predict the operation of the circuit. Particular implementations of these techniques and tools may be used to predict the timing characteristics of a circuit having a capacitive, inductive, or magnetically-coupled load.

Abstract: A method and a system for conducting a static timing analysis on a circuit having a plurality of point-to-point delay constraints between two points of the circuit, in which two conservative and two optimistic user defined tests are derived for all types of the point-to-point delay constraints. The method shows that when a conservative test is performed without introducing any special tags, then it is found that the point-to-point constraint is satisfied. On the other hand, when the optimistic test fails without any special tags, it is determined that the point-to-point constraint is bound to fail if special tags are introduced, in which case, they are to be introduced only when an exact slack is desired. Finally, for anything in between, a real analysis with special tags or path tracing is required. Based on the topology of the graph, arrival time based tests may be tighter in some situations, while the required arrival time based tests, may be tighter in others.

Abstract: In delay characteristic evaluation of a logical circuit, there was the problem of underestimation of the output load compared with the actual output load. There is provided a simulation device including a simplification section that, simplifies the load circuit using a transistor with which a virtual control voltage source is connected, by specifying a transistor driven through the output terminal of the target circuit and connecting to the drain of this transistor the virtual control voltage source whereby the output potential of this transistor is varied in accordance with the gate potential of this transistor.

Abstract: A circuit simulator includes: a DC analysis section which analyses a static stable potential on a transmission circuit if a capacitor which blocks a DC current while allowing an AC current to pass therethrough is connected in series in the line of the transmission circuit; and an initial potential application section which applies, as an initial potential in the simulation, the stable potential obtained by the DC analysis section to an application position on the upstream side of the capacitor in the flow of the signal through the transmission circuit. The simulator also includes a circuit simulation section which performs the simulation of the transmission circuit under the initial potential applied by the initial potential application section.

Abstract: One particular implementation takes the form of an apparatus or method for parallelizing a sequential power simulation of an integrated circuit device. The implementation may temporally divide the simulation so that separate time segments of the simulation can be run at the same time, thereby reducing he required time necessary to perform the power simulation. More particularly, a logic simulation may be performed on the integrated circuit and snapshots of the logic devices of the integrated circuit may be taken at a specified period. The separate time segments of the simulation may then be simulated in a parallel manner to simulate power consumption of the integrated circuit. Performing the power simulation on the separate time segments may reduce the required time of a typical power consumption simulation of an integrated circuit.

Abstract: A leakage power recovery system and method, and a electronic design automation (EDA) tool incorporating either or both of the system and the method. In one embodiment, the timing signoff tool includes: (1) a power recovery module configured to make first conditional replacements of cells in at least one path in a circuit design with lower leakage cells and estimate a delay and a slack of the at least one path based on the first conditional replacement and (2) a speed recovery module associated with the power recovery module and configured to determine whether the first conditional replacements cause a timing violation with respect to the at least one path and make second conditional replacements with higher leakage cells until the timing violation is removed.

Abstract: This invention intends to provide timing analysis methods, timing analysis programs, and timing analysis tools for the purpose of performing timing verification in optimum conditions without any excessive variations by statistically dealing with variations in elemental devices forming a semiconductor integrated circuit. In order to verify a timing between two signals, a delay value of a signal propagating through a signal path selected as a candidate for timing analysis is obtained, and with respect to a random variation amount of the delay value, a random variation amount corresponding to the number of gate circuit stages forming the signal path is obtained. Then, based on the delay value and the random variation amount, a most severe variation amount between the two signals in a most severe operating condition is obtained, and based on the most severe variation amount, a respective individual variation coefficient is allocated for each gate circuit, thereby performing a timing analysis.

Abstract: An interface test can be performed by, for example, only a self apparatus when interface operation specifications are different between the self apparatus and an original connection partner apparatus. An LSI has a plurality of interfaces (IFs) for transmission/reception of data with an external device, and the LSI includes an emulation control unit for allowing one of the two of the plurality of IFs to perform an operation of emulating an IF of a connection partner device having operation specifications different from those of the LSI, when two IFs are connected to each other via a transmission line.

Abstract: A high accuracy method for transistor-level static timing analysis is disclosed. Accurate static timing verification requires that individual gate and interconnect delays be accurately calculated. At the sub-micron level, calculating gate and interconnect delays using delay models can result in reduced accuracy. Instead, the proposed method calculates delays through numerical integration using an embedded circuit simulator. It takes into account short circuit current and carefully chooses the set of conditions that results in a tight upper bound of the worst case delay for each gate. Similar repeating transistor configurations of gates in the circuit are automatically identified and a novel interpolation based caching scheme quickly computes gate delays from the delays of similar gates. A tight object code level integration with a commercial high speed transistor-level circuit simulator allows efficient invocation of the simulation.

Abstract: A method and apparatus is provided for annotation-based behavior extensions. A primary contributor is identified based on a first attribute. Behaviors from a secondary contributor are linked to the primary contributor once a second attribute is examined. Finally, one or more files are generated using the linked behaviors from the primary and secondary contributors.

Abstract: A method and system for simulation of an electronic circuit is provided, the circuit being represented by a network of a plurality of logic elements, the circuit comprising first and second asynchronous clock domains, whereby jitter elements are additionally inserted at predetermined portions of circuit boundaries between the first and second clock domains, the jitter elements being represented as logic elements, the values of which are randomly set.

Abstract: A method of estimating a Miller coefficient for an aggressor network and a victim network coupled by a coupling capacitor includes synthesizing a reduced order system from the aggressor network and the victim network, estimating an active area across the coupling capacitor for an aggressor induced noise signal based on the reduced order system, calculating an estimate of the Miller coefficient based on the active area of the aggressor induced noise signal, and outputting the calculated estimate of the Miller coefficient.

Abstract: A method estimates the signal delay in a VLSI circuit and accurately estimates the delay and conversion time of a transmission signal in the circuit in order to prevent a designer of the VLSI circuit from erroneously judging the logic made by the designed circuit.

Abstract: The present invention is directed to determining the timing for a synchronous integrated circuit, the circuit including a multiplicity of clocked elements interconnected by signal paths. Predictions are formed for timing delays in said signal paths in the integrated circuit. A first such path is selected, wires are traced in the integrated circuit forming the path, hereinafter referred to as victim wires, and adjacent and crossing wires thereto, hereinafter referred to as aggressor wires, are determined. For each aggressor wire, the amount of electromagnetic coupling to the victim wires of the first path is determined. The aggressor wires are divided into a plurality of categories depending on the clocked timing of the aggressor wires in relation to the clocked timing of the victim wires.

Abstract: IC design flow includes RTL design, synthesis, APR, and layout. An IC designer can choose a suitable standard cell for an integrated circuit according to the timing, area, and BCI (best cell index) of each standard cell. Further, the BCI of a standard cell can be generated by generating critical dimensions of a standard cell in a plurality of surroundings, generating a plurality of circuit parameters corresponding to the plurality of surroundings, calculating the differences of the plurality of circuit parameters and the ideal circuit parameter of the standard cell, and analyzing the distribution of the differences.

Abstract: One embodiment of the present invention provides a system for determining an electrical property for an interconnect layer. During operation, the system receives interconnect technology data which includes nominal parameter values for a first interconnect layer, and parameter-variation values which represent variations in the nominal parameter values due to random process variations. Next, the system receives an interconnect template which describes the geometry of a portion of a second interconnect layer. The system then determines electrical property data for the interconnect template using the interconnect technology data. The electrical property data can include a nominal electrical property value, and sensitivity values which represent the sensitivities of the nominal electrical property value to variations in the nominal parameter values. Next, the system stores the electrical property data and the interconnect technology data in a storage.

Abstract: Techniques for organizing and displaying timing data derived from an EDA tool are provided that allows users to easily extract, analyze, and manipulate portions of the timing data relevant to particular user requirements. Relevant portions of signal waveforms are displayed on an interactive graphical user interface (GUI). Time points on the waveforms are marked with pointers so that users can easily visualize the relationships between different signals. A user can also extract relevant timing data from the EDA tool by manipulating the GUI. Manipulating and understanding circuit design requirements affects all of the design cycle and the quality of the final result from an EDA tool. A user can visualize all aspects of timing analysis on the GUI, such as clock skew, and the setup/hold relationship. A data entry approach is provided that can be used for natural and intuitive manipulation of various timing relationships.

Abstract: An integrated circuit design simulation method is provided that takes advantage of the fact that, when an instance of a circuit module has been simulated under a given set of input conditions, and the resulting output values and delays have been evaluated, another instance of the same module need not be re-simulated when it has the same input combination as the prior circuit module instance. The results computed earlier for the earlier circuit module instance can be re-used for the current circuit module instance.

Abstract: A method is specified for determining the quality of a quantity of properties describing a machine, including a step for determining the existence of at least one sub-quantity of interrelated properties (P0, P1, . . . Pn) of the form Pi=(forall t. Ai(t)=>Zi(t)), wherein Ai(t) present an initial state and Zi(t) a target state for a corresponding property and at least one initial state Ai is dependant on internal signals and including a step for checking whether at least one aspect of the input/output behaviour of the machine described by the properties, which cannot be derived from an individual property Pi, is described to such an accurate extent that one property Q exists, which represents this aspect without being dependant on the internal signals. The procedure is capable of providing a measurement and can particularly be used in the verification and specification of circuits.

Abstract: A method for generating automatic design characterization patterns for integrated circuits (IC) is provided. The method includes selecting a routing scheme from a file containing the device description of the routings of the IC. The routing scheme may be of a phase locked loop, clock tree, delay element, or input output block in one embodiment. Resource types for the routing scheme are identified and a path is defined, within constraints, between the resources. Once a path is defined, alternate paths are defined by retracing the path within constraints from an end of the path to the beginning of the path. An alternative path is then built and the alternative path shares a portion of the path previously defined. A computing system providing the functionality of the method is also provided.

Abstract: An electrical circuit comprising a plurality of cells can be simulated to produce simulation results by sorting cells between active status cells and inactive status cells and reducing the processing of simulation results from inactive cells to thereby save simulation time.

Abstract: Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit design having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is captured. For instance, the responses are determined more accurately by analyzing the effect of sensitizing a timing exception path during each time frame associated with a scan pattern. Path sensitization can be determined based on observing whether values injected at starting points of the timing exception paths due to signal transitions and glitches propagate to their end points. The response can be updated by masking the affected end points and propagating unknown values further in the circuit to determine whether they are captured at observation points of the circuit. For instance, the methods and systems described herein may result in reduced unknowns, improved test coverage and test compression.

Abstract: Instructions to be executed on a system are simulated. Representative simulation phases of the instructions, which most affect simulation results of the instructions to be executed on the system, are dynamically determined. For each representative simulation phase of the instructions, a model is selected from a number of models that provides specified accuracy with a minimal amount of simulation time, and the representative simulation phase is simulated using the model selected. The simulation results for the instructions to be executed on the system are then output.

Abstract: A method and system for modeling logical circuit blocks including transistor gate capacitance loading effects provides improved simulation of logical circuit block transition times and delay times. The non-linear behavior of transistor gates of other logical circuit block inputs that are connected to the logical circuit block output is taken into account by a transition time function and a delay time function that are each separately dependent on static capacitance and transistor gate capacitance and can be used to determine logical circuit block timing and output performance. A separate N-channel and P-channel gate capacitance may also be used as inputs to the transition time and delay time functions to provide further improvement, or a ratio of N-channel to P-channel capacitances may alternatively be used as input to the transition time and delay time functions.

Abstract: A method for optimization of clock gating in integrated circuit (IC) design. Clock gating techniques are very useful in reducing the electrical power consumed by an IC. A general method for identifying registers that are candidates for clock gating is presented. Furthermore, a determination is made regarding which of the candidate registers to clock gate in order to achieve optimal power and IC area savings. The determination is based on switching activity of the candidate registers.

Abstract: Methods and systems for automatically reporting delay incurred in a model is disclosed. The delay may be incurred in a part or in an entire portion of the model. Delay incurred in each component of the model is determined and reported to users before executing the model. The delay of each component of the model may be determined based on intrinsic information of the component. If the intrinsic information of the component does not provide information on the delay of the component, the component may be simulated to determine the delay of the components. The model may be automatically compensated for the delay. The delay is reported prior to the execution of the model, and compensated for without executing the model.

Abstract: A hardware-block constraint specification method includes defining a plurality of hardware-block constraint categories according to at least one of type of constraint and constraint operating mode and defining a plurality of hardware-block constraint commands. Each of the plurality of hardware-block constraint commands is categorized into one of the plurality of hardware-block constraint categories. The method also includes encapsulating the plurality of hardware-block constraint commands within a plurality of modules usable, via an application programming interface, in a stand-alone mode or an integrated mode.