Abstract: Various techniques provide systems and methods for facilitating truly random bit generation. In one example, a method includes receiving a first truly random bit stream in a first memory that includes a plurality of memory cells. Each of the plurality of memory cells stores a respective one bit of the first truly random bit stream. The method further includes generating, by a logic circuit, each bit of a second truly random bit stream based on a respective pair of bits of the first truly random bit stream. The method further includes storing the second truly random bit stream in a second memory. Related methods and devices are also provided.

Abstract: Various techniques provide systems and methods for facilitating truly random bit generation. In one example, a method includes receiving a first truly random bit stream in a first memory that includes a plurality of memory cells. Each of the plurality of memory cells stores a respective one bit of the first truly random bit stream. The method further includes generating, by a logic circuit, each bit of a second truly random bit stream based on a respective pair of bits of the first truly random bit stream. The method further includes storing the second truly random bit stream in a second memory. Related methods and devices are also provided.

Abstract: Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit (“LSB”) and most significant bit (“MSB”) ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide.

Abstract: A phase shifter controller arranged to generate phase shift control signals for at least one phase shifter. The phase shifter controller is arranged to receive a first phase value ?1, receive a second phase value ?2, and output phase shift control signals. The phase shifter controller comprises a digital synthesizer arranged to compute a first digital phase shift control value based on the received first phase value ?1, and compute a second digital phase shift control value based on the received second phase value ?2. The phase shifter controller further comprises digital to analogue converters arranged to generate the phase shift control signals based on the derived first and second digital phase shift control values.

Abstract: The method includes converting, by the receiver, an input signal into a return-to-zero (RZ) signal, generating, by the receiver, a first summation signal by performing an exclusive-or (XOR) operation on the RZ signal and a delayed signal obtained by delaying the RZ signal by a reference time, collecting, by the receiver, n-length seed codes from the first summation signal, generating, by the receiver, a PN code based on the seed codes, and generating, by the receiver, a second summation signal by performing an XOR operation on the PN code and the delayed signal.

Abstract: An apparatus is provided. The apparatus comprises a polynomial register having a plurality of bits, a first bus, a second bus, and a transceiver that is coupled to the first bus, the second bus, and the polynomial register. The polynomial register is configured to store a user-defined polynomial, and the transceiver includes a pseudorandom bit sequence (PRBS) generator is configured to generate a scrambled signal from the user-defined polynomial and a PRBS checker that is configured to generate a descrambled signal from a second signal using the user-defined polynomial.

Abstract: Integrated circuits with pseudo random bit sequence (PRBS) generation circuitry are provided. The PRBS generation circuitry may be configured to support parallel output generation in multiple modes, where the parallel bit width in each mode can be different. The PRBS generation circuitry may include a linear feedback shift register that implements a desired polynomial, one or more XOR tree circuits that produces the parallel output bits, a multiplexer for selectively routing a subset of the parallel output bits back to the input of the shift register, and a gearbox for performing an adjustable bit width conversion. Configured in this way, the PRBS generation circuitry can provide parallel PRBS generation with an adjustable bit width.

Abstract: An assemblage for monitoring an output of a random generator is provided, which assemblage compares chronologically successive sample values at a sampling point with one another in order to detect a relationship of the compared sample values with one another.

Abstract: A programming model for a processor accelerator allows accelerated functions to be called from a main program directly without a management API for the accelerator. A compiler automatically generates wrapper source code for each accelerator function called by the application source code. The wrapper code is compiled, together with the accelerator source code, to generate an object file that is linked to an object file for the main program. By automatically generating the wrapper code, a programmer can simply and directly invoke accelerator functions without the use of a complex management API. In addition, because the wrapper code for the accelerator is generated automatically, a standard compiler can be used to compile the main program, using standard linkage conventions.

Abstract: Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit (“LSB”) and most significant bit (“MSB”) ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide.

Abstract: Methods and systems for encrypting data are disclosed. A circuit uses a white noise generator to capture a random string of bits as an encryption key. The encryption key is generated at a central server and is provided to a subscriber on a physical memory device. The subscriber uses the encryption key to encrypt a source data file. The encrypted data file is sent to the central server, which uses the encryption key to decrypt the encrypted data file and to recover the source data file. The file name for the source data file may be encrypted into the encrypted data file and a new name assigned to the encrypted data file. A random number index may be used to identify the starting point of the encrypted file.

Abstract: Random number generation apparatus (2) is described that comprises a threshold detector (4) and an electrical noise generator (6). The electrical noise generator (6) has at least two channels (8a-8d) and each channel is arranged to generate an electrical noise signal. The threshold detector (4), which may comprise a digital input-output (DIO) card, is arranged to periodically compare this electrical noise signal with a threshold and to provide a binary data output that indicates whether the threshold has been exceeded. Each channel of the electrical noise generator comprises at least two amplifiers (10a-10c) electrically connected in series that preferably provide a gain of 50,000 or more. Use of the random number generation apparatus (2) for quantum cryptography applications is also described.

Abstract: A method of generating pseudo-random numbers on a parallel processing system comprises generating a plurality of sub-streams of pseudo-random numbers, wherein the sub-streams are generated in parallel by one or more co-processors, and providing the plurality of sub-streams to respective processing elements, wherein the respective processing elements employ the plurality of sub-streams to execute an application.

Abstract: The present invention discloses a pseudo-random bit sequence (PRBS) generator which outputs the entire datapath, or entire pseudo-random bit sequence, over one single clock cycle. This is accomplished by removing redundancy, or any redundant exclusive-or gates from linear feedback shift registers; using logic to identify the critical path and optimal shift for the critical path; and dividing the datapath into several pipeline stages to increase the clock rate (i.e., transmission speed).

Abstract: A random number generation system comprising one or more ring oscillators configured to generate entropy due to accumulated phase drift. A random number generator can include a ring oscillator configured to switch between a first state in which a signal of the ring oscillator oscillates between logic levels, and a second state in which the signal at least partially settles to one of the logic levels. The random number generator can also include a counter configured to measure a count of pulses of the signal and a whitener mechanism configured to receive the signal from the ring oscillator, latch a logic level of the signal from the ring oscillator, latch the count of pulses from the counter, and generate a random number based on the logic level and the count of pulses. Corresponding methods may also be performed.

Abstract: The pseudorandom number generating system repeatedly performs simple transformation of a non-secure pseudorandom number sequence that may be generated quickly, and thus may quickly generate a highly secure pseudorandom number sequence having a long period. Furthermore, the encryption system and the decryption system do not generate a large encryption function difficult to be deciphered based on a shared key 122, but prepare multiple functions 126, which perform fast, different types of transformation, and select a combination of functions determined based on information of the shared key 122, and make the selected functions transform a text multiple times, thereby encrypt the text. Each of the functions is fast, and thus transformation by the entire combination is also fast. Furthermore, since the combination of functions and repetitive count can be changed, future improvement in specification is easy. Moreover, security is high since which functions are applied in what order is unknown.

Abstract: A system for implementing a chip lockout protection scheme for an IC device includes an on-chip password register that stores a password externally input by a user; an on-chip security block that generates a chip unlock signal, depending on whether the externally input password matches a correct password; an on-chip false data generator; an input protection scheme configured to gate the external data inputs to functional chip circuitry upon entry of the correct password; and an output protection scheme in communication configured to steer true chip data to external outputs of the IC device upon entry of the correct password, and to steer false data generated by the false data generator to the external outputs upon entry of an incorrect password. The false generated by the false data generator is deterministic and based upon external data inputs, thereby obfuscating whether or not the correct password has been entered.

Abstract: Method and device for generating factors of a RSA modulus N with a predetermined portion Nh, the RSA modulus comprising at least two factors. A first prime p is generated; a value Nh that forms a part of modulus N is obtained; a second prime q is generated in an interval dependent from p and Nh so that pq is a RSA modulus that shares Nh; and information enabling the calculation of the modulus/V is outputted.

Abstract: A random number generator uses the output of a true random generator to alter the behavior of a pseudo-random number generator. The alteration is performed by a mixing logic that builds a random seed for the pseudo-random number generator and includes a generator of an alteration signal, the generation of which exploits the random instant of arrival of the bits outgoing from the true random generator. The alteration signal is obtained by processing the seed by means of the pseudo-random sequence.

Abstract: An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random binary sequence generator circuit. The encoded and parallel digital data is coupled through a multiplexer to be serialized in a serializer in a normal mode of operation and the parallel test data is coupled through the multiplexer to be serialized in the serializer in a test mode of operation. Encoded and serial digital data are transmitted to a transmission medium in the normal mode, and serial test data are transmitted to the transmission medium in the test mode. The encoder, the serializer, the sequence generator circuit, and the multiplexer may be fabricated in a single integrated circuit chip. The parallel test data may be parallel pseudo-random binary sequence data. The parallel digital data may include data to generate colors in a visual image.

Abstract: A compact apparatus for generation of desired pseudorandom sequences with controllable period. The apparatus includes two-dimensional cellular automata for generating a first sequence, 2-by-L cellular automata for generating a second sequence, adders for performing bit-to-bit mod2 sum of the first sequences and the second sequences, and a buffer for buffering the resultant sequences from the adders.

Abstract: A random number generator includes a plurality of memory cells arranged in a series, a feedback processor for generating a feedback signal and for feeding the feedback signal into one of the memory cells, and a random number outputter formed to combine states of a group of at least two memory cells to obtain an output sequence. Sequences strongly differing from one another, the number of which is greater than the number of memory cells, can be generated by generating several output sequences AF0, AF1, AF2, . . . , AFk by combining states of different memory cells such that a safe and efficient bus encryption is achievable.

Abstract: A method is provided for generating a chaotic sequence. The method includes selecting a plurality of polynomial equations. The method also includes using residue number system (RNS) arithmetic operations to respectively determine solutions for the polynomial equations. The solutions are iteratively computed and expressed as RNS residue values. The method further includes determining a series of digits in a weighted number system (e.g., a binary number system) based on the RNS residue values. According to an aspect of the invention, the method includes using a Chinese Remainder Theorem process to determine a series of digits in the weighted number system based on the RNS residue values. According to another aspect of the invention, the determining step comprises identifying a number in the weighted number system that is defined by the RNS residue values.

Abstract: One embodiment is a system adapted to encrypt one or more packets of plaintext data in cipher-block chaining (CBC) mode. The system includes a plurality of digital logic components connected in series, where respective components are operative to process one or more rounds of a block cipher algorithm. A plurality of N bit registers are respectively coupled to the plurality of digital logic components. An XOR component receives blocks of plaintext data and blocks of ciphertext data, and XORs blocks of plaintext data for respective plaintext packets with previously encrypted blocks of ciphertext data for those plaintext packets. The XOR component iteratively feeds the XOR'd blocks of data into a first of the plurality of the digital logic components. In addition, a circuit component is operative to selectively pass blocks of ciphertext data fed back from an output of a final logic component to the XOR component.

Abstract: A Gaussian noise is simulated by discrete analogue ri,j. A first parameter ? and pluralities of first and second integers i and j are selected. A plurality of points i,j are identified and a magnitude si,j is calculated for each point based on ?, i and j. The discrete analogue ri,j is based on a respective si,j. Examples are given of ? = 2 B - A 2 B and D>i?0 and 2C>j?0, where B?0, 2B>A>0, C?1 and D?1, and magnitude s i , j = 1 - ? i + ? i · 1 - ? 2 C · j ? ? or ? ? s D - 1 , j = 1 - ? D - 1 + ? D - 1 · 1 2 C · j . In some embodiments, a segment is defined based on ? and i. The segment is divided into points based on respective values of j, and the magnitude is calculated for each point of the segment. The defining and dividing segments and calculating the magnitude is iteratively repeated for each value of i.

Abstract: A method for generating cryptographically secure (or unpredictable) pseudo-random numbers uses simple functions whose inverse is not a well-defined function and has a large number of branches, although the inverse could be easily computed on each particular branch. In this way the sequence of numbers is practically unpredictable and at the same time may be generated using very simple functions.

Abstract: Performing a hash algorithm in a processor architecture to alleviate performance bottlenecks and improve overall algorithm performance. In one embodiment of the invention, the hash algorithm is pipelined within the processor architecture.

Abstract: A method and a circuit for normalizing an initial bit flow, provided by a noise source, comprising dividing the bit flow into words of identical lengths, and assigning to each bit word of the initial flow an output state, the occurrence of a word, all the bits of which have identical states, alternately resulting in the assignment of a first state or of a second one.

Abstract: A random number generator. The random number generator includes a noise source, a circuit controlling random current consumption, and a circuit generating random bits. A noise voltage output from the noise source drives the circuit controlling random current consumption, which also generates a random control signal. The circuit generating random bits also includes a voltage-controlled oscillator, a plurality of frequency dividers, and a plurality of flip-flops. The voltage-controlled oscillator is controlled by both the noise voltage and the random control signal. The output of the voltage-controlled oscillator is input to the frequency dividers and the flip-flops to generate a random number.

Abstract: An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random binary sequence generator circuit. The encoded and parallel digital data is coupled through a multiplexer to be serialized in a serializer in a normal mode of operation and the parallel test data is coupled through the multiplexer to be serialized in the serializer in a test mode of operation. Encoded and serial digital data are transmitted to a transmission medium in the normal mode, and serial test data are transmitted to the transmission medium in the test mode. The encoder, the serializer, the sequence generator circuit, and the multiplexer may be fabricated in a single integrated circuit chip. The parallel test data may be parallel pseudo-random binary sequence data. The parallel digital data may include data to generate colors in a visual image.

Abstract: Some demonstrative embodiments of the invention include a method, apparatus and system of generating a random number. A random number generator may include, for example, a plurality of different random-number-generation modules adapted to generate random bits at a plurality of bit paths; and a combiner adapted to combine the bits of the plurality of paths. Other embodiments are described and claimed.

Abstract: An apparatus, system and method for retaining the maximum speed of flip-flop metastability based random number generators includes a fixed delay unit having an input for receiving a common signal from a digital signal generator, and a variable delay unit having an input also for receiving the common signal from the digital signal generator. Each of the delay units is attached to the input of a respective logic gate. A frequency measurement of the occurrences of metastability, which is the speed of the random bit generation and delay tuning module 312 receives an output of one of the first NAND gates, checks the frequency of random number bit generation and updates the variable delay unit to according to predetermined criteria to tune the delay so as to maximize the speed of the random bit generation. An algorithm is used to determine whether the optimum delay is equal to, smaller or larger than the delay used to achieve the measured frequency.

Abstract: A sequence generator for generating a pseudo random sequence for random number generation or a stream cipher engine includes a plurality of linear feedback shift registers operable to generate a plurality of binary sequences. A plurality of nonlinear functions having the binary sequences as their input and operable to generate a second plurality of binary sequences. There are at least two switches and a controller including a shift register operable to control said first and second switches. The first switch is operative to select one of the second plurality of binary sequences to the first bit of the shift register, and the second switch is operative to select one of said second plurality of binary sequences to the output of the sequence generator.

Abstract: A white noise generator comprising a MOSFET operated in its linear region and having zero source-drain DC bias current. This is achieved by connecting the source or drain terminal of the MOSFET to a gate terminal of a MOSFET amplifier that may be implemented as a multi-stage differential amplifier. Such a noise source avoids the effect of DC current responsible for generating 1/f noise and has a small physical size that results in low parasitic capacitance of the device itself.

Abstract: A process is provided for searching in parallel for a plurality of prime number values simultaneously includes the steps of: randomly generating a plurality of k random odd numbers (wherein k is preferably more than 2, but could also be one or more) expressed as n0,0, n1,0, . . . n((k?1)),0, each number providing a prime number candidate; determining a plurality of y additional odd numbers based on each one of the randomly generated odd numbers n0,0, n1,0, . . .

Abstract: A gold code generator is described comprising two pairs of linear feedback shift registers, the seed values for the second pair of linear feedback shift registers are different from the seed values for the first pair of linear feedback shift registers. The second seed values are calculated from the first seed values. The use of this second pair of linear feedback shift registers prevents the need to use a wide span of taps to the linear feedback shift register to produce output bits. By using two pairs of linear feedback shift registers, a parallel output implementation can be produced in which multiple output bits are produced in a single clock cycle.

Abstract: A method and apparatus for generating random number outputs utilized in generating a noise function at a given location in space. The method consists of partitioning selected portions of the random number generation process to achieve outputs in parallel. The relevant parallel outputs are weighted by effect and then summed together to give the amplitude of the noise function at the given location.

Abstract: An apparatus for generating pseudo-noise codes adapted for advancing or retarding pseudo-noise chips generated therefrom within one clock in a radio communication network based on code division multiple access (CDMA). The apparatus includes a control uni for outputting a control signal for the normal state or a PN chip advance; a plurality of MUXs for outputting an output value of the next state for a normal operation or an output value of a PN chip advance as an output signal in response to the control signal of the control unit; and a plurality of shift registers for outputting PN chip codes of the next or the second next state during one system clock time period in response to said MUXs. Further, the input end of each of the shift registers is connected to the output end of each MUX.

Abstract: Embodiments for a gold code generator are generally described herein.

Abstract: A method and device for use, e.g., in a mobile telephone, for self-clocked controlled pseudo random noise (PN) sequence generation comprises a plurality of sequence generator units for outputting a plurality of sequence values (Zt) on the basis of a plurality of clock values (Ct), and step pattern generators for selecting a step pattern, comprising said plurality of clock values (Ct), from a plurality of possible step patterns on the basis of a step pattern select signal (Wt). Thus, a flexible and efficient self-clocked controlled pseudo random noise (PN) sequence generation is obtained.

Abstract: A microelectronic apparatus and method for generating random binary words including at least one clocked pseudorandom binary number sequence generator normally operative to generate a cyclic output sequence of binary numbers, each number including a string of binary symbols, the cyclic output sequence including a basic sequence which is generated repeatedly, at least one bit stream generator generating a clocked bit stream including a stream of binary symbols of a first type occasionally interrupted by a binary symbol of a second type, wherein a first varying time interval between the occasional interruptions is intractably correlated to the output sequence of the number sequence generator, wherein each occurrence of an interruption of the stream of binary symbols of the first type by a binary symbol of the second type causes a pseudorandom modification of the cyclic output sequence of the number sequence generator and a sampling device operative to sample the cyclic output sequence of binary numbers thereby

Abstract: A bitstream generator including a plurality of linear feed shift registers (LFSRs) operative to generate a bit stream and including: at least a first LFSR operative, when assigned as a generator during a first time period including at least one clock cycle, to provide an output bit in each clock cycle within the first time period, and at least a second LFSR operative, when assigned as an assignor during the first time period, to provide in each clock cycle an output bit for determining assignments of at least some of the plurality of LFSRs for a second time period following the first time period, the assignments including assignment as a generator, and assignment as an assignor, and a first combiner operative to combine output bits from all of the at least a first LFSR being assigned as generators thereby to produce during each clock cycle a single output bit which is provided to the bit stream. Related apparatus and methods are also provided.

Abstract: A fast pseudo-random number generator, which can be employed in a variety of systems such as a stream cipher cryptosystem or a Monte Carlo simulation system, includes a linear feedback shift register (LFSR) having a state contained in N storage elements storing N bits of binary data which are separated into w words having word length M. At least two tap sources provide binary data, each tap source has a number of bits which is a multiple of M. The LFSR also includes a linear feedback function coupled to tap sources and providing a temporary value which is a linear function, such as bit-wise exclusive-or, of the binary data provided from the tap sources. The LFSR state is advanced by shifting the binary data in the storage elements by a multiple of M bits and provide the temporary value to fill in storage elements that would otherwise be empty from the shifting.

Abstract: A spreading code generator provides a parallel output of plural-bit spreading codes by use of vector operations. A data circulating loop is formed that comprises a register capable of a parallel plural-bit input and output, a vector multiplier, and a selector. Each of the data pieces output in parallel from the register is multiplied by a vector operation coefficient, thereby providing a certain amount of shift to each of the data pieces. The data after the vector operation is again set in the register, after which the same operation is repeated.

Abstract: A spreading code generator generates a spreading code specified by a matrix order and row number, which are matrix elements.

Abstract: A system for outputting pseudorandom noise sequences comprises a plurality of output apparatuses.

Abstract: The invention presented is a novel method and apparatus for generating PN sequences with an arbitrary number of bits, where the number of bits is provided in parallel with each clock pulse. This allows the sequences to be generated at high speed when needed, and allows parallel processing in the acquisition and demodulation processes. In the invention, the initial values of states are loaded into registers of a parallel PN generator, which immediately generates the next n bits of the PN sequence, where n is an arbitrary number dependent on performance required. Then, a first sub-part of the PN generator of the present invention receives the present state of the PN generator and outputs the state of the PN generator n bits in the future. The output of this first sub-part is then provided to a second sub-part of the generator, which generates the next n bits of the PN sequence. In this fashion, the entire PN sequence can be continuously generated.

Abstract: A circuit is designed with a plurality of logic circuits (370-374) for producing an offset state matrix. The circuit includes a first logic circuit (380-383) coupled to receive N elements of a respective row of a transition matrix and N elements of column of an input state matrix. The first logic circuit produces a multi-bit logical combination of corresponding bits of the respective row and the column. A second logic circuit (390) is coupled to receive the multi-bit logical combination and produces a respective element of the offset state matrix.

Abstract: The present invention provides a random sequence generator for generating an output signal having random values. The generator comprises a plurality of cells inter-connected to one another such that each cell receives, as an input, an output from each cell connected thereto and generates a cell output based on a current value of the cell output and each cell output received. The plurality of cells include k subsets, each subset including n cells. A pre-selected cell from each of the k subsets generates an output and the output of the k pre-selected cells is provided as the output signal of the generator. In a specific embodiment, each of the cells is a linear cellular automaton, with k being an instruction width and k*n being an instruction length. The invention is particularly suitable for internal self-testing of a microcontroller in a smart card. This eliminates the need for external test contacts and thus prevents potential break-ins through the external contacts.

Abstract: A method and a generator are described for high speed generation of an S-bit long pattern of a PRBS sequence to be periodically burst on to a bus of width S. The technique provides the calculation time being independent from the width S of the bus, and comprises calculation of all S bits of the PRBS pattern separately and in parallel by using previous PRBS patterns stored in a memory. For each bit to be generated, the generator performs a constant number N of logical operations required (by a polynomial defining the PRBS sequence.