Abstract: A device for executing a cryptoalgorithm including a central processing unit for a first sub-group of operations and for a flow control of the cryptoalgorithm as well as a hardware circuit for a second sub-group of operations, wherein the first sub-group preferably includes arithmetic and/or logic operations, while the second sub-group includes rotation operations, permutation operations, substitution operations or selection operations.

Abstract: A system including a pseudo-random number generator having a register to store an extended state having a reduced state and a dynamic constant, an initialization module to initialize a part of the extended state based on a Key and/or an Initial Value, a state update module to update the reduced state, an output word module to generate output words, the state update module and the output word module being adapted to operate through cyclical rounds, each round including updating the reduced state and then generating one of the output words, and an update dynamic constant module to update the dynamic constant, wherein in a majority of the rounds, updating of the reduced state and/or generation of the output word is based on the dynamic constant, and the dynamic constant is only updated in a minority of the rounds. Related apparatus and method are also described.

Abstract: The present invention provides a semiconductor device such as an IC capable of generating completely random signals and generating an authentication signal, random number, and probability by integrally setting a random pulse generation source for spontaneously generating at the inside, and also provides a method/program for generating a random number and/or probability, comprising the steps of setting a random pulse generation source (hereafter referred to as RPG) for spontaneously generating random pulses, measuring the time interval between the random pulses generated from the RPG or measuring a voltage value of the random pulse, and converting it into a digital value, and generating an exponential distribution random number and/or uniform random number having a predetermined bit length and/or a probability from random pulses as converted to digital values.

Abstract: Provided is a random number generating circuit having a simple circuit structure, for generating a physical random number based on a noise. The random number generating circuit includes a reference voltage section, an inverting amplifier section having a threshold voltage equal to a reference voltage level, and a semiconductor switch provided between an output terminal of the reference voltage section and an input terminal of the inverting amplifier section. A thermal noise produced from the reference voltage section is held by the semiconductor switch and a capacitor and amplified by the inverting amplifier section to generate the physical random number.

Abstract: A method for creating entropy in a virtualized computing environment includes waking one or more samplers, each sampler having a sampling frequency; sampling a sample source with each of the one or more samplers; placing each of the samplers in an inactive state when not sampling; determining a difference between an expected value and a sampled value at each sampler; and providing a function of the difference from each of the one or more samplers to an aggregator.

Abstract: A method for generating a random number, comprising steps of receiving a data transmission binary signal subjected to phase jitter, generating several oscillator signals substantially of a same average frequency and having distinct respective phases, sampling a status of each of the oscillator signals upon the appearance of edges of the binary signal, and of generating a random number using the statuses of each of the oscillator signals. The method may be applied to an integrated circuit usable in a smart card.

Abstract: A random number generating device includes: a random number generator configured to have a plurality of random number generating elements that generate a random number in response to supply of a spin-injection current; and a temperature controller.

Abstract: Disclosed is method and chaos circuit for a random number generator comprising: a differential sample and hold circuit portion having a first and a second differential signal input and a first and a second differential signal output, a differential non-linear discriminator circuit portion that applies a differential discrimination function upon the first and the second differential signal output and outputs a first and a second discriminated signal, where the first and the second discriminated signals are also coupled to the first and the second differential signal inputs via a first and a second loop feedback.

Abstract: A system and method for providing non-deterministic data for processes executed by non-synchronized processor elements of a fault resilient system is discussed. The steps of the method comprise receiving a request for getting non-deterministic data from a requesting processor element; assigning non-deterministic data generated by an entropy source to the request; and supplying the non-deterministic data assigned to the request, to the requesting processor element.

Abstract: The present invention produces strings of true random numbers, extracted from field emission of electrons from nano-size emitters (NSE). Electrons may be produced in a miniature, three-electrode vacuum element that consists of a NSE emitter attached to the cathode surface, a close proximity gate electrode and an accelerating electrode (anode). A miniature fast response electron detector may also be inserted into the vacuum vessel. The detector sensitivity may allow single electron detection, with a noise level much lower than the resulting single-electron signal. The accelerated electrons may be directed to the detector and produce electric signals with well-defined pulse height and pulse shape characteristics. The electronic system analyzes the signals from the detector and generates random numbers thereby.

Abstract: The invention relates to a circuit for generating a true, circuit-specific and time-invariant random binary number, having: a matrix of K?L delay elements that can be connected to each other by means of L?1 single or double commutation circuits into chains of delay elements of length L, a single or double demultiplexer connected before the matrix, a single or double multiplexer connection after the matrix, and a run time or number comparator, wherein the setting of the commutation circuits, the demultiplexer, and the multiplexer can be prescribed by a control signal, wherein the circuit comprises a channel code encoder whereby code words of a channel code can be generated and a transcriber, whereby code words of the channel code can be transcribed into the control signal of the L?1 single or double commutation circuits, and a method for generating a true, circuit-specific and time-invariant random number by means of a matrix of L?K delay elements, L?1 single or double commutation circuits, a single or double

Abstract: An apparatus and method for providing a source of random numbers are generally described. In one example, an apparatus includes one or more storage elements having a selected voltage and a trip point, the voltage being close enough to the trip point such that random telegraph signal (RTS) noise associated with the elements is a determinant of whether the read voltage is above or below the trip point.

Abstract: Random numbers can be generated in a statistically independent manner and with identical probability if the bits generated by a controlled bit generator are stored by a storage in a plurality of memory regions, wherein the bits are each stored in such memory regions associated with a difference of the bits of the values 1 and 0 generated up to the time of storage, and if all the bits stored within a memory region are subjected to algorithmic post-processing as soon as a predetermined number of bits within a memory region is exceeded. The fact that the bits are not stored and processed sequentially, i.e. in the order of generation, allows using a sequence of bits within which the individual bits are statistically independent of one another for the algorithmic post-processing. Thus, a way of performing algorithmic post-processing of the bits without reducing the entropy is provided.

Abstract: Embodiments of an invention for cryptographic key generation using a stored input value and a stored count value have been described. In one embodiment, a processor includes non-volatile storage storing an input value and a count value, and logic to generate a cryptographic key based on the stored input value and the stored count value.

Abstract: A method of generating a sequence of random bits is disclosed. The method comprises steps of (a) generating a stream of photons using a laser; (b) attenuating said series of photons; (c) reflecting at least a part of said stream of photons from a reflector positioned such that at least part of said stream of photons is directed from said reflector into the cavity of said laser; (d) directing a part of said stream of photons to a detector such that a signal proportional to the intensity of the radiation falling on said detector is produced; (e) sampling the AC component of said signal at a plurality of times, thereby obtaining a sampled signal comprising a sequence of data points; (f) obtaining the nth time derivative of said sampled signal over at least a portion of said sample signal; and (g) adding the m least significant bits (LSBs) of said nth time derivative to said sequence. By this method, truly random sequences of bits can be obtained at rates of up to at least 300 GBits/s.

Abstract: Various embodiments of the present invention are directed to methods and systems for generating random numbers. In one embodiment, a quantum random number generator comprises: a state generator configured to generate a quantum system in a coherent state; a polarization states analyzer configured to project the quantum system onto one of four different polarization states, and detect each of the four different polarization states; a raw bit generator configured to convert the quantum system into a single photon and detect the single photon in either a first polarization state that corresponds to a first binary number or a second polarization state that corresponds to a second binary number; and a system control configured to receive signals from the polarization states analyzer and the raw bit generator, the signals corresponding to the polarization states, and output a random number based on the first and second polarization states of the single photon.

Abstract: A parallel computer system adds entropy to improve the quality of random number generation by using parity errors as a source of entropy because parity errors are influenced by external forces such as cosmic ray bombardment, alpha particle emission, and other random or near-random events. By using parity errors and associated information to generate entropy, the quality of random number generation in a parallel computer system is increased.

Abstract: Various embodiments of the present invention are directed optical-based quantum random number generators. In one embodiment, a quantum random number generator includes an input state generator that generates a first optical quantum system and a second optical quantum system in an entangled state, a detector that measures the state of the first optical quantum system and the state of the second optical quantum system, and a system control that evaluates a result obtained from measuring the state of the first optical quantum system and state of the second optical quantum system to determine whether or not to append a number associated with the result to the sequence of random numbers. The quantum random number generator also include state controllers, located between the input state generator and the detector, that are operationally controlled by the system control to maintain the entangled state, based on results obtained from previous measurements performed on the first and second optical quantum systems.

Abstract: A true random number generator (TRNG) in an integrated circuit comprises a plurality of independent ring oscillators with multiple output taps combined into enhanced outputs, a plurality of delay lines, a combiner-sampler and a source of a clock signal. Some embodiments provide a TRNG that is resettable, allowing one or more independent random numbers to be generated in response to a trigger signal.

Abstract: A Gaussian noise is simulated by discrete analogue ri,j. A first parameter ? and pluralities of first and second integers i and j are selected. A plurality of points i,j are identified and a magnitude si,j is calculated for each point based on ?, i and j. The discrete analogue ri,j is based on a respective si,j. Examples are given of ? = 2 B - A 2 B and D>i?0 and 2C>j?0, where B?0, 2B>A>0, C?1 and D?1, and magnitude s i , j = 1 - ? i + ? i · 1 - ? 2 C · j ? ? or ? ? s D - 1 , j = 1 - ? D - 1 + ? D - 1 · 1 2 C · j . In some embodiments, a segment is defined based on ? and i. The segment is divided into points based on respective values of j, and the magnitude is calculated for each point of the segment. The defining and dividing segments and calculating the magnitude is iteratively repeated for each value of i.

Abstract: There is provided a mechanism for generating random numbers following the normal distribution which does not generate a sequence correlation. The mechanism for generating random numbers following the normal distribution includes: a random recurrence plot generating mechanism 1 for generating random recurrence plots; and a recurrence plot-time series converting mechanism 4 for converting the random recurrence plots from the random recurrence plot generating unit 1 into time series, wherein Gaussian random numbers are generated by the recurrence plot-time series converting mechanism 4.

Abstract: A method for generating random numbers mimics by software the principle of coin flipping by combining different sources of randomness. The random number to be generated is assembled bit by bit from the subsequent results of this “coin flipping simulation”. The method for generating a random number with nRND bits BRi, wherein 0?i?nRND?1, comprises the steps of • providing a random bit table BFT with mBFT addressable bits BTj, wherein 0?j?mBFT?1, said random bit table containing an equal number of “0” bits and “1” bits in a random distribution, and • for a bit BRi of said random number with 0?i?nRND?1, generating an address FA in the range between 0 and mBFT?1, selecting the bit BTFA having the address FA from said random bit table, and setting said bit BRi of said random number to equal said bit BTFA from said random bit table (BRi=BTFA).

Abstract: There is provided a physical random number generation method and a physical random number generator by which safe random numbers can be obtained at high speed. The physical random number generator comprises a laser equipment which irradiates laser light, a frequency discrimination filter which discriminates frequencies of the laser light, an photodetector which converts intensity of laser light into electric signals, an on-off detector or an A/D converter which converts analogue signals output from the photodetector as a detected result into digital data. First, the laser light irradiated from the laser equipment is allowed to pass through the frequency discrimination filter. Transmitted light changes in intensity depending on frequency fluctuations of the laser light. Then, this intensity of the transmitted light is converted into electric signals by the photodetector to be converted into binary random numbers using the on-off detector or the A/D converter.

Abstract: An encrypted communication system, capable of performing processing with the speed higher than the conventionally achieved speed, includes an encryption device and a decryption device sharing parameters that satisfy p=3 and q=2^k (k: an integer of 2 or greater). The decryption device generates a public key and a private key using the parameters, the encryption device encrypts a plain text using the public key, and then, the decryption device decrypts the encrypted text using its own private key.

Abstract: A random signal generator uses a folded MOS transistor, whose drain-source current includes a random component, as an electronic noise source. The random signal generator generates a random binary signal from the random component. The invention may be applied, in particular, to smart cards.

Abstract: A method and apparatus for generating a random logic bit value. In some embodiments, a spin polarized current is created by flowing a pulse current through a spin polarizing material. The spin polarized current is injected in a free layer of a magnetic tunneling junction and a random logical bit value results from a variation in pulse current duration or a variation in thermal properties.

Abstract: An RNG circuit is connected to the parallel port of a computer. The circuit includes a flat source of white noise and a CMOS amplifier circuit compensated in the high frequency range. A low-frequency cut-off is selected to maintain high band-width yet eliminate the 1/f amplifier noise tail. A CMOS comparator with a 10 nanosecond rise time converts the analog signal to a binary one. A shift register converts the serial signal to a 4-bit parallel one at a sample rate selected at the knee of the serial dependence curve. Two levels of XOR defect correction produce a BRS at 20 kHZ, which is converted to a 4-bit parallel word, latched and buffered. The entire circuit is powered from the data pins of the parallel port. A device driver interface in the computer operates the RNG. The randomness defects with various levels of correction and sample rates are calculated and the RNG is optimized before manufacture.

Abstract: A random number generator which includes a bus including a plurality of bus lines configured to send and receive a signal between a circuit and another circuit, a calibration unit configured to dynamically adjust a reception condition of the signal, and a random number generating unit configured to generate a random number based on adjustment information of the calibration unit.

Abstract: A system having an entropy module, a memory module and a main module is disclosed. The entropy module may be configured to generate a plurality of first random numbers. The memory module may be configured to buffer (i) the first random numbers and (ii) a plurality of second random numbers. The main module is generally configured to (i) control a first transfer of the first random numbers from the entropy module to the memory module, (ii) control a second transfer of the first random numbers from the memory module to the main module, (iii) generate the second random numbers by encrypting the first random numbers and (iv) control a third transfer of the second random numbers from the main module to the memory module. The generation of the first random numbers and the generation of the second random numbers may be performed in parallel.

Abstract: A random number generating unit includes an external containment casing and a measurement cone within the external containment casing, to which liquid detection contacts are attached. One or more terminals on a random number generation integrated circuit, which terminals connect to the liquid detection contacts are included, as is a primary reservoir connected to a secondary reservoir containing a pump and a dropper to provide a bead of liquid from the pump, wherein the bead falls on the measurement cone to be detected by the liquid detection contacts and then fall into the primary reservoir.

Abstract: An apparatus includes: a plurality of bit producing circuits; a controller setting a sample frequency at which bits from the bit producing circuits are sampled; and a plurality of test circuits determining if bits sampled from each of the bit producing circuits are random, wherein the controller adjusts the sample frequency if the test circuits determine that the sampled bits are not random. A method performed by the apparatus is also included.

Abstract: A random number generating method for an electronic device including a plurality of unit circuits each first and second logic circuits, each logic circuit having a same shape and being formed through a same fabrication process, and an amplifier circuit for forming a binary signal by amplifying a noise superposed on the differential voltage of threshold voltages of the first and the second logic circuits; and a signal variation detecting circuit for forming an output signal in response to a variation in any of a plurality of binary signals outputted from the plurality of unit circuits, wherein a plurality of binary signals outputted from the signal variation detecting circuit are combined to generate a random number.

Abstract: A random bit generator and a method thereof are provided. The random bit generator includes an amplifier, a comparing circuit, an oscillator, a sampler, and a storage circuit. The amplifier amplifies a difference between input signals generated based on thermal noise. The comparing circuit compares an alternating current (AC) signal output from the amplifier with a direct current (DC) signal obtained by low-pass filtering the AC signal and outputs a signal according to the comparison result. The oscillator may be implemented with a resistor-capacitor (R-C) oscillator. The oscillator consumes lower current and occupies a smaller layout area than a voltage controlled oscillator (VCO) and outputs an oscillation signal. The sampler samples the oscillation signal output from the oscillator in response to the output signal of the comparing circuit. The storage circuit stores an output signal of the sampler in response to a clock signal.

Abstract: A server is configured for preventing flood attacks by a client having sent a request, by dynamically generating a challenge to be performed by the client before the server will perform any work for the client. The challenge includes a dynamically generated computational request and a dynamically generated secure cookie. The server generates a first hash result based on hashing a first random number, having a prescribed length, with a second random number having a dynamically selected length. A secure cookie is generated based on hashing the first hash result with a prescribed secure key known only by the server, and a unique identifier for the request such as the client network address with a time stamp. The challenge requires the client to determine the second random number based on the first random number and the hash result. The server validates the challenge results using the secure cookie.

Abstract: An architecture of an RFID system that facilitates the accessing of RFID tag data within an RFID environment. The architecture includes a plurality of RFID readers, each reader being operative to transmit a first RF signal for scanning at least one RFID tag disposed within an RF coverage region associated with the reader, and to receive at least one second RF signal including tag data in response to the scanning of the tag. The architecture further includes at least one host computer operative to execute at least one client application, and at least one controller/processor communicably coupled to the plurality of readers and the at least one host computer. The controller/processor is operative to control operation of the plurality of readers, to process the tag data received by the plurality of readers, and to provide the processed tag data to the at least one host computer for use by the at least one client application executing thereon.

Abstract: A system and method of determining locations of one or more RFID tags within an RFID environment. The system includes a plurality of RFID readers, each operative to transmit and receive RF signals for scanning a tag disposed within an RF coverage region associated with the reader, and for receiving tag data in response to the scanning of the tag. A plurality of sub-locations is determined within the environment, each corresponding to at least a portion of at least one of a plurality of RF coverage regions associated with the readers. The sub-locations are mapped to a plurality of predefined locations within the environment. A reader scans a tag, and receives tag scan data from the tag in response to the scanning of the tag. The tag scan data includes a tag identifier associated with the scanned tag. The tag scan data is mapped to the sub-locations based on the RF coverage region associated with the reader.

Abstract: In the encryption/decryption method, a random number sequence {ri} is generated on the basis of a given multiple-affine key system K and encryption is performed by an exclusive OR of the random number sequence {ri} with a plain text. Further, the multiple-affine key system K is automatically sequentially rewritten into a series of new multiple-affine key systems each time when the number of use times of the multiple-affine key system reaches a predetermined number and encryption of plain texts thereafter is continued while generating random numbers using the series of the rewritten multiple-affine key systems. Likewise, in decryption as well, since decryption is performed using a multiple-affine key system automatically rewritten each time when the number of use times reaches a predetermined number, a third party cannot reproduce the multiple-affine key system and therefore cannot decipher a cipher text.

Abstract: Methods, devices, and systems provide random number generation. Electrical characteristics of a processing device are sampled for statistically random values. The values are combined to produce random numbers. The random numbers are vended from the processing device for subsequent consumption by applications executing on or interfaced to the processing device.

Abstract: In the field of direct mind-machine interactions, prior art devices and methods do not provide sufficiently fast and reliable results. Mental influence detectors (100, 140, 400, 430) and corresponding methods provide fast and reliable results useful for detecting an influence of mind and hidden or classically non-inferable information. An anomalous effect detector (100) includes a source (104) of non-deterministic random numbers (110), a converter (114) to convert a property of numbers, a processor to accept converter output (118) and to produce an output signal (124) representative of an influence of mind. The processor output signal (124) contains fewer numbers than the input (110).

Abstract: A random number generator includes a fairness checker and correction module that ensures that a complete random sequence within a predetermined period of time will be output by the random number generator.

Abstract: A device for generating a random sequence (10) of bits is disclosed. The device comprises oscillating means (13), which will generate a random sequence of bits when biased with a noise signal. The oscillating means comprises at least one oscillator amplifier being protected from interfering signals by means of a load and a tail-current source for providing high noise-interference ratio. Further, the present invention relates to an integrated circuit and an electronic apparatus comprising the device for generating a random sequence according to the invention.

Abstract: A hybrid random number generator (HRNG) including an output, a combinational logic, a TRNG, and a PRNG. The HRNG is configurable to operate in a first and a second mode, wherein in the first mode the PRNG is serially connected between the TRNG and the output and the TRNG intermittently influences the PRNG, and in the second mode the TRNG and the PRNG are connected to the output via the combinational logic.

Abstract: Generally, this disclosure describes a system and method for generating random numbers. In at least one embodiment described herein, the method may include generating random bits in accordance with at least one security application via an integrated circuit, said integrated circuit including a true random number generator having an analog core. The method may further include providing, via an internally generated power supply, power to said analog core via a voltage regulator associated with said true random number generator. Of course, additional operations are also within the scope of the present disclosure.

Abstract: A system comprising a pseudo random number generator, a control circuit being configured to increase a quality of a pseudo random number output signal of the pseudo random number generator by coupling the pseudo random number generator with a true random number output signal of a true random number generator and a consumer circuit being configured to use the pseudo random number output signal before and after the increase.

Abstract: An integrated circuit (1 . . . 1??, 1a . . . I c) with a true random number generator (2 . . . 2??), which true random number generator (2 . . . 2?) comprises at least one instable physically uncloneable function (3 . . . 3??, 3a, 3a?) for generating true random numbers (8). Hence, each device of a group of devices can be provided with a unique true random generator, so that each device of the group is provided with different true random numbers even when said devices are applied to identical environmental conditions. Such a random number generator (2 . . . 2??) may be part of a smart card as well as of a module for near field communication, for example.

Abstract: A random number generator. The random number generator includes a noise source, a circuit controlling random current consumption, and a circuit generating random bits. A noise voltage output from the noise source drives the circuit controlling random current consumption, which also generates a random control signal. The circuit generating random bits also includes a voltage-controlled oscillator, a plurality of frequency dividers, and a plurality of flip-flops. The voltage-controlled oscillator is controlled by both the noise voltage and the random control signal. The output of the voltage-controlled oscillator is input to the frequency dividers and the flip-flops to generate a random number.

Abstract: A method and apparatus for generating true random numbers by way of a quantum optics process uses a light source to produce a beam which illuminates a detector array. The detectors of the array are associated with random numbers values. Detection of a photon by one of the detectors yields a number whose value is equal to that associated with the detector. This procedure is repeated to produce sequences of true random numbers. The randomness of the numbers stems from the transverse spatial distribution of the detection probability of the photons in the beam. If the array is made up of two detectors, the true random numbers produced are binary numbers. The process can be sped up using an array having pairs of two detectors. Using an array having more than two detectors also allows generating true random numbers of dimension higher than two. The primary object of the invention is to allow generating true random numbers by way of a quantum optics process.

Abstract: A device for generating a noise signal, which may be used for generating a truly random sequence (10) of bits is disclosed. The device comprises a noise source (11), and an amplifier (12) connected to the noise source (11). The device according noise source according to the invention is protected from interfering signals to provide high noise-interference ratio. Further, the present invention relates to an integrated circuit and an electronic apparatus comprising the device for generating a noise signal according to the invention.

Abstract: A true random number generator may comprise a multi-gigabit transceiver with a transceiver to receive a signal of predetermined source data. Recovery circuitry of the transceiver may be operable to recover data from the received signal. A controller may stress the recovery circuit to cause a portion of the data recovered to differ from the respective portion of the predetermined source data. An extractor may define numbers for a true random number sequence based on differences between the recovered data and the predetermined serial source data over an interval of time. In a particular example, the controller may influence at least one of the serial data transfer rate, the number of sequential same-state bits for the predetermined source data, and the stability of a clock signal to be recovered by a portion of the recovery circuit.

Abstract: A random number generator (RNG) resistant to side channel attacks includes an activation pseudo random number generator (APRNG) having an activation output connected to an activation seed input to provide a next seed to the activation seed input. A second random number generator includes a second seed input, which receives the next seed and a random data output, which outputs random data in accordance with the next seed. An input seed memory is connected to the activation seed input and a feedback connection from the activation output so that the next seed is stored in the input seed memory to be used by the APRNG as the activation seed input at a next startup cycle.