Multiple Parallel Operations Patents (Class 708/524)
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Patent number: 8495123Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: GrantFiled: October 1, 2012Date of Patent: July 23, 2013Assignee: Intel CorporationInventors: Alexander Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf C. Witt
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Patent number: 8458243Abstract: Digital signal processing (“DSP”) block circuitry on an integrated circuit (“IC”) is adapted for use (e.g., in multiple instances of the DSP block circuitry on the IC) for implementing finite-impulse-response (“FIR”) digital filters in systolic form. Each DSP block may include (1) first and second multiplier circuitry and (2) adder circuitry for adding (a) outputs of the multipliers and (b) signals chained in from a first other instance of the DSP block circuitry. Systolic delay circuitry is provided for either the outputs of the first multiplier (upstream from the adder) or at least one of the sets of inputs to the first multiplier. Additional systolic delay circuitry is provided for outputs of the adder, which are chained out to a second other instance of the DSP block circuitry.Type: GrantFiled: March 3, 2010Date of Patent: June 4, 2013Assignee: Altera CorporationInventors: Suleyman Sirri Demirsoy, Hyun Yi
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Patent number: 8407709Abstract: A batch scheduling apparatus that performs a scheduling of a parallel program to be executed as a batch job by a parallel computer includes a priority determining unit that determines a priority of the parallel program based on an index that indicates a level of utilization of the parallel computer by the parallel program; and a scheduling unit that schedules the parallel program based on the priority determined.Type: GrantFiled: July 29, 2005Date of Patent: March 26, 2013Assignee: Fujitsu LimitedInventor: Tomohide Inari
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Patent number: 8407273Abstract: A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not necessarily including, for example, one or more of addition, multiplication, subtraction, and division) on numerical values of low precision but high dynamic range (“LPHDR arithmetic”). Such a processor or other device may, for example, be implemented on a single chip. Whether or not implemented on a single chip, the number of LPHDR arithmetic elements in the processor or other device in certain embodiments of the present invention significantly exceeds (e.g., by at least 20 more than three times) the number of arithmetic elements, if any, in the processor or other device which are designed to perform high dynamic range arithmetic of traditional precision (such as 32 bit or 64 bit floating point arithmetic).Type: GrantFiled: February 17, 2012Date of Patent: March 26, 2013Assignee: Singular Computing LLCInventor: Joseph Bates
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Patent number: 8396915Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: GrantFiled: September 4, 2012Date of Patent: March 12, 2013Assignee: Intel CorporationInventors: Alexander Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf C. Witt
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Publication number: 20130031153Abstract: A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not necessarily including, for example, one or more of addition, multiplication, subtraction, and division) on numerical values of low precision but high dynamic range (“LPHDR arithmetic”). Such a processor or other device may, for example, be implemented on a single chip. Whether or not implemented on a single chip, the number of LPHDR arithmetic elements in the processor or other device in certain embodiments of the present invention significantly exceeds (e.g., by at least 20 more than three times) the number of arithmetic elements, if any, in the processor or other device which are designed to perform high dynamic range arithmetic of traditional precision (such as 32 bit or 64 bit floating point arithmetic).Type: ApplicationFiled: February 17, 2012Publication date: January 31, 2013Inventor: Joseph Bates
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Publication number: 20120331028Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: ApplicationFiled: September 4, 2012Publication date: December 27, 2012Inventors: Alexander D. Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt
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Publication number: 20120221618Abstract: A method and a device protected against hidden channel attacks includes a calculation of the result of the exponentiation of a data m by an exponent d. The method and the device are configured to execute only multiplications of identical large variables, by breaking down any multiplication of different large variables x, y into a combination of multiplications of identical large variables.Type: ApplicationFiled: February 23, 2012Publication date: August 30, 2012Applicant: INSIDE SECUREInventors: Benoît FEIX, Georges GAGNEROT, Myléne ROUSSELLET, Vincent VERNEUIL, Christophe CLAVIER
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Patent number: 8214758Abstract: An information processing apparatus is configured to execute a plurality of operations in parallel. A display unit displays a header identifying each operation in a plurality of operation on a display unit. A control unit switches a current operation based on selection of the header via an input unit and, when switching the current operation, controls display of suspension information to indicate a suspension state of a suspended operation on the header for the suspended operation in addition to the current operation.Type: GrantFiled: February 18, 2010Date of Patent: July 3, 2012Assignee: Canon Kabushiki KaishaInventor: Hirokazu Tanaka
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Method for combining binary numbers in environments having limited bit widths and apparatus therefor
Patent number: 8214418Abstract: The present disclosure provides a method and system for combining multiple coefficient words using only the magnitude bits of each of the coefficient words and using the sign bits of each of the coefficient words to modify the output of the combined magnitude bits. Using this method and/or system, it is possible to implement, for example, digital filters using larger coefficient word sizes without having to incur the inefficiencies and cost associated with using additional hardware resources, while maintaining an acceptable gain error in the filter response.Type: GrantFiled: November 20, 2007Date of Patent: July 3, 2012Assignee: Harris CorporationInventors: Larry Alan Stanton, John Crawford LeVieux -
Patent number: 8185571Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: GrantFiled: March 23, 2009Date of Patent: May 22, 2012Assignee: Intel CorporationInventors: Alexander D. Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt
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Patent number: 8150902Abstract: A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not necessarily including, for example, one or more of addition, multiplication, subtraction, and division) on numerical values of low precision but high dynamic range (“LPHDR arithmetic”). Such a processor or other device may, for example, be implemented on a single chip. Whether or not implemented on a single chip, the number of LPHDR arithmetic elements in the processor or other device in certain embodiments of the present invention significantly exceeds (e.g., by at least 20 more than three times) the number of arithmetic elements, if any, in the processor or other device which are designed to perform high dynamic range arithmetic of traditional precision (such as 32 bit or 64 bit floating point arithmetic).Type: GrantFiled: June 15, 2010Date of Patent: April 3, 2012Assignee: Singular Computing LLCInventor: Joseph Bates
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Patent number: 8117247Abstract: A configurable arithmetic block in a device having programmable logic for implementing arithmetic functions is disclosed. The configurable arithmetic block comprises a plurality of input registers coupled to receive multiple bit words; an arithmetic function circuit coupled to receive the multiple bit words; an output selection circuit coupled to receive the output of the plurality of input registers and an output of the arithmetic function circuit; and a plurality of output registers coupled the output selection circuit. A method of implementing arithmetic functions in a device having programmable logic is also disclosed.Type: GrantFiled: July 19, 2007Date of Patent: February 14, 2012Assignee: Xilinx, Inc.Inventor: Bradley L. Taylor
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Patent number: 8051121Abstract: According to some embodiments, a dual multiply-accumulate operation optimized for even and odd multisample calculations is disclosed.Type: GrantFiled: March 4, 2008Date of Patent: November 1, 2011Assignee: Marvell International Ltd.Inventors: Bradley C. Aldrich, Nigel C. Paver, William T. Maghielse
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Patent number: 8010590Abstract: A configurable arithmetic block for implementing arithmetic functions in a device having programmable logic is described. The configurable arithmetic block comprises a first plurality of registers coupled to receive input data; a second plurality of registers coupled to receive input data; an arithmetic function circuit having a plurality of arithmetic function elements, each arithmetic function element coupled to at least one other arithmetic function element of the plurality of arithmetic function elements and coupled to receive outputs of at least one of the first plurality of input registers and the second plurality of input registers; and an output coupled to the arithmetic function circuit. A method of implementing a configurable arithmetic block in a device having programmable logic is also disclosed.Type: GrantFiled: July 19, 2007Date of Patent: August 30, 2011Assignee: Xilinx, Inc.Inventor: Bradley L. Taylor
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Patent number: 7991816Abstract: A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted during the current cycle. The later operation may be a subtraction operation that immediately follows the first operation. The later instruction is decoded prior to the current cycle to control the inversion in the ALU. The ALU includes an adder, a rotator, and a data manipulation unit which invert the result during the current cycle in response to an invert control signal. The second operation subtracts the result during a subsequent cycle in which a carry control signal to the adder is enabled, and the rotator and the data manipulation unit are disabled. The ALU may be used in an execution unit of a microprocessor, such as a fixed-point unit.Type: GrantFiled: August 12, 2008Date of Patent: August 2, 2011Assignee: International Business Machines CorporationInventors: Brian William Curran, Ashutosh Goyal, Michael Thomas Vaden, David Allan Webber
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Patent number: 7986419Abstract: A method for optimizing the performance of a network printer comprising: scanning the input print data stream in a raster image processor and processing the entire input print data stream in a page parallel processing pathway where said input print data stream is in a page independent form; otherwise selecting the processing pathway corresponding to a lower processing time period and thereafter processing the entire input print data stream using said selected processing pathway.Type: GrantFiled: September 12, 2007Date of Patent: July 26, 2011Assignee: Xerox CorporationInventor: Chris Mazur
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Patent number: 7974996Abstract: A math coprocessor 1300 includes a multiply-accumulate unit 1600. Multiplier-accumulate unit 1600 includes a multiplier array 1603 for selectively multiplying first and second operands, the first and second operands having a data type selected from the group including floating point and integer data types. An adder 1604 selectively performs addition and subtraction operations on third and fourth operands, the third and fourth operands selected by multiplexer circuitry from the contents of a set of associated source registers, data output from multiplier array 1603 and data output from adder 1604.Type: GrantFiled: June 26, 2006Date of Patent: July 5, 2011Assignee: Cirrus Logic, Inc.Inventors: Gregory Allen North, Murli Ganeshan
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Publication number: 20110103578Abstract: Systems and methods efficiently process digests, hashes or other results by performing multiplicative functions in parallel with each other. In various embodiments, successive processing stages are provided, with each stage performing parallel multiplicative functions and also combining input terms to reduce the total number of terms that remain to be processed. By progressively combining the active terms into a smaller number of terms for subsequent processing, the time needed to process a result can be significantly reduced.Type: ApplicationFiled: October 30, 2009Publication date: May 5, 2011Applicant: GENERAL DYNAMICS C4 SYSTEMS, INC.Inventors: Gerardo ORLANDO, David KING, Mark KRUMPOCH
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Publication number: 20100325186Abstract: A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not necessarily including, for example, one or more of addition, multiplication, subtraction, and division) on numerical values of low precision but high dynamic range (“LPHDR arithmetic”). Such a processor or other device may, for example, be implemented on a single chip. Whether or not implemented on a single chip, the number of LPHDR arithmetic elements in the processor or other device in certain embodiments of the present invention significantly exceeds (e.g., by at least 20 more than three times) the number of arithmetic elements, if any, in the processor or other device which are designed to perform high dynamic range arithmetic of traditional precision (such as 32 bit or 64 bit floating point arithmetic).Type: ApplicationFiled: June 15, 2010Publication date: December 23, 2010Inventor: Joseph Bates
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Patent number: 7853635Abstract: A system for binary multiplication in a superscalar processor includes a first pipeline, an execution unit, and a first multiplexer; a first rotator in communication with one register of the first pipeline and the execution unit; and a leading zero detection register in communication with the execution unit and another register of the first pipeline; a second pipeline, a second execution unit, and a second multiplexer; a rotator in communication with one register of the second pipeline and the second execution unit; and a leading zero detection register in communication with the second execution unit and another register of the first pipeline; and a third pipeline, a binary multiplier in communication with a pair registers of the third pipeline; a general register; an operand buffer for obtaining first and second operands; and a bus for communication between the pipelines, the general register and the operand buffer.Type: GrantFiled: May 16, 2007Date of Patent: December 14, 2010Assignee: International Business Machines CorporationInventors: Fadi Y. Busaba, Steven R. Carlough, David S. Hutton, Christopher A. Krygowski, John G. Rell, Jr., Sheryll H. Veneracion
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Patent number: 7747020Abstract: Performing a hash algorithm in a processor architecture to alleviate performance bottlenecks and improve overall algorithm performance. In one embodiment of the invention, the hash algorithm is pipelined within the processor architecture.Type: GrantFiled: December 4, 2003Date of Patent: June 29, 2010Assignee: Intel CorporationInventor: Wajdi K. Feghali
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Patent number: 7733347Abstract: Although GPUs have been harnessed to solve non-graphics problems, these solutions are not widespread because GPUs remain difficult to program. Instead, an interpreter simplifies the task of programming a GPU by providing language constructs such as a set of data types and operations that are more familiar to non-graphics programmers. The interpreter maps these familiar language constructs to the more difficult graphics programming resources such as DirectX®, OpenGL®, Cg®, and/or HLSL®.Type: GrantFiled: October 21, 2005Date of Patent: June 8, 2010Assignee: Microsoft CorporationInventors: David Read Tarditi, Jr., Vivian Sewelson
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Patent number: 7725520Abstract: The present invention provides a processor including data manipulating means for generating an arbitrary combination of elements of a first input vector and elements of a second input vector, arithmetic means for performing a product-sum operation on the combination, and repetition control means for controlling the generation of the combination by the data manipulating means and the product-sum operation by the arithmetic means according to a number of the elements of the first input vector and the second input vector.Type: GrantFiled: November 16, 2005Date of Patent: May 25, 2010Assignee: Sony CorporationInventors: Hiroaki Sakaguchi, Koichi Hasegawa
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Methods and apparatus for efficient complex long multiplication and covariance matrix implementation
Publication number: 20100121899Abstract: Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex multiplication pipeline hardware to be efficiently used.Type: ApplicationFiled: January 19, 2010Publication date: May 13, 2010Applicant: Altera CorporationInventors: Gerald G. Pechanek, Ricardo Rodriguez, Matthew Plonski, David Strube, Kevin Coopman -
Patent number: 7663631Abstract: A single-instruction multiple-data processor comprises at least two multiply-accumulator units and associated coefficient memories and data memories. Coefficient memory addresses are formed from a base address and data samples stored in the data memories.Type: GrantFiled: February 28, 2006Date of Patent: February 16, 2010Assignee: Analog Devices, Inc.Inventors: Vladimir Friedman, Michael Hennedy
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Publication number: 20090292757Abstract: A zero prediction method and apparatus for use in a reduced instruction set computer. The zero predictor 115 in use is connected by a controller 110 to an arithmetic unit 120. Different embodiments of the invention for use in addition include inverters 205 connected via incrementers 220 to comparators 235 for subtraction and comparators 235 for decrementation. The method includes determination 915 of which arithmetic operation to be performed, activation 925, 950 and 975 of a suitable zero prediction method for the operation along with the operation subtraction 930, addition 955 and decrementation 980. If a zero is detected, operations 930, 955 and 980 are deactivated.Type: ApplicationFiled: May 23, 2008Publication date: November 26, 2009Inventor: Steven Leeland
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Publication number: 20090271464Abstract: A method of computing at least a first and a second tree of arithmetic or logical operations on a microprocessor comprising at least n parallel processing elements. The method comprises: a) executing (in 48) n arithmetic or logical operations of a first iteration of the first tree in parallel using the n processing elements, then b) executing (in 66) m arithmetic or logical operations in parallel between the results of the first iteration, using m processing elements chosen from the n processing element used for the computation of the first iteration, the other n-m processing element being unused for the computation of the second iteration. In parallel with the computation of the second iteration of the first tree, the method comprises executing (in 66) k arithmetic or logical operations of the second tree in parallel using k processing elements chosen from the n-m so processing elements unused for the computation of the second iteration of the first tree.Type: ApplicationFiled: December 13, 2005Publication date: October 29, 2009Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventor: Bruno Ballarin
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Publication number: 20090265409Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: ApplicationFiled: March 23, 2009Publication date: October 22, 2009Inventors: Alexander D. Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt
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Patent number: 7525457Abstract: A computer implemented method converts a data set of a first type to a data set type of a second type. The method includes casting up a first data set of a first type to a prescribed data set type that is large enough to encompass a data set of a second type. The method then includes casting down the casted up first data set from the prescribed data set type to the second data set of the second data set type.Type: GrantFiled: January 12, 2007Date of Patent: April 28, 2009Assignee: Star Bridge Systems, Inc.Inventor: Kent L. Gilson
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Patent number: 7509367Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: GrantFiled: June 4, 2004Date of Patent: March 24, 2009Assignee: Intel CorporationInventors: Alexander D. Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt
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Publication number: 20090049113Abstract: Embodiments of the invention provide methods and apparatus for executing a multiple operand instruction. Executing the multiple operand instruction comprises computing an arithmetic result of a pair of operands in each processing lane of a vector unit. The arithmetic results generated in each processing lane of the vector unit may be transferred to a dot product unit. The dot product unit may compute an arithmetic result using the arithmetic result computed by each processing lane of the vector unit to generate an arithmetic result of more than two operands.Type: ApplicationFiled: August 17, 2007Publication date: February 19, 2009Inventors: Adam James Muff, Matthew Ray Tubbs
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Publication number: 20090024684Abstract: A method for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.Type: ApplicationFiled: September 26, 2008Publication date: January 22, 2009Applicant: IBM CORPORATIONInventors: Sang Hoo Dhong, Harm Peter Hofstee, Christian Jacobi, Silvia Melitta Mueller, Hwa-Joon Oh
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Publication number: 20080307205Abstract: A method and apparatus perform many different types of algorithms that utilizes a calculation unit capable of utilizing the same multipliers for different algorithms. The calculation unit preferably includes a processor that has a plural number of arithmetic logic unit circuits that are configured to process data in parallel to provide processed data outputs and an adder tree configured to add the processed data outputs from the arithmetic logic circuits. A shift register that has more parallel data outputs then the processor's inputs is controlled to selectively output data from the parallel outputs to the data inputs of the processor. A communication device preferably includes the calculation unit to facilitate processing of wireless communication signals.Type: ApplicationFiled: August 20, 2008Publication date: December 11, 2008Applicant: INTERDIGITAL TECHNOLOGY CORPORATIONInventors: Ryan Samuel Buchert, Chayil S. Timmerman, Stephan Shane Supplee
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Patent number: 7430577Abstract: A method and system for performing many different types if algorithms utilizes a single mathematical engine such that the mathematical engine is capable of utilizing the same multipliers for all of the algorithms. The mathematical engine includes a selectively controlled parallel output register, at least one selectively controlled memory, and a plurality of processing elements. The output register, the memory and the processing elements are selectively controlled depending upon the algorithm to be performed.Type: GrantFiled: September 24, 2003Date of Patent: September 30, 2008Assignee: InterDigital Technology CorporationInventors: Ryan Samuel Buchert, Chayil S. Timmerman, Stephan Shane Supplee
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Patent number: 7424505Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: GrantFiled: November 19, 2001Date of Patent: September 9, 2008Assignee: Intel CorporationInventors: Alexander D. Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt
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Patent number: 7395294Abstract: An arithmetic logic unit is provided. The arithmetic logic unit preferably includes a minimum of routing delays. An arithmetic logic unit according to the invention preferably receives a plurality of operands from a plurality of operand registers, performs an arithmetic operation on the operands, obtains a result of the arithmetic operation and that transmits the result to a result register. The arithmetic logic unit includes a signal propagation path that includes no greater than two routing paths that connect non-immediately adjacent logic elements.Type: GrantFiled: January 10, 2003Date of Patent: July 1, 2008Assignee: Altera CorporationInventor: Paul J. Metzgen
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Publication number: 20080147770Abstract: An input device includes a power unit, a power switch unit, a processing unit, and an input unit. The power switch unit includes a first switch for supplying power to the processing unit when actuated; the input unit is connected with the processing unit and the power switch unit and is configured for generating input signals that is transmitted to the processing unit and further used for controlling the first switch; and the processing unit is configured for receiving the input signal from the input unit, keeping the first switch switched on during a time period, and performing a task corresponding to the input signal during the time period.Type: ApplicationFiled: May 25, 2007Publication date: June 19, 2008Applicants: ENSKY TECHNOLOGY (SHENZHEN) CO., LTD., ENSKY TECHNOLOGY CO., LTD.Inventors: Shin-Hong Chung, Han-Che Wang, Bin-Gang Duan, Shi-Quan Lin, Kuan-Hong Hsieh
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Patent number: 7353244Abstract: According to some embodiments, a dual multiply-accumulate operation optimized for even and odd multisample calculations is disclosed.Type: GrantFiled: April 16, 2004Date of Patent: April 1, 2008Assignee: Marvell International Ltd.Inventors: Bradley C. Aldrich, Nigel C. Paver, William T. Maghielse
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Patent number: 7346761Abstract: An arithmetic and logic device as an integral part of a processing unit is provided to achieve code size and overhead reduction. The arithmetic and logic device contains several auxiliary computing units, each of which is capable of simple arithmetic and logical operation, under the control of a control unit. By configuring the auxiliary computing units along the data path, additional processing to the operands could be carried out within the same instruction cycle. As such, a processing unit incorporating such an arithmetic and logic device is able to achieve significant performance improvement both in terms of code size and memory access overhead.Type: GrantFiled: October 8, 2005Date of Patent: March 18, 2008Assignee: National Chung Cheng UniversityInventors: Tien-Fu Chen, Chih-Heng Kang, Chen-Neng Win
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Publication number: 20080046496Abstract: A touch screen has a keyboard which has several areas of keys. Each area is sizable, including enlarging and shrinking, and movable. Because the sizes of the keys areas are controllable, the keyboard does not occupy the whole screen and the areas are not too small to clearly see the keys. With the present invention, more room is left for flexible operations.Type: ApplicationFiled: December 1, 2006Publication date: February 21, 2008Inventor: Arthur Kater
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Patent number: 7212959Abstract: A method and apparatus for accumulating arbitrary length strings of input values, such as floating point values, in a layered tree structure such that the order of adds at each layer is maintained. The accumulating utilizes a shared adder, and includes means for directing initial inputs and intermediate result values.Type: GrantFiled: August 8, 2001Date of Patent: May 1, 2007Inventors: Stephen Clark Purcell, Scott Kimura, Mark L. Wood Patrick
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Patent number: 7027597Abstract: A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received and another electronic message generated based on the encryption protocol. Two passes of Montgomery's method are used for a modular operation that is associated with the encryption protocol along with pre-computation of a constant based on a modulus. The modular operation may be a modular multiplication or a modular exponentiation. Modular arithmetic may be performed using the residue number system (RNS) and two RNS bases with conversions between the two RNS bases. A minimal number of register files are used for the computations along with an array of multiplier circuits and an array of modular reduction circuits. The approach described allows for high throughput for large encryption keys with a relatively small number of logical gates.Type: GrantFiled: September 18, 2001Date of Patent: April 11, 2006Assignee: Cisco Technologies, Inc.Inventors: Mihailo M. Stojancic, Mahesh S. Maddury, Kenneth J. Tomei
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Patent number: 7027598Abstract: A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received and another electronic message generated based on the encryption protocol. Two passes of Montgomery's method are used for a modular operation that is associated with the encryption protocol along with pre-computation of a constant based on a modulus. The modular operation may be a modular multiplication or a modular exponentiation. Modular arithmetic may be performed using the residue number system (RNS) and two RNS bases with conversions between the two RNS bases. A minimal number of register files are used for the computations along with an array of multiplier circuits and an array of modular reduction circuits. The approach described allows for high throughput for large encryption keys with a relatively small number of logical gates.Type: GrantFiled: September 19, 2001Date of Patent: April 11, 2006Assignee: Cisco Technology, Inc.Inventors: Mihailo M. Stojancic, Mahesh S. Maddury, Kenneth J. Tomei
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Patent number: 7013321Abstract: According to the invention, a processing core that executes a parallel multiply accumulate operation is disclosed. Included in the processing core are a first, second and third input operand registers; a number of functional blocks; and, an output operand register. The first, second and third input operand registers respectively include a number of first input operands, a number of second input operands and a number of third input operands. Each of the number of functional blocks performs a multiply accumulate operation. The output operand register includes a number of output operands. Each of the number of output operands is related to one of the number of first input operands, one of the number of second input operands and one of the number of third input operands.Type: GrantFiled: November 21, 2001Date of Patent: March 14, 2006Assignee: Sun Microsystems, Inc.Inventor: Ashley Saulsbury
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Patent number: 6999985Abstract: A data processing system is provided with an instruction (ADD8TO16) that unpacks non-adjacent portions of a data word using sign or zero extension and combines this with a single-instruction-multiple-data type arithmetic operation, such as an add, performed in response to the same instruction. The instruction is well suited to use within systems having a data path (2) including a shifting circuit (6) upstream of an arithmetic circuit (8).Type: GrantFiled: August 30, 2001Date of Patent: February 14, 2006Assignee: Arm LimitedInventors: Dominic Hugo Symes, David James Seal
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Patent number: 6922716Abstract: A processor includes a first vector processing unit including a first register file and first vector arithmetic logic unit; a second vector processing unit including a second register file and second vector arithmetic logic unit wherein the first register file has a first plurality of cross connections to the second vector arithmetic logic unit; wherein the second register file as a second plurality of cross connections to the first vector arithmetic logic unit.Type: GrantFiled: July 13, 2001Date of Patent: July 26, 2005Assignee: Motorola, Inc.Inventors: Vipul Anil Desai, David P. Gurney, Benson Chau
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Patent number: 6912557Abstract: A math coprocessor 1300 includes a multiply-accumulate unit 1600. Multiplier-accumulate unit 1600 includes a multiplier array 1603 for selectively multiplying first and second operands, the first and second operands having a data type selected from the group including floating point and integer data types. An adder 1604 selectively performs addition and subtraction operations on third and fourth operands, the third and fourth operands selected by multiplexer circuitry from the contents of a set of associated source registers, data output from multiplier array 1603 and data output from adder 1604.Type: GrantFiled: June 9, 2000Date of Patent: June 28, 2005Assignee: Cirrus Logic, Inc.Inventors: Gregory Allen North, Murli Ganeshan
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Patent number: 6889240Abstract: In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chip, an increase in the number of processing steps caused by differing types of data handled by the calculators is prevented, thereby enhancing the efficiency of the digital signal processing.Type: GrantFiled: October 29, 2003Date of Patent: May 3, 2005Assignee: Renesas Technology Corp.Inventors: Atsushi Kiuchi, Yuji Hatano, Toru Baji, Koki Noguchi, Yasushi Akao, Shiro Baba
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Patent number: 6854003Abstract: A circuit is provided which contains memory, logic, arithmetic and control circuitry needed to generate all or part of a frame for use in video processing and animation as well as digital signal and image processing. One or more such circuits are provided on an integrated circuit. A video or image frame generation system is constructed from one or more of these integrated circuits, optionally with additional memory circuitry, to provide exceptional performance in frame production for animation, particularly 3-D and other high performance applications such as medical imaging, virtual reality and real-time scene generation in video games and simulation environments. The circuit(s) are used to process high speed object-oriented graphics related streams such as proposed by MPEG 4, as well as act as a single chip JAVA engine with highly optimized numeric performance.Type: GrantFiled: December 18, 1997Date of Patent: February 8, 2005Assignee: Hyundai Electronics AmericaInventor: Earle W. Jennings, III