Abstract: Method, apparatus, and program means for nonlinear filtering and deblocking applications utilizing SIMD sign and absolute value operations. The method of one embodiment comprises receiving first data for a first block and second data for a second block. The first data and said second data are comprised of a plurality of rows and columns of pixel data. A block boundary between the first block and the second block is characterized. A correction factor for a deblocking algorithm is calculated with a first instruction for a sign operation that multiplies and with a second instruction for an absolute value operation. Data for pixels located along said block boundary between the first and second block are corrected.

Abstract: Method, apparatus, and program means for performing a sign and multiply operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a first source operand multiplied by a sign value of a second source operand. In some embodiments, the first source operand may be overwritten by the result.

Abstract: Method, apparatus, and program means for performing a packed multiply high with round and shift operation. The method of one embodiment comprises receiving a first operand having a first set of L data elements. A second operand having a second set of L data elements is received. L pairs of data elements are multiplied together to generate a set of L products. Each of the L pairs includes a first data element from the first set of L data element and a second data element from a corresponding data element position of the second set of L data elements. Each of the L products are rounded to generate L rounded values. Each of said L rounded values are scaled to generate L scaled values. Each of the L scaled values are truncated for storage at a destination. Each truncated value is to be stored at a data element position corresponding to its pair of data elements.

Abstract: A function block allows a multiplier and a multi-input multiplexer to be realized with a small number of blocks. A logical function generator generates a logical output signal from first to fourth logical inputs thereof according to a logical function selected from a plurality of 4-input/1-output logical functions depending on configuration data. A 4-2 carry block generates a 4-2 carry output from the second to fourth logical inputs. A first signal is generated from at least the logical output, a second signal from at least the first logical input, a third signal from at least a 4-2 carry input signal, and a fourth signal from at least the 4-2 carry input signal. A multiplexer selects one of the second and third signals depending on the first signal to produce a carry output signal. An exclusive OR circuit produce an exclusive-ORed result from the logical output and the fourth signal.

Abstract: An integrated circuit which has two separate paths for two different data widths. The first processing path processes data up to n bits in a n multiplier. A second path operates in parallel with the first path, and includes smaller units which process data up to n 2 bits. The two paths can operate in parallel, but since the two paths have different data widths, they can more effectively operate with the different data sizes.

Abstract: In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chip, an increase in the number of processing steps caused by differing types of data handled by the calculators is prevented, thereby enhancing the efficiency of the digital signal processing.

Abstract: An operation method has processing for applying a same type of operation in parallel to N M-bit operands to obtain N M-bit operation results executed on a computer. Here, N is an integer equal to or greater than 2 and M is an integer equal to or greater than 1. The operation method includes: an operation step of applying the type of operation to an N*M-bit provisional operand that is formed by concatenating the N M-bit operands, to obtain one N*M-bit provisional operation result, and generating correction information based on an effect had, by applying the operation, on each M bits of the provisional operation result from a bit that neighbors the M bits; and a correction step of correcting the provisional operation result in M-bit units with use of the correction information, to obtain the N M-bit operation results.

Abstract: A time-efficient real-time correlator is provided for use in a receiver of a wireless communications system. The correlator correlates a signal received by the receiver with a pseudo-random number (PN) code in order to determine the time delay of the received signal. The correlator requires no memory for storing samples of the received signal. A shift register having only W storage elements is utilized for storing the samples of the PN code sequence, where W is a positive integer corresponding to the length of the correlation window. W+1 correlation results storage elements are utilized to store correlation result values. When the correlator receives a current sample of the incoming signal, the current sample r(j) is multiplied by each of the samples of the PN code sequence to obtain products. The correlation result values stored in the correlation results storage elements are added to the products and the resulting sum is stored in the correlation results storage elements.

Abstract: A method of multiplying 32-bit values includes decomposing each multiplicand into its 16-bit components. This approach leads to a processor core design which permits re-use of much of the logic in the multiplication unit. The multiplication unit includes a selector which can feed various-sized data formats to the same multiplier circuits. Multiple data transformation paths are provided and feed into a single compression circuit and a single configurable full adder circuit.

Abstract: A multiply-accumulate (MAC) unit, having a first binary operand X, a second binary operand Y, a third binary operand, Booth recode logic for generating a plurality of partial products from said first and second operands, a Wallace tree adder for reducing the partial products and for selectively arithmetically combining the reduced partial products with said third operand, a final adder for generating a final sum, and a saturation circuitry for selectively rounding or saturating said final sum is provided. A dual MAC unit is also provided.

Abstract: A tightly coupled dual 16-bit multiply-accumulate (MAC) unit for performing single-instruction/multiple-data (SIMD) operations may forward an intermediate result to another operation in a pipeline to resolve an accumulating dependency penalty. The MAC unit may also be used to perform 32-bit×32-bit operations.

Abstract: The proposed architecture is integrated onto a Digital Signal Processor (DSP) as a coprocessor to assist in the computation of sum of absolute differences, symmetrical row/column Finite Impulse Response (FIR) filtering with a downsampling (or upsampling) option, row/column Discrete Cosine Transform (DCT)/Inverse Discrete Cosine Transform (IDCT), and generic algebraic functions. The architecture is called IPP, which stands for image processing peripheral, and consists of 8 multiply-accumulate hardware units connected in parallel and routed and multiplexed together. The architecture can be dependent upon a Direct Memory Access (DMA) controller to retrieve and write back data from/to DSP memory without intervention from the DSP core. The DSP can set up the DMA transfer and IPP/DMA synchronization in advance, then go on its own processing task. Alternatively, the DSP can perform the data transfers and synchronization itself by synchronizing with the IPP architecture on these transfers.

Abstract: The present invention provides a method and apparatus for performing floating-point operations. The apparatus of the present invention comprises a floating point unit which comprises standard multiply accumulate units (MACs) which are capable of performing multiply accumulate operations on a plurality of data type formats. The standard MACs are configured to operate on traditional data type formats and on single instruction multiple data (SIMD) type formats. Therefore, dedicated SIMD MAC units are not needed, thus allowing a significant savings in die area to be realized. When a SIMD instruction is to be operated on by one of the MAC units, the data is presented to the upper and lower MAC units as 64-bit words. Each MAC unit also receives one or more bits which cause the MAC units to each select either the upper or lower halves of the 64-bit words. Each MAC unit then operates on its respective 32-bit words.

Abstract: A digital signal processor being capable of rapidly operating a number of complex arithmetic formulae as such FFT. The digital signal processor operates data from first input line and data from second input line by a multiplier; operating data from any one of the first and second input lines and data from the first operating means by means of second operating means; and operating the data from any one of the first and second input lines and the data from the first operating means by means of third operating means. The data output from the multiplier is operates with any one from the first and second input lines by first accumulator. Also, the data output from the multiplier is operates with any one from the first and second input lines by second accumulator.

Abstract: The present invention provides a parallel arithmetic apparatus capable of easily performing vector inner product operations as well as efficient matrix operations. The parallel arithmetic apparatus is provided with pairs of registers that record arithmetical elements to be operated and FMACs that perform sum-of-products operations based on the arithmetical elements recorded in these registers, and selectors inserted between the register and FMAC. The selectors input the arithmetical element recorded in the register to the FMAC during a matrix operation, select the registers one by one in a round-robin fashion and supply the arithmetical element recorded in the selected register to the FMAC during a vector inner product operation.

Abstract: A vector processor provides a data path divided into smaller slices of data, with each slice processed in parallel with the other slices. Furthermore, an execution unit provides smaller arithmetic and functional units chained together to execute more complex microprocessor instructions requiring multiple cycles by sharing single-cycle operations, thereby reducing both costs and size of the microprocessor. One embodiment handles 288-bit data widths using 36-bit data path slices. Another embodiment executes integer multiply and multiply-and-accumulate and floating point add/subtract and multiply operations using single-cycle arithmetic logic units. Other embodiments support 8-bit, 9-bit, 16-bit, and 32-bit integer data types and 32-bit floating data types.

Abstract: A method and apparatus that adds each one of multiple elements of a packed data together to produce a result. According to one such a method and apparatus, each of a first set of portions of partial products is produced using a first set of partial product selectors in a multiplier, each of the first set of portions of the partial products being zero. Each of the multiple elements is inserted into one of a second set of portions of the partial products using a second set of partial product selectors, each of the second set of portions of the partial products being aligned. Each of the multiple elements are added together to produce the result including a field having the sum of the multiple elements.

Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

Abstract: In microcomputers and digital signal processorspin which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chippthis invention prevents an increase in the number of processing steps caused by differing types of data handled by the calculators, thereby enhancing the efficiency of the digital signal processing.

Abstract: A circuit is provided which contains memory, logic, arithmetic and control circuitry needed to generate all or part of a frame for use in video processing and animation as well as digital signal and image processing. One or more such circuits are provided on an integrated circuit. A video or image frame generation system is constructed from one or more of these integrated circuits, optionally with additional memory circuitry, to provide exceptional performance in frame production for animation, particularly 3-D and other high performance applications such as medical imaging, virtual reality and real-time scene generation in video games and simulation environments. The circuit(s) are used to process high speed object-oriented graphics related streams such as proposed by MPEG 4, as well as act as a single chip JAVA engine with highly optimized numeric performance.

Abstract: An application specific signal processor (ASSP) performs vectorized and nonvectorized operations. Nonvectorized operations may be performed using a saturated multiplication and accumulation operation. The ASSP includes a serial interface, a buffer memory, a core processor for performing digital signal processing which includes a reduced instruction set computer (RISC) processor and four signal processing units. The four signal processing units execute the digital signal processing algorithms in parallel including the execution of the saturated multiplication and accumulation operation. The ASSP is utilized in telecommunication interface devices such as a gateway. The ASSP is well suited to handling voice and data compression/decompression in telecommunication systems where a packetized network is used to transceive packetized data and voice.

Abstract: A digital signal processor being capable of rapidly operating a number of complex arithmetic formulae as such FFT. The digital signal processor operates data from first input line and data from second input line by a multiplier; operating data from any one of the first and second input lines and data from the first operating means by means of second operating means; and operating the data from any one of the first and second input lines and the data from the first operating means by means of third operating means. The data output from the multiplier is operates with any one from the first and second input lines by first accumulator. Also, the data output from the multiplier is operates with any one from the first and second input lines by second accumulator.

Abstract: A multimedia execution unit configured to perform vectored floating point and integer instructions. The execution unit may include an add/subtract pipeline having far and close data paths. The far path is configured to handle effective addition operations and effective subtraction operations for operands having an absolute exponent difference greater than one. The close path is configured to handle effective subtraction operations for operands having an absolute exponent difference less than or equal to one. The close path is configured to generate two output values, wherein one output value is the first input operand plus an inverted version of the second input operand, while the second output value is equal to the first output value plus one. Selection of the first or second output value in the close path effectuates the round-to-nearest operation for the output of the adder.

Abstract: A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated based upon each operand's most significant bit and a control signal. The effective signs may then be used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components.

Abstract: An apparatus, a processor, a computer system and a method may be used to directly transfer and translate data between a memory format in an integer processing unit and a floating point format in a floating point processing unit. Data is stored in integer registers of the integer processing unit in a memory format and is stored in floating point registers of the floating point processing unit in a floating point format. A direct data link is provided between the integer register file of the integer processing unit and the floating point register file of the floating point processing unit. The direct data link includes a logic circuit which translates data between the memory format and the floating point format.

Abstract: A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data.

Abstract: A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.

Abstract: The present invention generally relates to multiply-accumulate units for use in digital signal processors. Each multiply-accumulate unit includes a multiply unit which is coupled with two or more dedicated accumulators. Because of the coupling configuration, when an instruction specifies which accumulator should be used in executing an operation, the instruction need not specify which multiply unit should be utilized. A scheduler containing a digital signal processor's coupling configuration may then identify the multiply unit associated with the accumulator and may then forward the instruction to the identified multiply unit. Multiply-accumulate units can be configured to execute both scalar and vector operations. For executing vector operations, multiply units and their coupled accumulators are configured such that each may be easily grouped with other multiply units and accumulators.

Abstract: A programmable function block comprises a core logic circuit having a first argument input group consisting of first through fourth argument input terminals, a second argument input group consisting of first through fourth argument input terminals, first through third configuration input terminals, a core logic carry output terminal, a core logic carry generation output terminal, a core logic carry propagation output terminal, a ripple-core logic carry input terminal, and a sum output terminal. Connected to interconnection wires and the first and the second argument input groups, an input block includes eighth input selection units for selecting, as eight input selected signals, eight ones of signals on the interconnection wires, a fixed logic value of “1”, and a fixed logic value of “0”. Connected to the first through the third configuration input terminals, respectively, first through third memory circuits stores, as first through third stored logic values, a logic value of one bit.

Abstract: Along with an arithmetic processing unit and an arithmetic execution unit, another arithmetic processing unit is coupled in parallel to an instruction issue unit. Disposed within one of the arithmetic processing units are an address generation unit, an instruction buffer, an instruction decoder, an arithmetic execution unit, a data memory, and a flag register. The instruction decoder decodes an instruction read from the instruction buffer. If the decoded instruction is an iteration start instruction, the instruction decoder extracts a number of times an iterative process is to be executed that is included in the instruction for forwarding to the address generation unit. The address generation unit exerts control as to the execution and termination of iterative processes.

Abstract: A digital video signal processor using parallel processing includes an input serial-access memory having memory cells in which data is inputted into successive ones of the memory cells in response to a programmed-controlled pointer and a three or more port data memory unit for writing-in data read out from the serial-access memory. An arithmetic logic unit responds to stored-program control to read out data from the data memory, perform a program-prescribed arithmetic operation, and write the result of the arithmetic operation back to the data memory. An output serial-access memory is controlled so that the arithmetic result will be outputted under program control in a sequential manner. Operation of the interconnected components is effected by a stored-program control unit connected to the input serial-access memory, the data memory, the arithmetic logic unit, and the output serial-access memory.

Abstract: A microprocessor circuit is disclosed for instructions on an arithmetic/shift function performing standard operations (e.g., ALU instructions or Shift instructions) on instructions in a first cycle of operation, and a correction circuit responsive to the arithmetic/shift function for modifying the standard results provided by the arithmetic/shift function to results required by a SIMD instruction being executed. The arithmetic/shift function is an instruction provided by either an Arithmetic Logic Unit (ALU) or by a shift instruction. The correction circuit passes data, unchanged for logical instructions but provides condition codes according to the SIMD instruction.

Abstract: A data processor determines an overall extremum value of an input set of array data, with the input set of array data partitionable into a first set of array data and a second set of array data. The data processor includes a pair of compare-select circuits implemented in an adder as well as in an arithmetic-logic unit (ALU), respectively, which operate in parallel for respectively processing the first set and the second set, and for respectively determining first and second extremum values of the first set and the second set, respectively. A first compare-select circuit of the pair of compare-select circuits determines the overall extremum value of the input set of array data from the first and second extremum values. The first compare-select circuit also determines the location of the overall extremum value in the input set of array data.

Abstract: In the case that the bit width of a high-speed internal calculation of CPU or DSP is restricted and the high-speed internal calculation is performed as a fixed-point calculation, and the bit width of the input data of CPU or DSP is different from the bit width of the high-speed internal calculation, the input digital signal is truncated prior to the internal calculation. After the high-speed internal calculation has completed (at step S2-3), the result of the high-speed internal calculation is shifted in the direction reverse to that of the truncation by a predetermined bit width (at step S2-4). Thus, the gain of the output signal of the CPU or DSP is prevented from decreasing while performing the high-speed internal calculation.