Abstract: A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a summer circuit configured to add a feedback signal to a received input, and a latch configured to receive an output of the summer circuit in accordance with a clock signal. A feedback circuit includes a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence, and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input to be provided to the summer circuit of each branch.

Abstract: Embodiments disclosed herein include vector processing carry-save accumulators employing redundant carry-save format to reduce carry propagation. The multi-mode vector processing carry-save accumulators employing redundant carry-save format can be provided in a vector processing engine (VPE) to perform vector accumulation operations. Related vector processors, systems, and methods are also disclosed. The accumulator blocks are configured as carry-save accumulator structures. The accumulator blocks are configured to accumulate in redundant carry-save format so that carrys and saves are accumulated and saved without the need to provide a carry propagation path and a carry propagation add operation during each step of accumulation. A carry propagate adder is only required to propagate the accumulated carry once at the end of the accumulation.

Abstract: A shared parallel adder tree for executing multiple different population count operations on a single datum includes a number of carry-save adders (CSAs) and/or half adders (HAs), arranged in rows, where certain CSAs and HAs are dedicated to a single population count operation, while other CSAs and HAs are shared among two or more population count operations. The datum is applied to the first row in the tree. Partial sums of the number of ones at various locations within the tree are routed to certain CSAs and/or HAs “down” the tree to propagate the particular population count operations. Carry-propagate adders generate at least a portion of the final sum of the number of ones in certain population count operations. An “AND” operation on a particular number of the bits in the datum provides the high order bit of the resulting sum of the particular population count operation.

Abstract: A device may include a compressor. The compressor may receive a first number of inputs, each of the inputs having a predetermined width. The compressor may also compute a one's complement sum of the first number of inputs to generate carry bits having the predetermined width and sum bits having the predetermined width, modify the carry bits by moving a most significant bit of the carry bits to a least significant bit position, and output the modified carry bits and the sum bits.

Abstract: Provided are N-digit addition and subtraction units and N-digit addition and subtraction modules in which borrowing and carrying are not propagated in modules having basic digits. In the units and modules, an output pattern of results of addition and subtraction is predicted based on a relation between an augend and an addend and a relation between a minuend and a subtrahend, respectively, thereby preventing borrowing and carrying from being propagated in modules having basic digits.

Abstract: Herein described is a method and system of implementing integrated circuit logic modules that provide maximum efficiency and minimum energy dissipation. In a representative embodiment, a method of implementing one or more digital signal processing functions comprises determining one or more parameters associated with generating an optimal logic module. The one or more parameters may comprise the circuit area of the logic module and the processing time through a critical path of the logic module. In a representative embodiment, the system comprises a logic module that utilizes four full adders arranged in a tree configuration. In a representative embodiment, the logic module comprises a carry-save accumulator that provides maximum efficiency and minimal energy dissipation.

Abstract: The present invention provides a means for optimization and re-use of hardware in the implementation of Viterbi and Turbo Decoders using carry save arithmetic. Successful provision for each target application requires that two main issues be confronted. These are: merging the computation of summation terms (a2?b2+c2) with (x2+y2+z2); and (a3+b3?c3) with (x3+y3+z3); implementing an efficient method of computing (a4?b4?c4); and merging this computation with (x4+y4+z4). The invention solves both of these issues and successfully merges the Viterbi instructions with a complete reuse of the hardware that is required for the implementation of Turbo instructions. The hardware required by both classes of instructions is optimized by efficiently employing carry save arithmetic.

Abstract: Low density parity check (LDPC) decoding can be mapped to a class of DSP instructions called MINST. The MINST class of instructions significantly enhance the efficiency of LDPC decoding by merging several of the functions required by LDPC decoders into a single MINST instruction. This invention is an efficient implementation of the MINST class of instructions using a configurable three input arithmetic logic unit. The carry output results of the three input arithmetic logic unit enable permit boundary decisions in a range determination required by the MINST instruction. The preferred embodiment employs 2's complement arithmetic and carry-save adder logic. This invention allows reuse of hardware required to implement MAX* functions in LDPC functions.

Abstract: The present invention provides a means for optimization and re-use of hardware in the implementation of Viterbi and Turbo Decoders using carry save arithmetic. Successful provision for each target application requires that two main issues be confronted. These are: merging the computation of summation terms (a2?b2+c2) with (x2+y2+z2); and (a3+b3?c3) with (x3+y3+z3); implementing an efficient method of computing (a4?b4?c4); and merging this computation with (x4+y4+z4). The invention solves both of these issues and successfully merges the Viterbi instructions with a complete reuse of the hardware that is required for the implementation of Turbo instructions. The hardware required by both classes of instructions is optimized by efficiently employing carry save arithmetic.

Abstract: In a computing device that calculates a square of an element in a finite field, a vector representation of the element in the finite field is accepted. The vector representation includes a plurality of elements. The computing device performs a multiplication operation on a base field using the accepted elements, and obtains a multiplication value. The multiplication operation is determined by a condition under which the element in the finite field is placed in an algebraic torus. The computing device performs an addition and subtraction operation using the obtained multiplication value and the accepted elements, and obtains a calculation result of the square of the element. The addition and subtraction operation is determined by the condition. The computing device then outputs the calculation result.

Abstract: In one embodiment, the invention includes a method for compressing video data using redundant binary mathematics. Other embodiments are described and claimed.

Abstract: A method for accumulation of information is described. The information is separated into first portions of MSBs and second portions of LSBs. The first and second portions are respectively input to a first adder and a second adder to provide first and second sums. The first and second sums are output from a first and a second storage device for feedback input respectively to the first and second adder to provide the first and second sums. A carry bit output from the second storage device is generated responsive to each wrap condition associated with the storing of the second sums in the second storage device. The carry bit is fed back to the first adder and fed forward for subsequent consolidation with the first sums respectively output from the first storage device. The first sums and the second sums are respectively accumulated as numbers represented in a redundant number system.

Abstract: An integrated circuit having a digital signal processing (DSP) circuit is disclosed. The DSP circuit includes: a plurality of multiplexers receiving a first set, second set, and third set of input data bits, where the plurality of multiplexers are coupled to a first opcode register; a bitwise adder coupled to the plurality of multiplexers for generating a sum set of bits and a carry set of bits from bitwise adding together the first, second, and third set of input data bits; and a second adder coupled to the bitwise adder for adding together the sum set of bits and carry set of bits to produce a summation set of bits and a plurality of carry-out bits, where the second adder is coupled to a second opcode register.

Abstract: An Arithmetic Logic Unit that includes first multiplexers coupled to a first adder, the first multiplexers controlled by a first opcode register; second multiplexers receiving input from the first adder and coupled to a second adder; and a second opcode register for controlling one or more of the second multiplexers, the first adder, or the second adder. A combination of the bits in the first and second opcode registers configures the ALU to perform one or more arithmetic operations or one or more logic operations or any combination thereof.

Abstract: Methods and apparatus for improving the efficiency of an arithmetic logic unit (ALU) are provided. The ALU of the invention combines the operation of a single-cycle ALU with the processing speed of a pipelined ALU. Arithmetic operations are performed in two stages: a first stage that produces separate sum and carry results in a first cycle, and a second stage that produces a final result in one or more immediately subsequent cycles. While this produces final results in two or more clock cycles, useable partial results are produced each cycle, thus maintaining a one operation per clock cycle throughput.

Abstract: A multi-operand decimal adder is described that performs addition on multiple binary coded decimal (BCD) operands. The multi-operand decimal adder uses binary carry-save adders to produce intermediate sums and carries, and outputs a decimal result based on the intermediate sums and carries. In various configurations, the multi-operand decimal adder may perform speculative or non-speculative binary carry-save addition. The multioperand decimal adders achieve a reasonable critical path. As a result, the decimal adders and the techniques described herein may be especially suited for numerically intensive commercial applications, such as spreadsheet or financial applications where large amounts of decimal data typically need to be processed quickly.

Abstract: Methods and apparatus provide for accumulating bit streams from four partial products and producing a carry-save output pair, including: producing the save, S, portion of the carry-save output pair, in accordance with the following Boolean expression: S=d3 XOR ((d0 XOR d1) XOR (d2 XOR Cin)), wherein d0, d1, d2, d3 are the bit streams from the four partial products, and Cin is a carry in bit stream receivable from an adjacent compression circuit of an overall partial product reduction array.

Abstract: A macrocell including an adder block with a plurality of bit-slice adders, a bypass path and a control unit adapted to receive a carry of a first neighboring macrocell, and to output a carry by generation within the adder block or by passage of the carry of the first neighboring macrocell through the bypass path to a second neighboring macrocell. The control unit is adapted to signal a validity of the carry output of the macrocell depending on a logical combination of states of the two carry output lines. The control unit is further adapted, depending on a validity signal of the first neighboring macrocell indicating a validity of the carry, to prevent forwarding the carry.

Abstract: Provided are a simplified 4:2 carry save adder (CSA) cell and a 4:2 carry save adding method. The 4:2 CSA cell is formed of an odd detector and first through sixth switches through logic optimization. The odd detector generates an XOR of the first through fourth input signals, outputs the XOR as an odd signal, generates an XOR of the first and second input signals, and outputs the XOR as a first XOR signal. The first switch outputs the third input signal as a carry output signal in response to the first XOR signal. The second switch outputs the first input signal as the carry output signal in response to an inverted first XOR signal. The third switch outputs the carry input signal as a carry signal in response to the odd signal. The fourth switch outputs the fourth input signal as the carry signal in response to an inverted odd signal. The fifth switch outputs an inverted carry input signal as a sum signal in response to the odd signal.

Abstract: In one embodiment, a compressor circuit has a carry-in input and input bits a, b, c, and d. The compressor circuit comprises a first multiplexor (mux) coupled to receive a value of input bit a and a complement of the value of input bit a as inputs and a value of the input bit b as a first selection control. The first mux has a first output. Coupled to receive a value of input bit c and a complement of the value of input bit c as inputs and a value of the input bit d as a second selection control, a second mux has a second output. A third mux is coupled to receive the first output and a complement of the first output as inputs and the second output as a third selection control, and the third mux has a third output. The fourth mux, coupled to receive a value of the third output and a complement of a value of the third output as inputs and the carry-in input as a fourth selection control, has a fourth output which is a sum output of the compressor circuit.

Abstract: The invention relates to an adder for adding at least four bits of the same significance w, said adder having a first number of inputs for receiving the bits of the same significance w that are to be added and a number of outputs, the bits to be added being applied to the inputs in presorted form, and the adder adding the bits while taking account of the presorting. The invention also provides an adding device for adding at least four bits of equal significance and a corresponding method.

Abstract: The conventional two's complement multiplier which is constituted by a Booth encoder, a partial production generation circuit, and an adder has a problem that the circuit scale would be increased because a bit extension is performed when the multiplier is adapted to an unsigned multiplication. A multiplication circuit of the present invention is provided with a first Booth encoder (1) for encoding lower-order several bits of a multiplier according to first rules of encoding using a Booth algorithm, and a second Booth encoder (5) for encoding most-significant several bits of the multiplier according to second rules of encoding using a Booth algorithm, which are different from the first rules of encoding, and thereby the most-significant several bits of the multiplier are encoded using the Booth algorithm which is different from that for the lower-order several bits.

Abstract: A circuit and method provides an estimate of a population count (popcount) of a plurality of input bit values. In one form the input bit values represent respective nodes of an integrated circuit. An approximation circuit uses an approximation input stage which receives a plurality of data inputs and has a plurality of logic circuits. Each logic circuit provides a single bit output. The approximation circuit provides monotonic accuracy. A reduction tree receives the single bit outputs of the plurality of logic circuits and provides an approximate count of how many of the plurality of data inputs are asserted. Size and speed are improved by providing the estimate as opposed to an exact value.

Abstract: Methods and apparatus are described for an execution unit. A method includes receiving an instruction and one or more operands, determining a plurality of program bits and one or more sets of pluralities of select input bits, based on the instruction and the one or more operands, determining a plurality of extra adder input bits, based on the instruction and the one or more operands, determining a plurality of multiplexer output bits, based on the plurality of program bits and the one or more sets of pluralities of select input bits, determining one or more carry-save adder tree outputs, based on the plurality of multiplexer output bits and the plurality of extra adder input bits, determining a carry-propagate adder sum output, based on the one or more carry-save adder tree output; and determining the result of the instruction on the one or more operands, based on the carry-propagate adder sum output.

Abstract: Circuitry for reducing propagation delays in calculation of a value for use in a floating point multiply-accumulate operation. In the circuitry, a carry-save adder receives values of three input operands from three latches. A carry-lookahead adder receives the outputs from the carry-save adder and implements an XOR operation on a most-significant bit along with its own logic operation to produce the value for the floating point multiply-accumulate operation. Modification of the carry-lookahead adder to perform the XOR operation results in elimination of an entire stage of logic.

Abstract: A cryptography processor includes a central processing unit and a co-processor, the co-processor comprising a plurality of calculating subunits as well as a single control unit which is coupled to each of the plurality of calculating subunits. A cryptographic operation is distributed among the individual calculating subunits in the form of sub-operations by the control unit. The central processing unit, the plurality of calculating subunits and the control unit are integrated on a single chip, the chip comprising a common supply current access for supplying the plurality of calculating subunits and the control unit with current. Due to the arrangement of the calculating subunit in parallel, on the hand, the throughput of the cryptography processor is increased. On the other hand, however, the current profile that may be detected at the supply current access is randomised to such an extent that an attacker can no longer infer numbers processed in the individual calculating subunits.

Abstract: A cascaded differential domino four-to-two reducer. In an embodiment, the four-to-two reducer is constructed of a first three-to-two reducer and a second three-to-two reducer directly connected to the first three-to-two reducer. In a further embodiment, the first and second three-to-two reducer both include a symmetric carry generate gate.

Abstract: Methods and apparatus for improving the efficiency of an arithmetic logic unit (ALU) are provided. The ALU of the invention combines the operation of a single-cycle ALU with the processing speed of a pipelined ALU. Arithmetic operations are performed in two stages: a first stage that produces separate sum and carry results in a first cycle, and a second stage that produces a final result in one or more immediately subsequent cycles. While this produces final results in two or more clock cycles, useable partial results are produced each cycle, thus maintaining a one operation per clock cycle throughput.

Abstract: A 4-to-2 carry save adder using limited switching dynamic logic (LSDL) to reduce power consumption while reducing the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a first LSDL circuit configured to output a sum bit. The carry save adder may further include a second LSDL circuit configured to output a carry bit. Both the first and second LSDL circuits use a carry generated in the current stage that was previously generated in the previous stage (next lower order bit position). Since the carry is generated in the current stage and not in the previous stage, the delay in outputting the sum and carry bits is reduced and hence the performance of carry save adders is improved. Further, since LSDL circuits were used in the carry save adder, power consumption was reduced while using a small amount of area.

Abstract: A 4-to-2 carry save adder with a reduction in the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a lower order full order coupled to a higher order full adder. The carry save adder may further include a logic unit coupled to the higher order full adder where the logic unit is configured to generate a carry bit to be inputted to the higher order full adder that normally would be generated from the carry save adder located in the previous stage. By generating this carry bit (carry-in bit) in the current stage and not in the previous stage, the delay of the carry-in bit inputted to the higher order full adder is reduced thereby reducing the delay of outputting the sum and carry bits by the higher order full adder.

Abstract: A function block allows a multiplier and a multi-input multiplexer to be realized with a small number of blocks. A logical function generator generates a logical output signal from first to fourth logical inputs thereof according to a logical function selected from a plurality of 4-input/1-output logical functions depending on configuration data. A 4-2 carry block generates a 4-2 carry output from the second to fourth logical inputs. A first signal is generated from at least the logical output, a second signal from at least the first logical input, a third signal from at least a 4-2 carry input signal, and a fourth signal from at least the 4-2 carry input signal. A multiplexer selects one of the second and third signals depending on the first signal to produce a carry output signal. An exclusive OR circuit produce an exclusive-ORed result from the logical output and the fourth signal.

Abstract: A carry save adder circuit for reducing the number of inputs to a lower number of outputs, the carry save adder circuit including four carry save adders, the four carry save adders being arranged in two layers with the first and second carry save adders being arranged in a first of said layers and the third and fourth carry save adders being arranged in a second of the layers, said third and fourth carry save adders being arranged to provide the outputs, the third and fourth carry save adders each receiving at least one output from each of the first and second carry save adders and the first and second carry save adders being arranged to receive at least some of the inputs.

Abstract: In one embodiment, a wordline decoder provides access to cache memory locations when addresses are bypassed directly from arithmetic circuitry in redundant form. The wordline decoder is also designed to provide access to cache memory locations when addresses are received from registers in an unsigned binary form. The combined functionality is provided in a pre-decode circuit by selectively replacing one of a plurality of redundant bit vectors with a constant bit vector when redundant addressing is not enabled.

Abstract: An addition circuit for producing a sum of four redundant binary numbers includes a 4:2 compression adder for receiving each of the operand fields of the four redundant binary numbers, and producing a first sum field and a first carry field therefrom. The addition circuit further includes a 4:3 compression adder for receiving each of the sparse carry-save fields of the four redundant binary numbers, and producing a second sum field therefrom. The addition circuit also includes a 3:2 compression adder for receiving the first sum field, the first carry field and the second sum field, and producing a third sum field and a second carry field therefrom. The third sum field and the second carry field are the final results from addition of the four redundant binary numbers.

Abstract: A compressor of a multiplier according to an embodiment of the present invention includes a first compressor, in which the first compressor includes a first plurality of inputs. The first compressor also includes a summation output, a first carry bit output; and a first plurality of transistor paths connecting each of the first plurality of inputs to the summation output. The compressor also includes a successive compressor, in which the successive compressor includes a second plurality of inputs and a plurality of successive transistor paths connecting at least one of the first plurality of inputs to the first carry bit output and connecting the first carry bit output to at least one of the second plurality of inputs. In one embodiment of the present invention, a first compressor critical transistor stage path level within the first compressor is less than seven and a successive compressor critical transistor stage path level within the successive compressor is less than eight.

Abstract: A compressor of a multiplier according to an embodiment of the present invention includes a first compressor, in which the first compressor includes a first plurality of inputs. The first compressor also includes a summation output, a first carry bit output; and a first plurality of transistor paths connecting each of the first plurality of inputs to the summation output. The compressor also includes a successive compressor, in which the successive compressor includes a second plurality of inputs and a plurality of successive transistor paths connecting at least one of the first plurality of inputs to the first carry bit output and connecting the first carry bit output to at least one of the second plurality of inputs. In one embodiment of the present invention, a first compressor critical transistor stage path level within the first compressor is less than seven and a successive compressor critical transistor stage path level within the successive compressor is less than eight.

Abstract: A sample-to-pixel calculation unit in a graphics system may comprise an adder tree. The adder tree includes a plurality of adder cells coupled in a tree configuration. Input values are presented to a first layer of adder cells. Each input value may have two associated control signals: a data valid signal and a winner-take-all signal. The final output of the adder tree equals (a) a sum of those input values whose data valid signals are asserted provided that none of the winner-take-all signals are asserted, or (b) a selected one of the input values if one of the winner-take-all bits is asserted. The selected input value is the one whose winner-take-all bit is set. The adder tree may be used to perform sums of weighted sample attributes and/or sums of coefficients values as part of pixel value computations.

Abstract: An address generating circuit, in which address generation by a modulo addition is executed at high speed, is provided. The address generating circuit makes, a two input adder that adds an address and a renewing step, a three input adder and subtracter that adds the address and the renewing step and further adds the size of a modulo area to this added result or subtracts the size of the modulo area from this added result, and a selection judging circuit that generates a selection signal for selecting one of the outputs from the two input adder and the three input adder and subtracter, work in parallel and independently. And a multiplexer selects one of the outputted results from the two input adder and the three input adder and subtracter based on the selection signal from the selection judging circuit.

Abstract: An adder circuit is provided that generates the sum and sum complement (sum_) signals by constructing the logic in such a way that various levels of both N-type devices and P-type devices are both “on” at the same when that leg is to be open. The logic is then determined by another level and only one P or N type device is on at a given time. For carry and carry complement (carry_) signals a circuit is provided that is symmetrical with respect to P and N devices. The carry and carry_ signals are generated by inputting the complement signals to the same circuit used to generate the carry signal. The symmetrical P and N type devices are complementary in that associated devices are on or off with respect to each other. Both the carry and carry_ signals are concurrently output. The symmetric nature of the static, dual rail, simultaneous, sum and carry circuits will improve switching performance and minimize the floating body effect that can be found in silicon on insulator (SOI) devices.

Abstract: A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in redundant form to subtract numbers received in redundant form, including numbers received from a bypass circuit. The method includes generating a complemented redundant form of at least one number supplied to the arithmetic circuit in redundant form. It also includes providing an adjustment input to the arithmetic circuit to augment a result produced through the arithmetic circuit to generate a valid outcome in redundant form of a subtraction operation. A carry-save adder structure is used in one preferred embodiment of the current invention to perform a subtraction operation A−B, where B is a number represented by one of its valid carry-sum redundant representations. In order to perform the subtraction operation, each of the carry bits and each of the sum bits in a redundant representation of B are complemented and supplied to the carry-save adder.

Abstract: A partial carry-save format is employed for a finite impulse response filter output representation, thereby reducing a number of flip-flops and hence power. By replacing the least significant bit processing section on the output side of the finite impulse response filter with a combined carry-save adder and carry-propagate adder followed by a register rather than two flip-flops, the present invention reduces the load on the clock and achieves reduced propagation delay. To further improve the performance of the finite impulse response filter, a simpler carry-save adder is employed in the least significant bit section, which is possible due to the use of a single register at an input to each of the carry-save adders rather than two flip-flops, one for a carry output and one for a sum output from the adder.

Abstract: The present invention generally relates to an apparatus and method for efficiently summing the partial product bits produced by a multiplier. Briefly described, in architecture, the apparatus includes a first array of odd/even summation circuitry, a second array of odd/even summation circuitry, and a linear array of adders. The apparatus is configured to add a row of partial product bits produced by a multiplier in multiplying a first operand with a second operand. The first array of odd/even summation circuitry produces a first summation of a portion of the partial product bits. The second array of odd/even circuitry produces a second summation of the other partial product bits. The linear array of adders then adds the first summation and the second summation to produce a carry save representation of a product bit (i.e., a bit of the product produced by multiplying the first operand by the second operand).

Abstract: A small swing reducer circuit. An apparatus includes a first number of input terminals including at least two input terminals coupled to receive a differential small swing signal and a reducer circuit to generate differential, small swing sum and carry output signals based on data received via the input terminals.

Abstract: A compressor circuit suitable for use in an arithmetic unit of a microprocessor includes a first stage, a second stage, a carry circuit, and a sum circuit. The first stage is configured to receive a set of four input signals. The first stage generates a first intermediate signal indicative of the XNOR of a first pair of the input signals and a second intermediate signal indicative of the XNOR of a second pair of the input signals. The second stage configured to receive at least a portion of the signals generated by the first stage. The second stage generates first and second control signals where the first control signal is indicative of the XNOR of the four input signals and the second control signal is the logical complement of the first signal. The carry circuit is configured to receive at least one of the control signals and further configured to generate a carry bit based at least in part on the state of the received control signal.

Abstract: An addition circuit for producing a sum of four redundant binary numbers includes a 4:2 compression adder for receiving each of the operand fields of the four redundant binary numbers, and producing a first sum field and a first carry field therefrom. The addition circuit further includes a 4:3 compression adder for receiving each of the sparse carry-save fields of the four redundant binary numbers, and producing a second sum field therefrom. The addition circuit also includes a 3:2 compression adder for receiving the first sum field, the first carry field and the second sum field, and producing a third sum field and a second carry field therefrom. The third sum field and the second carry field are the final results from addition of the four redundant binary numbers.

Abstract: A compressor circuit suitable for use in an arithmetic unit of a microprocessor includes a first stage, a second stage, a carry circuit, and a sum circuit. The first stage is configured to receive a set of four input signals. The first stage generates a first intermediate signal indicative of the XNOR of a first pair of the input signals and a second intermediate signal indicative of the XNOR of a second pair of the input signals. The second stage configured to receive at least a portion of the signals generated by the first stage. The second stage generates first and second control signals where the first control signal is indicative of the XNOR of the four input signals and the second control signal is the logical complement of the first signal. The carry circuit is configured to receive at least one of the control signals and further configured to generate a carry bit based at least in part on the state of the received control signal.

Abstract: A four-input to two-output adder is disclosed. The four-input/two-output adder includes a sum-lookahead full adder and a modified full adder. The sum-lookahead full adder includes an XOR3 block and an AXOR block for receiving a first input, a second input, a third input, and an input from a forward adjacent adder to generate a first sum signal and a sum-lookahead carry signal, respectively. The modified full adder includes an XOR2 block and a MUX2 block for receiving the first sum signal from the sum-lookahead-full adder, a fourth input, and a sum-lookahead carry signal from a backward adjacent adder to generate a second sum signal and a carry signal, respectively.

Abstract: A five-input/two-output binary adder is disclosed. The five-input/two-output adder includes five inputs and two outputs. Four levels of XOR logic gates are coupled between the five inputs and the two outputs for combining values received at the five inputs and generating a sum value and a carry value at the outputs.

Abstract: The present invention is a 5:2 carry-save-adder (CSA) that receives the five input signals I0, I1, I2, I3 and I4 and computes the two output signals SUM and CARRY. The 5:2 CSA comprises a first level of logic circuitry and a second level of logic circuitry. The first level of logic circuitry comprises a plurality of adders and receives the input signals and generates three intermediate terms T0, T1, and T2. The second level of logic circuitry comprises a carry logic circuit and a sum adder, and uses the intermediate terms to compute the two output signals SUM and CARRY. The 5:2 CSA of the present invention operates using either binary signals or N-NARY signals.

Abstract: A cascaded differential domino four-to-two reducer. In an embodiment, the four-to-two reducer is constructed of a first three-to-two reducer and a second three-to-two reducer directly connected to the first three-to-two reducer. In a further embodiment, the first and second three-to-two reducer both include a symmetric carry generate gate.