Abstract: A pixel circuit and a driving method thereof, and a display panel are provided. The pixel circuit included a data writing circuit, a driving circuit, and a compensation circuit. The data writing circuit is configured to write a data signal to the control terminal of the driving circuit in response to a scan signal; and the compensation circuit is connected with the control terminal of the driving circuit, the first terminal of the driving circuit, the second terminal of the driving circuit and a first voltage terminal, and is configured to store a data signal written by the data writing circuit, to compensate the driving circuit, and to adjust, by coupling, a voltage of the second terminal of the driving circuit.

Abstract: A multi-processor system with processing elements, interspersed memory, and primary and secondary interconnection networks optimized for high performance and low power dissipation is disclosed. In the secondary network multiple message routing nodes are arranged in an interspersed fashion with multiple processors. A given message routing node may receive messages from other message nodes, and relay the received messages to destination message routing nodes using relative offsets included in the messages. The relative offset may specify a number of message nodes from the message node that originated a message to a destination message node.

Abstract: An integrated circuit that includes very large adder circuitry is provided. The very large adder circuitry receives more than two inputs each of which has hundreds or thousands of bits. The very large adder circuitry includes multiple adder nodes arranged in a tree-like network. The adder nodes divide the input operands into segments, computes the sum for each segment, and computes the carry for each segment independently from the segment sums. The carries at each level in the tree are accumulated using population counters. After the last node in the tree, the segment sums can then be combined with the carries to determine the final sum output. An adder tree network implemented in this way asymptotically approaches the area and performance latency as an adder network that uses infinite speed ripple carry adders.

Abstract: A multi-processor system with processing elements, interspersed memory, and primary and secondary interconnection networks optimized for high performance and low power dissipation is disclosed. In the secondary network multiple message routing nodes are arranged in an interspersed fashion with multiple processors. A given message routing node may receive messages from other message nodes, and relay the received messages to destination message routing nodes using relative offsets included in the messages. The relative offset may specify a number of message nodes from the message node that originated a message to a destination message node.

Abstract: A circuit includes a plurality of first counting gates, a first ternary half adder (THA) and a second THA that are connected to the plurality of first counting gates, a third THA configured to receive a sum output signal of the first THA and a sum output signal of the second THA, a first ternary sum gate configured to receive a carry output signal of the first THA and a carry output signal of the second THA, and a second ternary sum gate configured to receive a carry output signal of the third THA and an output signal of the first ternary sum gate, wherein the third THA and the second ternary sum gate may be configured to output voltage signals corresponding to a number of drain voltages among input signals applied to the plurality of first counting gates.

Abstract: Disclosed herein is an apparatus for calculating a cryptographic component R2 mod n for a cryptographic function, where n is a modulo number and R is a constant greater than n. The apparatus comprises a processor configured to set a start value to be equal to R mod n, perform b iterations of a shift and subtract operation on the start value to produce a base value, wherein the start value is set to be equal to the base value after each iteration, set a multiplication operand to be equal to the base value, and perform k iterations of a Montgomery modular multiplication of the multiplication operand with the multiplication operand to produce an intermediate result, wherein the multiplication operand is set to be equal to the intermediate result after each iteration, wherein the shift and subtract operation comprises determining a shifted start value which is equivalent to the start value multiplied by two, and subtracting n from the shifted start value if the shifted start value is greater than or equal to n.

Abstract: The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.

Abstract: Some embodiments provide a method for compiling a neural network program for a neural network inference circuit. The method receives a neural network definition including multiple weight values arranged as multiple filters. For each filter, each of the weight values is one of a set of weight values associated with the filter. At least one of the filters has more than three different associated weight values. The method generates program instructions for instructing the neural network inference circuit to execute the neural network. The neural network inference circuit includes circuitry for executing neural networks with a maximum of three different weight values per filter.

Abstract: A method and a system for selecting items one by one from a set of items in an associative memory array includes determining a density of the set, if the density is sparse, repeatedly performing an extreme item select (EIS) method to select a next one of the elected items from the set and removing the next one from the set to create a next set, and if the density is not sparse, performing a next index select (NIS) method to create a linked list of the elected items and to repeatedly select a next elected item from the set. An associative memory array includes a plurality of associative memory cells arranged in rows and columns where each first cell in a first row and in a first column has access to a content of a second cell in a second row in an adjacent column.

Abstract: A first register has a lane storing first input data and a second register has a lane storing second input data elements. A width of the lane of the second register is equal to a width of the lane of the first register. A single-instruction-multiple-data (SIMD) lane has a lane width equal to the width of the lane of the first register. The SIMD lane is configured to perform a sliding window operation on the first input data elements in the lane of the first register and the second input data elements in the lane of the second register. Performing the sliding window operation includes determining a result based on a first input data element stored in a first position of the first register and a second input data element stored in a second position of the second register. The second position is different from the first position.

Abstract: A processing device including a primary processing unit and at least one secondary processing unit, the primary processing unit being designed to subject primary digital input data to a predefinable first data processing, the secondary processing unit being designed to subject secondary digital input data to a predefinable second data processing, the processing device being designed to delay the second data processing by the at least one secondary processing unit at least intermittently in relation to the first data processing by the primary processing unit.

Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

Abstract: A device may receive a direct memory access request that identifies a virtual address. The device may determine whether the virtual address is within a particular range of virtual addresses. The device may selectively perform a first action or a second action based on determining whether the virtual address is within the particular range of virtual addresses. The first action may include causing a first address translation algorithm to be performed to translate the virtual address to a physical address associated with a memory device when the virtual address is not within the particular range of virtual addresses. The second action may include causing a second address translation algorithm to be performed to translate the virtual address to the physical address when the virtual address is within the particular range of virtual addresses. The second address translation algorithm may be different from the first address translation algorithm.

Abstract: A memory sense amplifier is configurable on command between a current-sensing mode and a voltage-sensing mode. The sense amplifier is intended, in its current-sensing configuration, to read a datum stored in a memory cell connected to the amplifier, and is intended, in its voltage-sensing configuration, to read a datum stored in a bit-line latch connected to the amplifier.

Abstract: Examples of systems, apparatuses, and methods for performing delta encoding on packed data elements of a source and storing the results in packed data elements of a destination using a single vector packed delta encode instruction are described.

Abstract: A method of encoding and an encoder are provided. The method includes generating first one-hot bits for most significant bits (MSBs) and second one-hot bits for least significant bits (LSBs) using input one-hot bits; encoding the first one-hot bits to the MSBs and complementary MSBs through a first logical operation using a cross-connection; and encoding the second one-hot bits to the LSBs and complementary LSBs through a second logical operation using a cross-connection. The encoder includes a first bit generator, a first encoder, a second bit generator and a second encoder.

Abstract: The present disclosure includes apparatuses and methods related to converting a mask to an index. An example apparatus comprises an array of memory cells and periphery logic configured to: generate an indicator mask by resetting, in response to a first control signal, a second digit of a mask different from a first digit of the mask that is set; and convert, in response to a second control signal, a digit position in the indicator mask of the first digit that is set to an identifier value as an index.

Abstract: Disclosed is a system for a facility supporting an access controller, at least one ingress card reader and an auto-enrollment type controller including a front panel having a single button, a controller board, a terminal block for connecting at least the one ingress card reader to the auto-enrollment type controller board and to connect the auto-enrollment type controller to door locks, and a mounting plate, with the auto-enrollment type controller being configured by a user according to operational requirements of the facility by the user asserting the button for a defined period of time.

Abstract: A computer system using virtual memory provides hybrid memory access either through a conventional translation between virtual memory and physical memory using a page table possibly with a translation lookaside buffer, or a high-speed translation using a fixed offset value between virtual memory and physical memory. Selection between these modes of access may be encoded into the address space of virtual memory eliminating the need for a separate tagging operation of specific memory addresses.

Abstract: Methods, products, apparatuses, and systems may provide at least multiplexed audio for a plurality of conferences. A conference attendee may simultaneously listen to the plurality of conferences via the multiplexed audio. Audio corresponding only to a respective conference of the plurality of conferences may be provided to another conference attendee having access to the respective conference. The multiplexed audio may be blocked from one or more other attendees. In addition, a conference operation may be implemented at any time to add a conference, delete a conference, select a subset of conferences, and/or rejoin conferences.

Abstract: The present invention discloses a parameter generating device and the method thereof to generate a parameter for circuit operation in which the parameter corresponds to an N degree polynomial of a characteristic curve while said N is a positive integer. The parameter generating device comprises: a storage circuit to store at least N+1 initial values that are determined by a start value and a unit variation amount; and an parameter calculating circuit, coupled to the storage circuit, to carry out addition calculation for at least [(K?1)×N+1] time(s) if a multiple K is positive or subtraction calculation for at least ?K×N time(s) if the multiple K is negative, so as to generate the aforementioned parameter, wherein the multiple K is derived from a difference divided by the unit variation amount while the difference is a current value minus the start value.

Abstract: A logic circuit computes various modal interval arithmetic values using a plurality of arithmetic function units. A multiplexer gates the desired arithmetic values to a storage register.

Abstract: An information processing device includes: plural input registers including a first input register and a second input register; an added value register; a first adding unit that performs addition processing for stored data of the first input register and stored data of the second input register; a second adding unit that performs addition processing for connected data, which is obtained by connecting the stored data of the first input register and the stored data of the second input register, and stored data of the added value register; and plural output registers in which a processing result of the first adding unit or the second adding unit is stored, wherein in each of given execution cycles, the first adding unit stores a processing result of the first adding unit in any one of the plural output registers and the second adding unit stores a processing result of the second adding unit in any one of the plural output registers.

Abstract: A computer-implemented method includes receiving instructions to execute an analytic, wherein the instructions comprise one or more analytic inputs and a corresponding one or more uncertainty values, and wherein the analytic defines a continuous, monotonic mathematical function. The method includes executing the analytic using the one or more analytic inputs to determine one or more analytic outputs. The method also includes executing an uncertainty calculation to estimate one or more uncertainty outputs corresponding to the one or more analytic outputs, based, at least in part, on the one or more analytic inputs and the corresponding one or more uncertainty values. The method further includes providing the one or more analytic outputs as well as the corresponding one or more uncertainty outputs.

Abstract: In one embodiment, a four-input, four-output bin adder is disclosed. The bin adder comprises a two-by-three, multi-stage, cascaded array of two-input, two-output adder circuits. Each of the bin-adder input signals comprises a numeric data value and an associated address, and the bin adder is adapted to add together (a.k.a. accumulate) the numeric values of only those inputs signals having addresses that are the same. In particular, the inputs and outputs of the two-input, two-output adder circuits are connected together in such a way that each input signal is compared to every other input signal, in a round-robin configuration. If the associated addresses match, then the input signals' numeric data values are added (i.e., accumulated) and output as a single signal comprising the sum of the numeric data values and the common address.

Abstract: There is provided a video signal processing method for performing predetermined signal processing on an input video signal to transmit an output video signal in a form of a specified transmission format through a video signal line including invalid bit polarity setting processing to be performed by an invalid bit polarity setting unit, wherein, when there exists an invalid bit having no data corresponding to data making up the input video signal in the specified transmission format of the output video signal, to count the number of low and high levels of gray-level data of the input video signal to compare a numerical size between the number of low levels and the number of high levels for judgment and to set a polarity of the invalid bit based on the judgment result.

Abstract: Disclosed herein are systems and methods for a signed-magnitude adder based on one's complement logic, where the adder offers enhancements in both speed and chip area consumption. The one's complement based adder includes circuitry for converting operands from their signed-magnitude representations to their one's complement representations, circuitry for adding operands in their one's complement representations, and circuitry for converting the resulting sum into a signed-magnitude format.

Abstract: A Generalized Programmable Counter Array (GPCA) is a reconfigurable multi-operand adder, which can be reprogrammed to sum a plurality of operands of arbitrary size. The GPCA is configured to compress the input words down to two operands using parallel counters. Resulting operands are then summed using a standard Ripple Carry Adder to produce the final result. The GPCA consists of a linear arrangement of identical compressor slices (CSlice).

Abstract: A shared parallel adder tree for executing multiple different population count operations on a single datum includes a number of carry-save adders (CSAs) and/or half adders (HAs), arranged in rows, where certain CSAs and HAs are dedicated to a single population count operation, while other CSAs and HAs are shared among two or more population count operations. The datum is applied to the first row in the tree. Partial sums of the number of ones at various locations within the tree are routed to certain CSAs and/or HAs “down” the tree to propagate the particular population count operations. Carry-propagate adders generate at least a portion of the final sum of the number of ones in certain population count operations. An “AND” operation on a particular number of the bits in the datum provides the high order bit of the resulting sum of the particular population count operation.

Abstract: A unified computation unit for iterative multiplication and division may include an architecture having a unified integer iterative multiplication and division circuit. A method may include a device receiving a dividend and a divisor for a division operation, separating the dividend into two parts based on the determining, and evaluating whether an overflow situation exists based on the two parts. A single-cycle multiplication unit may include a multi-operand addition schema for partial products compression that implements tree-based addition methods for single-cycle multiplication operations.

Abstract: An arithmetic logic unit (ALU) for use within a flight control system is provided. The ALU comprises a first register configured to receive a first operand, a second register configured to receive a second operand, and an adder coupled to the first register and the second register. The adder is configured to generate a sum of the first operand and the second operand and to generate intermediate sums that are used to determine a product of the first operand and the second operand.

Abstract: The OSBS Subtractor Accelerator will enable the subtraction operation to simultaneously subtract all Bits of a data set, where: no ripple affect, no complement operations; therefore no multiple additions, no multiple moves, no temporary storage and no multiple instruction steps are required. In stand alone (pure) format the required time is six propagation delays to perform a subtraction operation. Beside the pure format a distributed or grouped format is available; which is dividing both input operands into groups. This grouped configuration also performs a parallel operation on the bits and on the groups in the same time. However, it needs nine propagation delays to execute a subtraction operation (including the first and second XOR gates); regardless it is a 16, 32 or 64 bit subtractor. It uses considerably less number of components than the pure configuration, and none of the integrated circuits have more than 5 input pins.

Abstract: A processor includes a two's complement arithmetic unit that reduces a level of complexity in the critical path by eliminating the addition of the “1” to the carry in of the two's complement arithmetic unit. To execute a subtraction instruction using two's complement arithmetic, the subtraction as disclosed herein is performed in accordance with the identity “A?B=not (not (A)+B),” where A is a first operand and B is a second operand that is to be subtracted from A. Accordingly, the addition of the “1” term into the carry in is eliminated, and reduces a level of complexity that would otherwise slow down and/or limit the speed at which a subtraction instruction can be performed.

Abstract: Disclosed are an accumulator for reducing nonlinearity of a data converter and a data weighted average device including the accumulator. According to the accumulator including a register configured to output input data according to a clock signal; a first adder configured to receive a digital input signal having any bit width and an output signal from the register to perform an add operation; a preset unit configured to output a preset value or a 0 value according to whether a carry of the first adder is generated; and a second adder configured to receive an output signal of the first adder and an output signal of the preset unit to perform the add operation and input the add operation to the register and the data weighted average device including the accumulator, it is possible to improve the nonlinearity occurring in the data converter by generating a number of DAC codes in addition to 2n DAC codes.

Abstract: A digital signal processing block with a preadder stage for an integrated circuit is described. The digital signal processing block includes a preadder stage and a control bus. The control bus is coupled to the preadder stage for dynamically controlling operation of the preadder stage. The preadder stage includes: a first input port of a first multiplexer coupled to the control bus; a second input port of a first logic gate coupled to the control bus; a third input port of a second logic gate coupled to the control bus; and a fourth input port of an adder/subtractor coupled to the control bus.

Abstract: A dividing unit sets an actual packet length transferred from a packet receiving section to a variable U, and then sets 2? to a variable V. If a positive number determining section determines that a subtraction result of subtracting a remainder N0 from a quotient M0, both found by dividing U by V, is a positive number, the dividing unit overwrites the subtraction result to U. The dividing unit repeats such operations of dividing the subtraction result by V, until the positive number determining section determines that the subtraction result of subtracting the remainder from the quotient, both found by dividing U by V, is a non-positive number. When the subtraction result becomes a non-positive number and the quotient and the remainder match, a packet length determining section determines that received data has a normal size, and notifies it to a discard determining section.

Abstract: An analog optical adder system that achieves high precision results. The system uses an analog optical carry function to provide a result having a precision higher than the precision of the individual elements of the system. The optical carry function is created by optical carry determinators that are configured to add an optical carry, if any, to an optical signal associated with a next adjacent byte of the digital signals being added. The use of optical carry enables greater overall addition precision.

Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.

Abstract: A nonvolatile full adder circuit comprising a full adder electrical circuitry comprising three input terminals for receiving two input and carry-in signals, a sum output terminal, and an carry-out output terminal; first and second nonvolatile memory elements electrically coupled to the first and second output terminal, respectively at their first ends and to an intermediate voltage source at their second ends. The nonvolatile memory elements comprise two stable logic states. A logic state each of the of the nonvolatile memory elements is controlled by a bidirectional electrical current running between its first and second ends. The full adder circuitry is electrically coupled to a high voltage source at its first source terminal and to a low voltage source at its second source terminal, wherein an electrical potential of the intermediate voltage source is lower than that of the high voltage source but higher than that of the low voltage source.

Abstract: A system is used to determine if a sum of a first operand and a second operand is the same as a third operand wherein a comparison to the third operand is of variable length. This is particularly useful in a content addressable memory (CAM) where the likelihood of hit is commonly improved over a set associative cache and allows for the CAM to identify different things. For example, an entry can be one length to identify a page of a memory and another entry be a different length to identify a page of memory. This is better understood by reference to the following description and the drawings.

Abstract: For calculating a result of a modular multiplication with long operands, at least the multiplicand is divided into at least three shorter portions. Using the three shorter portions of the multiplicand, the multiplier and the modulus, a modular multiplication is performed within a cryptographic calculation, wherein the portions of the multiplicand, the multiplier and the modulus are parameters of the cryptographic calculation. The calculation is performed sequentially using the portions of the multiplicand and using an intermediate result obtained in a previous calculation, until all portions of the multiplicand are processed, to obtain the final result of the modular multiplication.

Abstract: A method of simplifying a combinational circuit establishes an initial combinational circuit operable to calculate a set of target signals. A quantity of multiplication operations performed in a first portion of the initial combinational circuit is reduced to create a first, simplified combinational circuit. The first portion includes only multiplication operations and addition operations. A quantity of addition operations performed in a second portion of the first, simplified combinational circuit is reduced to create a second, simplified combinational circuit. The second portion includes only addition operations. Also, the second, simplified combinational circuit is operable to calculate the target signals using fewer operations than the initial combinational circuit.

Abstract: Computer-implementable recursive summation algorithms are disclosed that are useful for efficiently performing recursive convolution, such as is often required in Statistical Signal Analysis (SSA) techniques. The disclosed recursive summation algorithms can be more computationally-efficient from both a speed and memory perspective than other recursive convolution techniques known in the prior art, such as the techniques relying on Fast Fourier Transforms (FFTs).

Abstract: An apparatus and method for generating a codebook in a wireless communication system are disclosed. The codebook generation method includes determining one or more dominant singular vectors in a channel matrix for antennas and setting each of the dominant singular vectors as a random non-zero vector, generating a first codebook having codewords, a minimum distance between the code-words being maximized, using the random non-zero vector in a region that includes unit norm vectors each having a Euclidean distance to each of the dominant singular vectors, equal to or less than a predetermined value, generating a second codebook corresponding to a unitary matrix that rotates the random non-zero vector toward the dominant singular vectors, and generating a final codebook using the first and second codebooks.

Abstract: Methods and a system are disclosed for one or more appliances including a controller for managing power consumption within a household. The controller is configured to receive and process a signal indicative of one or more energy parameters of an associated energy utility, including at least a peak demand period or an off-peak demand period. A generated serial number is obtained from an original serial number of the appliance or controller, which is configured for a signal to communicate to the appliance within a population and command the appliance to operate in an energy savings mode and a normal mode at various time periods. The generated serial number (GSN) is used to segregate a total population into segments to provide granularity in assigning DR activations and deactivations based upon the GSN.

Abstract: Memories and methods for performing an atomic memory operation are disclosed, including a memory having a memory store, operation logic, and a command decoder. Operation logic can be configured to receive data and perform operations thereon in accordance with internal control signals. A command decoder can be configured to receive command packets having at least a memory command portion in which a memory command is provided and data configuration portion in which configuration information related to data associated with a command packet is provided. The command decoder is further configured to generate a command control signal based at least in part on the memory command and further configured to generate control signal based at least in part on the configuration information.

Abstract: A machine for tracking job completion is disclosed. The machine for tracking job completion includes a software program that users can execute. Users are classified as either parents or children. Users classified as parents are allowed to use an assign jobs utility, an assign reward utility, a family member definition utility, and a parent send message utility. Parents use these utilities to define and assign jobs to a child and define and assign rewards the child can earn by completion of the jobs. Users classified as children are allowed to use a job credit utility, a reward purchase utility, an organize points utility, and a child send message utility. Children use these utilities to track job completion and purchase rewards earned by job completion. Child users can spend earned points on rewards that allow them to save money or rewards points, and/or contribute their earned money to charity.

Abstract: Methods and a system are disclosed for one or more appliances including a controller for managing power consumption within a household. The controller is configured to receive and process a signal indicative of one or more energy parameters of an associated energy utility, including at least a peak demand period or an off-peak demand period. A generated serial number is obtained from an original serial number of the appliance or controller, which is configured for a signal to communicate to the appliance within a population and command the appliance to operate in an energy savings mode and a normal mode at various time periods. The generated serial number (GSN) is used to segregate a total population into segments to provide granularity in assigning DR activations and deactivations based upon the GSN.

Abstract: According to one embodiment of the invention, a summing circuit comprises a first transmitter, a second transmitter, a first current offset circuit and a first transconductance amplifier. The first current offset circuit is coupled to the emitters of the first and second transistors. The first transconductance amplifier is coupled to the first current offset circuit.

Abstract: A system for processing an image including multiple pixels and intensity data thereof. An image memory is adapted for storing the image. An arithmetic core is connectible to the image memory and adapted for inputting the intensity data. The arithmetic core includes a multiple function processing units. One or more of the function processing units includes (i) a processing core adapted for computation of a function of the intensity data and for producing results of the computation, (ii) a first and (iii) a second accumulator for summing the results; and storage adapted to store the results. The function processing units are configured to compute the functions in parallel and sum the results simultaneously for each of the pixels in a single clock cycle.