Abstract: Hybrid adder circuitry is provided for integrated circuits such as programmable integrated circuits. The hybrid adder may combine the capabilities of multiple adder architectures. Hybrid adders may include carry select and carry ripple adder circuits. The adder circuits may be combined using a carry look-ahead architecture. Adder functionality may be implemented using the resources of logic regions on the programmable integrated circuits. Each logic region may include combinatorial logic such as look-up table logic and register circuitry. The hybrid adder circuitry may receive input words to be added from the combinatorial circuitry and may produce corresponding arithmetic sum output signals to the register circuitry.

Abstract: An n bit adder includes first computing circuit with 2n inputs for receiving n values of bits of first and second binary numbers and an additional input for receiving an input carry digit. The first computing circuit elaborates from each of the n pairs of bit values of the same significance, a carry digit propagating signal and diagonal generation signals. The adder further including: an estimating circuit performing a first estimation of each coefficient of the number resulting from the sum of the first and second numbers, by using the complement of the corresponding bit of significance of the first number; a second computing circuit, elaborating a set of correcting signals based on the propagating signals and the diagonal generation signals; a correcting block applying to each estimated value of bit of significance k of the sum, k+1 corrections using the correcting signals, and delivering n bits of the sum.

Abstract: A carry look-ahead adder may include: a carry generation circuit to generate carry propagation bit values and carry kill bit values for M blocks based on an N-bit addend and augend; a block carry circuit to generate block carry signals based upon the bit values; a Manchester-carry-chain configured bit carry circuit to generate first bit carry signals where a block carry exists in each of the M blocks and second carry bit signals where no block carry exists, based on the bit values; a control circuit to generate, independently of a clock enable signal at a logical level, selection-control signals based upon the block carry signals; and a summation selection circuit to select between the first bit carry signals and the second bit carry signals and to add the carry propagation bit values and the selected carry signals.

Abstract: Provided is an architecture (hardware implementation) for an authentication engine to increase the speed at which SHA1 multi-loop and/or multi-round authentication algorithms may be performed on data packets transmitted over a computer network. As described in this application, the invention has particular application to the variant of the SHA1 authentication algorithms specified by the IPSec cryptography standard. In accordance with the IPSec standard, the invention may be used in conjunction with data encryption/encryption architecture and protocols. However it is also suitable for use in conjunction with other non-IPSec cryptography algorithms, and for applications in which encryption/decryption is not conducted (in IPSec or not) and where it is purely authentication that is accelerated. Among other advantages, an authentication engine in accordance with the present invention provides improved performance with regard to the processing of short data packets.

Abstract: Logic circuit for generating carry or sum bit output by combining binary inputs, includes bit level carry generate and propagate function logic receiving binary inputs and generating bit level carry generate/propagate function bits for binary inputs by respectively logically AND and OR combining respective bits of binary inputs; logic generating high output if a carry is generated out of a first group of most significant bits of binary input or if carry propagate function bits for the most significant bits are all high; logic for receiving bit level carry generate and propagate function bits for binary inputs to generate high output if any of carry generate function bits for the most significant bits are high or if carry is generated out of another group of least significant bits of binary input; and logic for generating the carry or sum bit output by combining outputs of the two logics.

Abstract: A 64-bit adder implemented in partially depleted silicon on insulator technology and having two levels of lookahead uses a dynamic eight-bit carry module containing a differential pass-gate evaluation tree employing a chain of source followers that feeds a sense amplifier, thereby obtaining benefits from high initial drive, low variation in body voltage, resulting in low variation in history-dependent delay, reduced noise sensitivity and noise-based delay.

Abstract: Bit blocks for an adder are provided which include a first bit stage that generates a first bit associated propagation characteristic (bapc). The bapc is independent of a carry input to the bit block from another bit block of the adder. Additional bit stages may be included in the bit block such as a second bit stage that, based on the first bapc, generates a second bapc that is also independent of the carry input to the bit block. The first and second bapc may be generated based on first and second operand bits input to the respective stages and a bapc that is generated by a less significant bit stage of the bit block and is independent of the carry input to the bit block. Adders including the bit blocks and methods for adding using the bit block as well as bit block size optimization methods are also provided.

Abstract: A method for computing a sum or difference and a carry-out of numbers in product-term based programmable logic comprising the steps of: (A) generating (i) a portion of the sum or difference and (ii) a lookahead carry output in each of a plurality of logic blocks; (B) communicating the lookahead carry output of each of the logic blocks to a carry input of a next logic block; (C) presenting the lookahead carry output of a last logic block as the carry-out.

Abstract: Apparatus and method for performing fast arithmetic operations, including addition, in a pipelined circuit. In one embodiment, the apparatus comprises a plurality of gates, the critical path through the plurality of gates being three gates delays for some embodiments. The apparatus may comprise: a first level of logic for receiving at least two binary numbers and generating multi-bit P, G, Z, and K carry signals; a second level of logic receiving the multi-bit P, G, Z, and K carry signals and generating multi-bit section-based carry signals; and a third level of logic receiving the multi-bit section-based carry signals and generating a sum of the received binary numbers, the third level of logic comprising: a plurality of domino logic gates forming sum bits using the multi-bit section-based P, G, Z, and K carry signals.

Abstract: Calculating unit having adder blocks, each having single adders, a carry input, a carry output, and a carry pass output, wherein a signal at the carry pass output is indicative of a carry passing through the adder block. Depending on the carry pass output signal, a clock generator for feeding the adder blocks with operands to be processed is decelerated. A determining unit determines in which of the adder blocks a least significant bit of an operand to be subtracted is disposed. A deactivating unit deactivates a carry pass output of adder block(s) provided for lower order digits with respect to the adder block in which the least significant bit is disposed, and a feeding unit feeds a carry into the carry input of this adder block in which the least significant bit is disposed.

Abstract: A calculating unit comprises several adder blocks with single adders, a clock generator and control means. A carry pass means is associated with each adder block, which determines whether a carry passes fully through the respective adder block. If it is determined that the carry does not pass through any of the adder blocks, the calculating unit is clocked with a clock period, which is sufficient that the carry passes almost fully through an adder block, and passes through at least part of the upstream adder block. If it is determined, that the carry passes fully through an adder block, a panic signal is generated. The adder block is decelerated, so that the clock period is high enough that the carry additionally fully passes through another adder block. Only in a case of panic signals of two adjacent adder blocks, is the calculating unit is decreased so much, that the carry passes from the least significant digit of the calculating unit to the most significant digit of the calculating unit.

Abstract: A carry look-ahead adder capable of adding or subtracting two input signals includes first stage logic having a plurality of carry-create and carry-transmit logic circuits each coupled to receive one or more bits of each input signal. Each carry-create circuit generates a novel carry-create signal in response to corresponding first bit-pairings of the input signals, and each carry-transmit circuit generates a novel carry-transmit signal in response to corresponding second bit-pairings of the input signals. The carry-create and carry-transmit signals are combined in carry look-ahead logic to generate accumulated carry-create signals, which are then used to select final sum bits.

Abstract: The inventive mechanism encodes the carry in as well as the operand bits for each place in a binary addition of two streams of bits. The carry ins are encoded as Propagate (Pin), Kill (Kin), and Generate (Gin), with respect to the carry in to a block of bits. Only one of the signals would be high at any time, and the other two would be low. The Pin signal for a bit is true where the bit has a carry in that is the same as the carry in to the block of bits, i.e., the carry in to the block is propagated up to the particular bit. The Kin signal for a bit is true where a carry in to the bit is zero regardless of the carry in to the block, i.e., any carry in to the block is killed before it gets to the bit. The Gin signal for a bit is true where the bit has a carry in of one regardless of carry in to the block, i.e., the carry in to the bit is generated within the block. These signals are used in the calculation of the sum of the operand bits.

Abstract: An adder circuit for determining the sum of two operands including a set of PGK circuits, at least one tier of group circuits, and a carry generation circuit. The PGK circuits are configured to generate propagate, generate, and kill bits corresponding to at least a portion of the first and second operands. The group circuit receives propagate, generate, and kill bits from a plurality of the PGK circuits and produces a set of group propagate, generate, and kill values. The carry generation circuit receives a carry-in bit and the outputs of at least one of the group circuits and generates a carry-out bit representing the carry-out of the corresponding group. Each generate bit is the logical AND of its corresponding bits in the first and second operand while each propagate bit is the EXOR of its corresponding bits, and each kill bit is the logical NOR of its corresponding bits.

Abstract: Bit blocks for an adder are provided which include a first bit stage that generates a first bit associated propagation characteristic (bapc). The bapc is independent of a carry input to the bit block from another bit block of the adder. Additional bit stages may be included in the bit block such as a second bit stage that, based on the first bapc, generates a second bapc that is also independent of the carry input to the bit block. The first and second bapc may be generated based on first and second operand bits input to the respective stages and a bapc that is generated by a less significant bit stage of the bit block and is independent of the carry input to the bit block. Adders including the bit blocks and methods for adding using the bit block as well as bit block size optimization methods are also provided.

Abstract: In one embodiment, an adder is sectioned into a plurality of operational blocks; namely, a first block, second block, and third block. The first block in a first section generates sum bits and a section carry signal. The second block in the second section generates a second plurality of sum bits and a first block carry signal. A third block in the second section receives both the section carry signal and the first block carry signal. The third block includes a carry processor which receives the section carry signal and outputs a second block carry signal corresponding to the third block.

Abstract: A high-speed carry-lookahead binary adder is disclosed. The binary adder includes multiple rows of carry-lookahead circuits, a half-sum module, and a sum/carry module. A first carry-lookahead circuit row includes multiple eight-bit group generate circuits and multiple eight-bit group propagate circuits. Each of the eight-bit group generate circuits produces a generate signal for a corresponding bit location. Each of the eight-bit group propagate circuits produces a propagate signal for a corresponding bit location. The half-sum module is utilized to generate a half-sum signal. By utilizing the half-sum signal, the generate signals, and the propagate signals, the sum/carry module generates sum signals and a carry signal.