Abstract: A module connection assembly connects modules in a torus configuration that can be changed remotely. In particular, a single module can be added to or deleted from the configuration by remotely switching from conducting paths that provide end-around electrical paths to conducting paths that provide pass-through electrical paths. The assembly includes two backplanes, a first set of module connectors for electrically connecting modules to one of the backplanes, and a second set of module connectors for electrically connecting modules to the other backplane. The assembly further includes configuration controllers. Each configuration controller selects between end-around electrical paths that electrically connect multiple module connectors of the first set to each other, and pass-through electrical paths that electrically connect module connectors of the first set to module connectors of the second set.

Abstract: In one embodiment of the present invention, a wireless USB architecture includes a transmitting device and a receiving device. The transmitting device includes a USB port to which a USB peripheral device can be connected, a conversion circuit for translating from USB protocol to RF protocol, and an RF transmitter for transmitting RF signals to the receiving device. The receiving device includes an RF receiver, a conversion circuit for translating from RF protocol to USB protocol, and a USB port which can be connected to the USB port of a computer.

Abstract: In order to overcome the relatively short battery life and the relatively long delay between the activation and the actual functioning of a typical mobile computing system, the mobile computing system is provided with a personal computer (PC) architecture system and a personal digital assistant (PDA) architecture system, and a common display and shared peripherals. Interfacing to the systems is a super input output or embedded controller (SIO/EC) that acts as a slave device to whatever system has control of computing system. The SIO/EC controls a quick switch which blocks or allows communication along communication busses connecting the systems to the SIO/EC. A user can selectively change, by way of a user interface to the SIO/EC, to whatever system that is desired by the user.

Abstract: A microcomputer capable of efficiently accessing a plurality of devices with different access speeds through a shared bus. If, during access to a first device in compliance with a first access request, a second access request for a second device is issued from a CPU, an access completion time determination section determines the relation of order in time between the completion time of the access to the first device and the earliest time at which the access to the second device can be completed. If it is judged by the access completion time determination section that the access to the second device can be completed earlier than the completion time of the access to the first device, a bus access section accesses the second device in compliance with the second access request during the processing cycle of the access to the first device in compliance with the first access request.

Abstract: A system for coupling a disk drive to a CPU subsystem to produce a single server unit capable of providing network or other services. Further, a plurality of such server units may be aggregated to create server farms.

Abstract: A network system includes a network having a network bus, such as unshielded differential twisted-pair wires, electrically connected to a plurality of remote devices, and a network controller for digitally directing transmissions with the remote devices via the network bus. The network system also includes a plurality of network device interface elements adapted to interconnect the network controller with respective remote devices via the network bus. Each network device interface element is capable of transmitting and receiving messages via the network bus. And to at least partially limit electromagnetic emissions from the respective network device interface element and/or the respective remote device, each network device interface element includes a suppression assembly. Additionally, each network device interface element can include a transceiver and a processing element, with the suppression assembly electrically connected between the transceiver and the network bus.

Abstract: A CPU which performs video processing, and a network processor which performs network processing share a PCI bus. Video data is transmitted to a wireless LAN via the PCI bus.

Abstract: An arrangement is provided for ingress throttling via adaptive interrupt delay scheduling. When packets are received, a receive interrupt is issued with a delay determined based on the backlog information of an associated host, gathered from the number of packets returned from the host after the completion of processing previously delivered packets.

Abstract: A transmission managing apparatus included in an information transmitting system comprising a serial bus, an IRM node, which has a resource register for storing a channel used for an information transmission executed in a time division manner on the serial bus and a transmission occupation period occupied for the information transmission, for indicating the channel and the transmission occupation period and a general node for insuring a non-used channel and a preservable period, which is the transmission occupation period, that can be occupied, while referring to a memory content of the transmission state memory, to thereby carry out the information transmission. The transmission managing apparatus is provided with: a comparator for monitoring whether or not the memory content is updated; and a command generator for reporting a fact of the updating through the serial bus to the general node when updated.

Abstract: The disclosed embodiments relate generally to remote server management technology. More particularly, the embodiments relate to improving the ability of remote server management tools to snoop large amounts of data, including graphical video data, from a communication bus. When snooping the communication bus for data, there is a risk that a storage device gathering the data will be overrun when the volume of relevant data snooped is high. The embodiments relate to a method and apparatus for passively throttling the communication bus to prevent overrun of devices storing snooped data.

Abstract: A system and method of partitioning a multiprocessor or multinode computer system containing two or more partitions each of which contain at least three nodes or processors and a central hardware device communicating with a requestor node or processor, a target node or processor and at least one additional node or processor in the partition. The multiprocessor system architecture allows for partitioning resources to define separate subsystems capable of running different operating systems simultaneously. The method operates with the central device, a tag and address crossbar system, which transmits requests for data from the requestor node to the target node, but not to any of the additional nodes or processors which are not defined as part of a given partition. The method provides steps of assignment of definitions to physical ports with the central device corresponding with desired partitioning of resources within the system.

Abstract: An interfacing logic is implemented in one or more processors and a memory controller in a multiprocessor system. The interfacing logic enables all processors to receive snoops and snoop responses substantially at the same time by delaying data transmitted over faster busses before the data is provided to a local logic at a receiving end of the faster busses. The interfacing logic comprises two or more paths of a multiplexer component connected to a storage component. The storage components are connected to another multiplexer component for selecting one of the two or more paths. Preferably, a bus control logic in the receiving end determines how much delay is performed to compensate for delay differences between data busses.

Abstract: Briefly, in accordance with one embodiment of the invention, a circuit includes: a physical arrangement of power transistors. The circuit is adapted to couple a node to a power bus segment.

Abstract: A computing network uses Time Division Multiplexing (TDM) to divide the time on a bus into a plurality of frames, each frame having a plurality of time slots. Each time slot is assigned no more than one of the plurality of devices within a collision domain, the assignments indicating the identity of the device permitted to transmit packets onto the network during the assigned time slot. A bus cadence unit simultaneously sends an epoch packet initiating the frame. The epoch packet contains a time slot assignment table containing the time slot assignments, the device identification, as well as a time slot offset and duration. Each device on the network is configured to measure a frame interval between repeating epoch packets. The measured frame interval is further processed in each receiving node to obtain a calibrated frame interval. The calibrated frame interval is used to accurately synchronize transmissions of data from the various devices onto the network.

Abstract: A method of searching for a report in a database including a plurality of items generated by multiple users. Users are allowed to create an item with a plurality of fields. The item is stored in a database with an identifier corresponding to the user. Upon receipt of a search query, the database is searched using the search query. The identifiers of a plurality of items found during the search are displayed. Upon selection of the associated identifier of one of the items, the fields of that item are depicted.

Abstract: A system on a chip (SOC) integrated circuit is disclosed. The SOC integrated circuit includes a plurality of logic functions. The logic functions include a plurality of base functions and a plurality of peripheral functions. The SOC integrated circuit includes at least one field programmable gate array (FPGA) cell that is coupled to the plurality of peripheral functions. The FPGA cell can then be configured to selectively enable the plurality of peripheral functions. Accordingly, one or more FPGA cells are provided on an SOC. The FPGA cells can then be selectively configured to enable one or more peripheral chip functions. Because FPGAs are customized “in the field”, i.e., in a specific customer application, one SOC part number containing all peripheral functions can be used to satisfy multiple customer markets.

Abstract: A transmission management device of a server utilizing a serial port RS232 and a bus to manage the server and to transmit data. The transmission management device includes a transmission system, a control system and an I/O (Input/Output) system. The transmission system is used for connecting independent sub-systems in the server and transmitting data. The control system is used for receiving data from an external system and interrupt signals from the Interrupting Processing Unit and for communicating with the transmission system directly. The I/O system outputs and inputs the data from the external system into the bus between the transmission system and the control system, achieving the objective of transmitting data and managing the sub-system through the server.

Abstract: A communications apparatus having: a communication cable receptacle having signal terminals and power supply terminals for connection to a communication cable having signal lines and power supply lines; a communication interface for transferring a signal to and from an external via the signal terminals of the communication cable receptacle; and one or a plurality of light emitting elements capable of emitting light, the light emitting element being disposed near the communication cable receptacle, being selectively connected to the power supply terminals of the communication cable receptacle, and being capable of displaying at least one of a communication state, a state of the apparatus, an alarm state, and a connection state of the apparatus while receiving a power from the communication cable via the power supply terminals.

Abstract: A method and apparatus for operating and actuating remote devices using a single pair of wires together with communication and networking protocols necessary for operational control of the remote devices and data gathering activities from the remote devices. The invention leverages the use of existing wiring and is particularly useful in heating and air conditioning systems, sprinkler control systems, security systems, lighting control systems, industrial automation control systems and similar environments.

Abstract: Multiple voice channels are aggregated into a packet having a segmented data structure and sent over a packet network. The segmented data structure includes segment IDs, corresponding data segments and a packet header arranged so that all data is aligned on 8-byte boundaries for efficient processing by 64-bit processors. The data segment represents one or more milliseconds of digitized voice data, and the segment ID explicitly identifies the voice channel associated with the digitized voice data without reference to any other data in the data structure.

Abstract: An internal processor/memory bus contains an address portion for transmitting addresses and commands, having a series of hierarchical uni-directional links between processors and local repeaters (ARPs), and between the ARPs and a central repeater (ASW). A command propagates from a requesting device to its local ARP, to the ASW. From the ASW, the command is broadcast to all devices on the bus by transmitting to all ARPs or directly attached memory, and from the ARPs to the devices. Preferably, the ASW globally arbitrates the address bus, and all commands propagate at pre-defined clock cycles through the bus. Preferably, each device on the bus independently signals a response via a separate response link running directly to a global collector, which collects all responses and broadcasts a single system-wide response back to the devices.

Abstract: A chipset with LPC interface and data accessing time adapting function is proposed. The chipset comprises an LPC slave controller connected to an LPC master controller in a main controller, a LPC/ISA bridge connected to the LPC slave controller and convert a data in LPC specification to a data in ISA specification, a plurality of ISA logic control units connected to the LPC/ISA bridge and controlling corresponding ISA devices, and a data accessing time adjuster connected to the LPC/ISA bridge and adjusting the time of accessing operation for an ISA or LPC device.

Abstract: A system for oversubscribing a pool of modems comprises at least one digital signal processor and a switch. The digital signal processor is configured as a variable number of high speed data modems and a variable number of low bandwidth synchronization modems. A communication bus is connected to the digital signal processor for configuring the processor, connecting the system to external devices, and communicating status information with external devices. The high speed data modems and low bandwidth synchronization modems are connected, via the switch, to customer premise equipment devices. Active data and synchronization data is transferred between the high speed data modems, the low bandwidth synchronization modems, and respective customer premise equipment devices. The synchronization modems consume significantly less power than the high speed data modems.

Abstract: A point-of-sale system is disclosed which is freely configurable with a plurality of peripheral input devices. The system includes a general purpose computer having a communications port for receiving and/or transmitting data. An electronic interface is coupled to the communications port and readily connectable to the plurality of peripheral input devices for communicating data between the plurality of input devices and the computer. The plurality of peripheral input devices can be selectively connected and disconnected from the electronic interface, the electronic interface maintaining a continuous dialogue with the computer during the connection and disconnection of the input devices.

Abstract: The present invention provides a virtual network, sitting “above” the physical connectivity and thereby providing the administrative controls necessary to link various communication devices via an Access-Method-Independent Exchange. In this sense, the Access-Method-Independent Exchange can be viewed as providing the logical connectivity required. In accordance with the present invention, connectivity is provided by a series of communication primitives designed to work with each of the specific communication devices in use. As new communication devices are developed, primitives can be added to the Access-Method-Independent Exchange to support these new devices without changing the application source code. A Thread Communication Service is provided, along with a Binding Service to link Communication Points. A Thread Directory Service is available, as well as a Broker Service and a Thread Communication Switching Service. Intraprocess, as well as Interprocess, services are available.

Abstract: A non-uniform memory access (NUMA) computer system includes at least a local processing node and a remote processing node, with a node controller, that are coupled to a node interconnect. In response to receipt by the node controller of a request transaction transmitted from the local processing node, via the node interconnect, the node controller at the remote processing node issues the request transaction on the local interconnect. If the request transaction receives a retry response at the remote processing node, the node controller reissues the request transaction on the local interconnect at least once, thus giving the request transaction another opportunity to complete successfully.

Abstract: A communication method for use with a decentralized bus system B, to which a plurality of communication participants are connected, including a first master M1, which is assigned to a first master system MS1, and a second master M2 and a slave S3, which are assigned to a second master system MS2 that is associated with at least one application and provided with a filter table FT containing data entries. A message M having a header (provided with data entries corresponding to the filter table data entries) and message data is formed and transmitted from the first master M1 over the bus B. The message M is detected, and at least some header data are evaluated in the second master system MS2, including being compared to the filter table data entries. The message data D are made available to the application when the header and filter table data entries coincide.

Abstract: A bridge device (4) for connecting a plurality of communication networks (1-3) around which data is transmitted in frames which include control information defining at least the identity of a destination for data in the frame, each network having at least one end station (8-12). The bridge device comprises a corresponding plurality of data coupling units (13,14) for connection to respective ones of the networks (1-3), each data coupling unit including receive (13) and transmit (14) interfaces for respectively receiving data from and transmitting data onto the connected network. A common store (17) is connected to all the data coupling units for receiving data being transmitted from one network to another.

Abstract: In a first embodiment, multi-speed concatenated packet strings are transmitted by a first node on a serial bus. To accommodate multi-speed packets, a speed signal is transmitted immediately prior to the packet. In a second embodiment, ACK-concatenation is used to allow a node to transmit a data packet immediately after transmitting an acknowledge signal on the bus. The data packet need not be related to the ACK packet. In a third embodiment, a node which receives a first data packet followed by a data end signal on a child port, concatenates a second data packet onto the first data packet during retransmission. The second data packet is also transmitted down the bus in the direction of the node which originally transmitted the first data packet.

Abstract: A picture signal processing apparatus and method is presented that determines whether there is an odd or even-number field signal in the picture signals received, by referring to flags that are turned on or off in accordance with the result of odd and even-number field detection. If the odd and even-number field flags are on, an image processing operation A is performed. If the odd-number field flag is on and the even-number field is off, an image processing operation B is performed. If the odd-number field flag is off and the even-number field is on, an image processing operation C is performed. In accordance with whether there is an odd or even-number field signal in the received picture signals, an appropriate image processing operation is selected from the different operations. That is, the received picture signals are processed in a mode suitable to the signals, so as to generate suitable image data.

Abstract: The invention relates to the field of programming, of the execution of test sequences, of diagnosis and of the maintenance of medical appliances which, due to their computer architecture, comprise two communications buses. One such computer architecture is generally provided when a medical appliance, due to safety requirements, comprises an auxiliary computer system in addition to its action computer system. Said auxiliary computer system independently monitors the functional mode of the action computer system and can induce a reliable state of the appliance in an emergency. The aim of the invention is to be able to easily, quickly and reliably implement a programming, the execution of test sequences, the diagnosis and the maintenance of such an appliance. To these ends, the invention provides that a connection line, which can be interrupted by a switch, is arranged between the communications buses, and both communications buses can be connected to form a unified communications bus via said connection line.

Abstract: In a first embodiment, multi-speed concatenated packet strings are transmitted by a first node on a serial bus. To accommodate multi-speed packets, a speed signal is transmitted immediately prior to the packet. In a second embodiment, ACK-concatenation is used to allow a node to transmit a data packet immediately after transmitting an acknowledge signal on the bus. The data packet need not be related to the ACK packet. In a third embodiment, a node which receives a first data packet followed by a data end signal on a child port, concatenates a second data packet onto the first data packet during retransmission. The second data packet is also transmitted down the bus in the direction of the node which originally transmitted the first data packet.

Abstract: A communication system for a house, a flat or an office in a house or for separated blocks of buildings, so as to connect at least three terminal units within said house, flat, office or separated blocks of buildings, is based on a central data bus for transmitting data to be transmitted between the terminal units, wherein the data bus has no specific deterministic access control and a limited transmission capacity. A first intelligent network terminating device is provided in the first terminal unit and includes interfaces for communication devices which may be located in the first terminal unit. A second intelligent network terminating device is located in the second terminal unit and includes interfaces for communication devices which can be located in the second terminal unit.

Abstract: A communications apparatus comprising a plurality of communication devices each having a plurality of ports and a data bus interconnecting the plurality of units, wherein each device is provided with means enabling the device to detect automatically its position on the data bus.

Abstract: A communications core implemented on a single programmable device. In one embodiment, the communications core may include a subsystem interconnect operable to connect the programmable device to computer; a message processor coupled to the subsystem interconnect, the message processor having an instruction set architecture that includes a data path configured to reduce hardware requirements and increase memory management capabilities; and a codec coupled to the message processor. The programmable device may also include an instruction data buffer coupled to the message processor; and a signal conditioner coupled to the codec.

Abstract: In connection with a method for the data exchange between an operating and monitoring program BA and a field device (10, 20, 30), which is connected via a field bus adapter (5) with the internet, the operating and monitoring program BA accesses a serial interface (8), which is connected with an internet interface (13). By means of this a data exchange between the operating and monitoring program BA via the internet is possible without extensive program changes.

Abstract: The communication system conducts communication among nodes N1 to N4 that form a communication network of bus type by using set communication parameters. The communication system includes one master node N1 selected from among the nodes N1 to N4; and one or more slave nodes N2 to N4 that are nodes N2 to N4 other than the master node N1, the one or more slave nodes logically star-connected to the master node N1, each of the one or more slave nodes conducting communication with another node N2 to N4 via the master node N1 by using communication parameters negotiated with the master node N1.

Abstract: On the preferred embodiment, the basic system comprises a communication serial bus 8, which interconnects one or several remote smart micro-units 14, minimal in size and cost, with a master controller unit 2. The remote unit 14 controls and monitors the operation of one or several sensors, actuators or peripherals 12. The resulting network system provides reliability, and easy and low-cost deployment. The network utilizes the Inter-Integrated Circuit communication (IIC) protocol, with one or more masters 2 on one end of an external bus 8, and one or more slave remote units 14 distributed along the bus 8. The peripherals 12 are powered, controlled and connected to the network via the remote unit 14 attached to them. The remote units are configured and operated via the network, receiving commands issued by the master 2.

Abstract: The present method describes a format for the generation and processing of commands interpreted by network controller modules of peripheral devices in electrical systems. These commands create the possibility of device intercommunication through a network; offer reliability in the modification of remote module configuration; and offer capability of working with internal parameters of remote modules. The versatility of their structuring allows easy creation of new commands according to the requirements of the system.

Abstract: WN nodes (2 to 5) set the number of clocks in low-order 12 bits of cycle time data from cycle masters (20-50) to a bus counter (102A) and an internal counter (102B). When a control block is transmitted to the WN nodes (3 to 5), the WN node (2) stores a counted value of the counter (102B) in a cycle sync area. The WN nodes (3 to 5) which receive the control block extract the counted value from the cycle sync area, generate control information for correcting a difference so as to maintain an initial value by comparing the extracted counted value and the counted value of the above-mentioned counter (102A), and transmits such control information to the cycle masters (30 to 50). Thus, the number of clocks in the low-order 12 bits of the cycle time data in the cycle masters (30 to 50) is corrected, and a time synchronization among respective buses is established. Therefore, a time synchronization among a plurality of buses may be established satisfactorily.

Abstract: A programmable controller system includes at least one programmable controller and one or more other devices with which it can exchange data through a network or a bus. The programmable controller stores one or more program blocks and executes them selectively and individually by switching them between active and stopped conditions. At least one of the other devices is adapted to issue a command to have a specified operation carried out on a specified one of the program blocks. Upon receiving this command, the programmable controller carries out the specified operation on the specified programmable block and returns the result of the operation back to the device which issued the command. Such other devices may be themselves a programmable controller, a support tool or a host computer. The command may be to add or delete a specified problem block.

Abstract: An inter-processor communications interface is disclosed. The interface permits the transparent movement of data from one processor to another via a memory fabric which is connected with both processors. This permits the incoming data of a first processor to be utilized by a second processor thereby freeing that processor from having to handle incoming data. Further, the second processor can handle outgoing data exclusively, freeing the first processor from having to handle outgoing data. In this way, each direction of a bi-directional dataflow may be handled by the maximum capability of a bi-directional capable processing device.

Abstract: A control messaging structure for a multi-zone entertainment and communications network and control method therefor. The network is a digital peer-to-peer network distributing data that is being streamed from multiple independent entertainment and communications media sources to multiple independent receivers and/or transceivers. The receivers and transceivers may be located in different zones from each other. The zones may be individual rooms of a building or house. The control messaging structure is a peer-to-peer communication protocol structure. Feature cards or remote devices are connected to peer nodes, which are controlled by control data passed between the nodes on the network over a control bus using the control messaging structure. Likewise, information is shared over the control bus between devices connected to network nodes using the control messaging structure of the present invention.

Abstract: A packet processing system may include a processor, a cache, a memory controller, and at least one packet interface circuit integrated into a single integrated circuit. In one embodiment (which may be used in integrated or non-integrated systems), the packet interface circuit is configured to cause allocation in the cache of a portion of a received packet. In one embodiment (which may be used in integrated or non-integrated systems), the memory controller may be configured to selectively block memory transactions. Particularly, the memory controller may implement at least two block signals, one for the packet interface circuit and one for other devices. The block signals may be used to control the initiation of memory transactions when the memory controller's input queue is approaching fullness.

Abstract: A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.

Abstract: An apparatus is described to implement a module redundant system using logical addresses. The apparatus may comprise a bus on which a plurality of server modules may be coupled to. One of the server modules may be configured to be active and remaining server modules may be configured to be on standby. A plurality of client modules may be coupled to the bus and configured to be in communication with the active server module using logical addresses.

Abstract: The invention relates to a bus system for transmitting data between a processing unit (10) and a memory unit (19) comprising memory cells (17), in which a plurality of logic addresses is available for each memory cell (17). Dependent on the kind of address used, the data transmitted through the data bus (13) are differently manipulated by a data modification unit (16) so that, for protection against abuse of data, the unchanged identical data are not present at the data bus (13).

Abstract: A data transfer circuit and a data transfer method are provided that can minimize the time required for transferring identical data to a plurality of data registers. A data transfer circuit for writing parallel data transferred through a data bus into a plurality of data registers is provided with auxiliary registers which respectively correspond to the data registers, a write timing determining section, and an auxiliary register setting section. At a first timing, the auxiliary register setting section makes the auxiliary registers store the respective bit values of parallel data transferred through the data bus. At a second timing, after the first timing, the write timing determining section makes the data registers store another parallel data transferred through the data bus in accordance with the respective bit values stored in the auxiliary registers.

Abstract: A remote data acquisition and transmission system and method are disclosed. A plurality of application controllers are interfaced with remote equipment from which operation data is acquired by the application controllers. The application controllers communicate with an application host via a local area network, and the application host can communicate with a network operations center using a wide area network interface. In one embodiment, each application controller interfaces with remote equipment that comprises a vending machine.

Abstract: Apparatuses are connected in a tree structure, wherein the branches correspond to bus connections between apparatuses. The apparatus at the root node the tree ultimately arbitrates access to the bus connections. The tree structure is dynamically reorganized by selecting a new root node. Selection of the new root node involves predicting a volume of messages to be sent by each of the apparatuses (preferably by counting the number of messages originating from each apparatus during an observation period). An expected heavy sender apparatus is selected as new root node. Thus, the heavy sender is able to get faster access to arbitration and network resources, reducing jitter in the time points at which messages can be sent by the heavy sender.