System Configuring Patents (Class 710/104)
  • Patent number: 10558604
    Abstract: An integrated circuit includes a processor to monitor a communication interface arbitration sequence on a system bus, determine, based on the monitored arbitration sequence, a master or slave identifier that is sending a transaction on the system bus, and process the transaction based on the determined master or slave identifier that is sending the transaction.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: February 11, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Christopher Kong Yee Chun, Chris Rosolowski
  • Patent number: 10545769
    Abstract: A method performed by an information handling system, the method including bifurcating, by a processor of the information handling system, an I/O unit (IO unit) of the information handling system into a first root port and a second root port, wherein the first root port comprises a first pre-determined number of first lanes of the IO unit and the second root port comprises the first pre-determined number of second lanes of the IO unit. The method further including discovering, by the processor, a first I/O device (IO device) coupled to the IO unit, wherein the first IO device utilizes a first lane width that is greater than the first pre-determined number of lanes, and in response to discovering the first IO device, bifurcating, by the processor, the IO unit into a third root port, wherein the third root port comprises the first lanes and the second lanes.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: January 28, 2020
    Assignee: Dell Products, LP
    Inventors: Michael W. Arms, Anand P. Joshi, Justin L. Frodsham
  • Patent number: 10539989
    Abstract: A memory device can include: a non-volatile storage register configured to store an active reset polling enable bit that corresponds to a reset operation; a controller configured to control execution of the reset operation on the memory device; an operation completion indicator configured to provide a reset recovery indication external to the memory device when the reset operation has completed and the active reset polling enable bit is set; and a command decoder configured to receive a command to be executed on the memory device in response to the reset recovery indication.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: January 21, 2020
    Assignee: Adesto Technologies Corporation
    Inventors: Bard M. Pedersen, Paul Hill
  • Patent number: 10528357
    Abstract: A method and system for identifying a data recorder based upon a unique signature generated for the data recorder. Configuration information is received, the information specifying a plurality of data recording input parameters which are selected to facilitate use of the data recorder in a particular data recording application. A unique signature is generated according for the data recorder, the unique signature including a code which uniquely identifies the data recorder based on a transformation of the configuration information. The unique signature is stored for subsequent access or reference. To differentiate between similar makes and models of data recorders, at least a portion of the unique signature includes a unique core part number that is assigned to only one data recorder by, for example, the manufacturer of the data recorder.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: January 7, 2020
    Assignee: L3 TECHNOLOGIES, INC.
    Inventors: Daniel J. Cunningham, Todd R. White
  • Patent number: 10528492
    Abstract: A circuit for USB interface sharing includes a host device module, a slave device module, a switch module and a Universal Serial Bus (USB) interface. A detection end of the host device module is connected to a signal detection end of the USB interface. A first control output end of the host device module is connected to a first control input end of the switch module. A data end of the host device module is connected to a first data end of the switch module. A data end of the slave device module is connected to a second data end of the switch module. A third data end of the switch module is connected to a data end of the USB interface.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: January 7, 2020
    Assignee: XI'AN ZHONGXING NEW SOFTWARE CO., LTD.
    Inventors: Tengyuan Qiu, Guodong Song
  • Patent number: 10521255
    Abstract: The method includes identifying, by one or more computer processors, a program being utilized by a user. The method further includes identifying, by one or more computer processors, an environmental factor related to a user of the program. The method further includes determining, by one or more computer processes, a relationship between the program and the environmental factor. The method further includes generating, by one or more computer processors, one or more instructions for the program based at least in part on the determined relationship and the environmental factor.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: December 31, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jeremy R. Fox, Andrew R. Jones, Balasubramanian Sivasubramanian
  • Patent number: 10509758
    Abstract: Provided are systems and methods for hot-plugging emulated peripheral devices (e.g., endpoints) into host devices that either have a hypervisor that does not support virtualized peripheral device or that do not include a hypervisor. In various implementations, a configurable peripheral device can emulate a switch that includes upstream ports and downstream ports. When a new endpoint device is requested, the configurable peripheral device can, using an emulation configuration for the new endpoint device, generate an emulation for the new endpoint device. The configurable peripheral device can connect the endpoint device to a downstream port, and then trigger a hot-plug mechanism, through which the host device can add the new endpoint device to the known hardware of the host device.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: December 17, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Adi Habusha, Georgy Zorik Machulsky, Nafea Bshara, Tal Zilcer
  • Patent number: 10496625
    Abstract: An ordering system includes a plurality of ticket order release bitmap blocks that together store a ticket order release bitmap, a bus and a Global Reordering Block (GRO). Each Ticket Order Release Bitmap Block (TORBB) stores a different part of the ticket order release bitmap. A first TORBB of the plurality of TORBBs is protected. The GRO 1) receives a queue entry onto the ordering system from a thread, 2) receives a ticket release command from the thread, and in response 3) outputs a return data of ticket release command. The queue entry includes a first sequence number. The return data of ticket release command indicates if a bit in the protected TORBB was set. An error code is included in the return data of ticket release command if a bit is set within the protected TORBB. When a bit in the TORBB is set the thread stops processing packets.
    Type: Grant
    Filed: November 19, 2016
    Date of Patent: December 3, 2019
    Assignee: Netronome Systems, Inc.
    Inventor: Christopher A. Telfer
  • Patent number: 10482253
    Abstract: In some examples, a computing device may receive (i) settings associated with one or more features of a basic input output system (BIOS) of the computing device and (ii) a device identifier that uniquely identifies the computing device. The computing device may determine a policy identifier that identifies a policy being implemented by the settings associated with the one or more features of the BIOS. The computing device may retrieve a public key associated with an organization that acquired the computing device and sending a request to a service to validate the policy. The request may include the policy identifier and the public key. After the computing device receives a response from the service indicating that the policy is valid, the computing device may initiate a reboot and modify, during the reboot, the one or more features of the BIOS of the computing device based on the settings.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: November 19, 2019
    Assignee: Dell Products L. P.
    Inventors: Charles D. Robison, Ricardo L. Martinez, Joseph Kozlowski, Daniel L. Hamlin
  • Patent number: 10485036
    Abstract: A disclosed wireless tunneling system determines a suitable configuration of a wireless tunneling apparatus for tunneling communications between two processing apparatuses through a wireless link. Responsive to determining the configuration of the wireless tunneling apparatus, the wireless tunneling system establishes a communication with another wireless tunneling apparatus through the wireless link, while maintaining compliance of the communications between the two processing apparatuses with a wired communication protocol. Moreover, the wireless tunneling apparatus can supply power to or source power from a processing apparatus coupled to the wireless tunneling apparatus through a wired cable.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: November 19, 2019
    Assignee: Ubistar Technology, Inc.
    Inventors: Brian Henry John, Nishit Kumar, Ron Zeng
  • Patent number: 10474607
    Abstract: A source device includes an adaptive link training circuity. The link training circuitry includes source capability information for link training of a link between the source device and a sink device. The source device includes a transmitter coupled to the adaptive link training circuitry to transmit the source capability information to the sink device. The adaptive link training circuitry is to initiate link training between the source device and the sink device, determine whether the link training between the source device and the sink device is unsuccessful, and in response to determining that the link training is unsuccessful, automatically adapt a setting of the link training based on the source capability information.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: November 12, 2019
    Assignee: Intel Corporation
    Inventors: Sriram Venkatesan, Sanjib Sarkar
  • Patent number: 10474606
    Abstract: Various examples described herein provide for a management controller that includes a virtual universal serial bus (USB) host controller that can emulate an actual USB host controller to a central processor. A particular endpoint from a number of endpoints is associated with a virtual USB device that is coupled to the virtual USB host controller. The particular endpoint is to refer to a location in a management memory.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: November 12, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Theodore F. Emerson, David F. Heinrich, Richard Wei Chieh Yu, Robert L. Noonan, Christopher J. Frantz, Sze Hau Loh
  • Patent number: 10474612
    Abstract: A lane reversal detection and bifurcation system includes an interface that includes a plurality of lanes that are coupled to an endpoint interface of an endpoint device and a BIOS that bifurcates the interface into a first root port and a second root port, such that the first root port is coupled to a first subset of the plurality of lanes, and the second root port is coupled to a second subset of the plurality of lanes. The BIOS initializes the endpoint device to establish a link between the endpoint device and the interface. The BIOS detects an endpoint presence and a non-functional link at the first root port and an endpoint presence and a functional link at the second root port and, in response, determines that the first subset of the plurality of lanes coupled to the endpoint device are subject to a lane reversal.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: November 12, 2019
    Assignee: Dell Products L.P.
    Inventors: Alberto David Perez Guevara, Wei G. Liu
  • Patent number: 10446222
    Abstract: A memory subsystem empirically tests performance parameters of I/O with a memory device. Based on the empirical testing, the memory subsystem can set the performance parameters specific to the system in which the memory subsystem is included. A test system performs the testing. For each of multiple different settings for multiple different I/O circuit parameters, the test system sets a value for each I/O circuit parameter, generates test traffic to stress test the memory device with the parameter value(s), and measures an operating margin for the I/O performance characteristic. The test system further executes a search function to determine values for each I/O circuit parameter at which the operating margin meets a minimum threshold and performance of at least one of the I/O circuit parameters is increased. The memory subsystem sets runtime values for the I/O circuit parameters based on the search function.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventors: Theodore Z. Schoenborn, Christopher P. Mozak
  • Patent number: 10445279
    Abstract: A computer system includes a system bus having multiple lanes, one or more peripheral devices, and a bus controller. The peripheral devices are coupled to the system bus. The bus controller is configured to receive, from one or more of the peripheral devices, respective indications of numbers of the lanes requested by the peripheral devices, and to configure the system bus in response to the indications.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: October 15, 2019
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Yuval Itkin, Assad Khamaisee
  • Patent number: 10437762
    Abstract: Systems and methods for providing a partitioned interconnect slot for inter-processor operation. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include: a processor comprising a first core and a second core; and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to enable an Input/Output (I/O) device to communicate directly with the first core and the second core utilizing a single interconnect slot.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: October 8, 2019
    Assignee: Dell Products, L.P.
    Inventors: John Christopher Beckett, Rich M. Hernandez, Robert Wayne Hormuth, Mukund P. Khatri, Yogesh Varma
  • Patent number: 10436838
    Abstract: The present disclosure is directed to systems and methods for autonomously generating test methods for testing features included on semiconductor platforms. The systems and methods described herein either manually or autonomously receive information and/or data indicative of the features included in, on, or about a semiconductor platform to be tested. Based on the presence of features and/or feature combinations on the semiconductor platform, the systems and methods described herein autonomously select the appropriate test blocks used to generate the test method. The systems and methods described herein generate additional test methods as permutations of the selected test blocks. The validity of each test method is confirmed using dependency rules and all valid test methods are combined to form a test package that is used to test the semiconductor platform.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventors: Sneha S. Pingle, Soumya P. Mukherjee, Chandrashekhar Mutuguppe Venkataramana, Divya Appaji Lalithamba
  • Patent number: 10409737
    Abstract: Provided are apparatus, system, and method for positionally aware device management bus address assignment. A presence of a plurality of storage devices is detected on a bus. One of the storage devices detected on the bus is selected. A get identifier command is sent on the bus to all of the storage devices that is only responded to by the selected storage device. A unique identifier is received from the selected storage device over the bus. An address for the selected storage device is assigned and an entry is added to the address mapping to indicate the unique identifier, the assigned address, and a physical location indicator for the selected storage device.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: September 10, 2019
    Assignee: INTEL CORPORATION
    Inventors: Myron D. Loewen, Andrew W. Morning-Smith, Anthony M. Constantine
  • Patent number: 10409242
    Abstract: An electronic operator interface based controller and device automatic downloads are provided. An electronic operator interface can determine if control logic or content used by an industrial controller has been updated, changed, or otherwise modified. If the content has been modified, then the electronic operator interface can automatically obtain the content and store a back-up copy in memory. Additionally or alternatively, the electronic operator interface can periodically update a backup copy of the content. Furthermore, the electronic operator interface can determine if the controller has lost its content, and restore the content from the most recent version saved in memory.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: September 10, 2019
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Ronald E. Bliss, Brian R. Oulton
  • Patent number: 10402358
    Abstract: A system and approach for addressing modules on a platform bus that may incorporate a master module and one or more slave modules. The platform bus may run through sub-base connectors that interlock modules together on a rail. Addressing of the modules may occur automatically and dynamically in that the master module may have a first address by default, and a first slave module adjoining the master module may be assigned a second address. A second slave module adjoining the first slave module, if there is one, may be assigned a third address. Each of the other slave modules, adjoining a preceding slave module assigned an address, may be assigned a next address after an address assigned to a preceding slave module. Addresses may be assigned in a numerical order to each module based on a physical position of the respective module on a rail.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: September 3, 2019
    Assignee: Honeywell International Inc.
    Inventors: Ronald Sorenson, Paul Patton, Rick Solosky, Rolf L. Strand, John Evers, Patrick Springman, Yury Millman
  • Patent number: 10394291
    Abstract: An interface adapter may include a printed circuit board that includes an edge connector dimensioned to be inserted into an expansion socket of a computing device. The interface adapter may also include a plurality of modular computing components removably mounted to a top surface of the printed circuit board, where each modular computing component includes a connector dimensioned to be inserted into a socket of the printed circuit board and the connector of each modular computing component includes a pinout that is more compact than a pinout of the edge connector of the printed circuit board. In addition, the interface adapter may include one or more modular heatsinks coupled to a top surface of each modular computing component to facilitate heat dissipation from the top surface of the modular computing component. Various other apparatuses, systems, and methods are also disclosed.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: August 27, 2019
    Assignee: Facebook, Inc.
    Inventors: Chuankeat Kho, John Edward Fernandes, Yueming Li
  • Patent number: 10394747
    Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores. Also disclosed are techniques for implementing hierarchical serial interconnects such as a PCI Express switch topology over a coherent mesh interconnect.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: August 27, 2019
    Assignee: Mellanox Technologies Ltd.
    Inventors: Peter Paneah, Carl G. Ramey, Gil Moran, Adi Menachem, Christopher J. Jackson, Ilan Pardo, Ariel Shahar, Tzuriel Katoa
  • Patent number: 10387178
    Abstract: A guest operating system of a virtual machine sends a request to a hypervisor to coalesce interrupts from a networking device. The guest operating system then monitors the execution state of an application on the virtual machine to detect when the application becomes idle. Upon detecting that the application is idle, the guest operating system can send a request to the hypervisor for any coalesced interrupts that have been queued for delivery to the application. The guest operating system may then receive the coalesced interrupts from the hypervisor and deliver them to the application.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: August 20, 2019
    Assignee: Red Hat Israel, Ltd.
    Inventor: Michael S. Tsirkin
  • Patent number: 10379839
    Abstract: A process for communicating utility-related data over at least one network is described. the process includes: collecting utility-related data at a hub device during a first predetermined period of time; securing the utility-related data at the hub device using digital envelopes during the first predetermined period of time; initiating by the hub device an autonomous wake up process during a second predetermined period of time; sending the secure utility-related data over a first network to a designated server via at least one User Datagram protocol (“UDP”) message during the second predetermined period of time; and receiving an acknowledgement of receipt message of the at least one UDP message from the designated server; wherein the first and second predetermined periods of time typically do not overlap, but may overlap.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: August 13, 2019
    Assignee: Trilliant Networks, Inc.
    Inventors: Frederick Enns, Michel Veillette, Randall Wayne Frei
  • Patent number: 10379160
    Abstract: An apparatus 2 for performing serial data communication with a target device 4, such as an integrated circuit, utilizes serial transfer circuitry 16 to perform a serial transfer of data to a communication register 26 in the target device 4 and serial retrieval circuitry 18 to retrieve an acknowledge signal 32 indicating whether or not the target device is ready to perform further processing following such a transfer. Delay control circuitry 20 serves to apply a predetermined delay period following the transfer of the serial data via the serial transfer circuitry before initiating the retrieval of the acknowledge signal. This predetermined delay period is controlled in dependence upon the ready status indicated by the acknowledge signals retrieved such that the proportion of acknowledge signals retrieved which indicate an unready status meets a predetermined condition, such as being less than a non-zero predetermined value.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: August 13, 2019
    Assignee: ARM Limited
    Inventors: Russell John Buckett, Ian Craig McFarland, Robert John Walker
  • Patent number: 10346583
    Abstract: Methods, systems, and computer-readable and executable instructions are described herein. One method includes identifying a number of structural rules of an area utilizing a map of the area, determining a placement for each node of a number of nodes of a node network on the map of the area utilizing a node placement model, identifying a placement of a node among the number of nodes that deviates from a structural rule among the number of the structural rules, and providing an indication of the node on the map of the area.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: July 9, 2019
    Assignee: Honeywell International Inc.
    Inventor: Arunkumar Kamalakannan
  • Patent number: 10333865
    Abstract: An example method for transformation of Peripheral Component Interconnect Express (PCIe) compliant virtual devices in a server in a network environment is provided and includes receiving, during runtime of the server, a request to change a first configuration of a PCIe compliant virtual device to a different second configuration, identifying a bridge on a PCIe topology below which the virtual device is located, issuing a simulated secondary bus reset to the bridge, the virtual device being reconfigured according to the change in configuration after the simulated secondary bus reset is issued, re-enumerating below the bridge after the change in configuration completes without rebooting the server, and updating the PCI topology with the virtual device in the second configuration. A virtual interface card adapter traps the simulated secondary bus reset, removes the virtual device from the PCI topology, and reconfigures the virtual device from the first configuration to the second configuration.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: June 25, 2019
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Sagar Borikar, Prabhath Sajeepa
  • Patent number: 10333778
    Abstract: Disclosed are various embodiments for staging client devices that allow for multiple user access. A computing device retrieves a current version of the list of user profiles associated with the client device. The computing device determines that the current list of user profiles differs from a previous version of the list of user profiles associated with the client device. The computing device identifies a list of policies to be sent to a management component executing on the client device based at least in part on a determination that the current list of user profiles differs from the previous version, wherein the list of policies comprises at least one policy that is associated with at least one user profile included in the current list of user profiles that is absent from the previous version of the list of user profiles. The computing device then sends the list of policies to the management component executing on the client device.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: June 25, 2019
    Assignee: AirWatch, LLC
    Inventor: Adam Hardy
  • Patent number: 10290151
    Abstract: Methods, apparatuses and computer-readable media for virtualizing a physical device using an augmented reality (AR) or virtual reality (VR) virtualized or partially virtualized device (an AR/VR device) are provided. In particular, first data of a user interaction with the physical device is received by the AR/VR device from the physical device. The first data of the user interaction with the physical device is converted into second data for representation of the user interaction with the physical device in a virtual representation of the physical device. The virtual representation of the physical device and the representation of the user interaction with the physical device are outputted by the AR/VR device.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: May 14, 2019
    Assignee: BlackBerry Limited
    Inventor: Phillip Riscombe-Burton
  • Patent number: 10275389
    Abstract: A module comprising a USB Type-C receptacle, a USB Type-C plug and a logic unit is disclosed. A power pin of the receptacle is connected with another power pin of the plug via a switch. A CC pin of the receptacle is connected to ground through a pull-down resistance. Another CC pin of the plug is connected to the logic unit through a pull-up resistance. The module connects with a power source device being a power sink-role in order to receive a source capability of the power source device, then turns on the switch and transforms itself to a power source-role. The module connects to a DRP device afterward being the power source-role to act for the power source device and perform a USB PD communication with the DRP device.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: April 30, 2019
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Tien-He Chen, Che-Min Chen
  • Patent number: 10241955
    Abstract: A device is provided that has a bus including a first line and a second line. A first set of devices are coupled to the bus and, in a first mode of operation, configured to use the first line for data transmissions and use the second line for a first clock signal. One or more additional lines are connected between two or more of the devices in the first set of devices for transmitting signaling between the two or more devices. A second set of devices are configured to use the bus and at least one of the additional lines for data transmissions in a second mode of operation, where in the second mode of operation symbols are encoded across the first line, the second line, and the at least one of the additional lines.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: March 26, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Radu Pitigoi-Aron, Richard Dominic Wietfeldt
  • Patent number: 10236649
    Abstract: There is provided an adapter for adapting an electronic device to a modular electronic device system. The adapter generally has a housing having two lateral edges, a cavity between the lateral edges and being adapted to receive the electronic device, each of the two lateral edges of the housing having at least one magnetic coupler electrically connectable with at least one magnetic coupler of the modular electronic device system by magnetically engaging the at least one magnetic coupler of the adapter with the at least one magnetic coupler of the modular electronic device system, and an internal electric conductor network electrically connected to the magnetic couplers of the adapter and electrically connected to an internal connector which is electrically connectable to the electronic device when received in the cavity of the housing.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: March 19, 2019
    Assignee: NANOPORT TECHNOLOGY INC.
    Inventor: Timothy Jing Yin Szeto
  • Patent number: 10228961
    Abstract: Implementations of the disclosure provide for live storage domain decommissioning in a virtual environment. A method of the disclosure includes identifying, by a processing device, a storage domain to decommission from a storage system. The storage domain comprises a plurality of disk images. It is determined whether the disk images are associated with a virtual machine. Thereupon, the disk images are hot-unplugged from the virtual machine. Responsive to detecting that the disk images are unplugged from the virtual machine, the disk image is deleted from the storage domain and the storage domain is removed from the storage system.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: March 12, 2019
    Assignee: Red Hat Israel, Ltd.
    Inventors: Maor Lipchuk, Daniel Erez
  • Patent number: 10216685
    Abstract: A memory module is organized into slice sections, each configured to input and output a slice of data for a different section of a data bus. Each slice section includes at least one nonvolatile memory (NVM) and a memory element, such as random access volatile memory, to store the slice of data for the slice section during operations that transfer the slice of data between the section of the data bus for the slice section and the NVM of the slice section. Each slice section also includes a slice controller configured to translate an address for the slice of data for the section of the data bus into a physical address of the NVM of the slice section.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: February 26, 2019
    Assignee: AgigA Tech Inc.
    Inventors: Ronald H Sartore, Thomas O. Koger
  • Patent number: 10209920
    Abstract: A method for generating machine code for driving an execution unit is introduced to incorporate with at least the following steps: Data access instructions of a kernel, which are associated with the same memory surface, are collected. An address pattern associated with the data access instructions is analyzed to generate a global-id address. Machine code containing the global-id address is generated.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: February 19, 2019
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventor: Tian Shen
  • Patent number: 10198257
    Abstract: A process for communicating utility-related data over at least one network is described, the process includes: collecting utility-related data at a hub device during a first predetermined period of time; securing the utility-related data at the hub device using digital envelopes during the first predetermined period of time; initiating by the hub device an autonomous wake up process during a second predetermined period of time; sending the secure utility-related data over a first network to a designated server via at least one User Datagram, protocol (“UDP”) message during the second predetermined period of time; and receiving an acknowledgement of receipt message of the at least one UDP message from the designated server; wherein the first and second predetermined periods of time typically do not overlap, but may overlap.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: February 5, 2019
    Assignee: Trilliant Networks, Inc.
    Inventors: Frederick Enns, Michel Veillette, Randall Wayne Frei
  • Patent number: 10162778
    Abstract: A universal serial bus stack may use an emulation layer to grant a non-universal serial bus device access to universal serial bus drivers and applications. The universal serial bus stack may exchange a device communication at an emulation layer. The universal serial bus stack may translate between a universal serial bus communication and the device communication at the emulation layer, and then may exchange the universal serial bus communication at a universal serial bus client interface.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: December 25, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Firdosh Bhesania, Andrea A. Keating, Vivek Gupta, Robbie Harris, Randall Aull
  • Patent number: 10122884
    Abstract: A cooperative image processing system including an image processing apparatus and a portable terminal apparatus capable of connecting to each other. The image processing apparatus includes a first processor to execute instructions to control the functions of a first screen data obtaining portion that obtains screen data for reproducing a first operation screen that allows operating the portable terminal apparatus, from the portable terminal apparatus. The image processing apparatus further includes a memory that stores a cooperation table that contains a list of operations that can be performed on the first operation screen and a plurality of next second operations to be displayed in a next second operation screen that allows operating the image processing apparatus, each of the next second operations corresponding to a respective one of the operations on the list of operations that can be performed on the first operation screen.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: November 6, 2018
    Assignee: Konica Minolta, Inc.
    Inventors: Kazusei Takahashi, Katsuhiko Akita, Takeshi Morikawa, Daisuke Nakano
  • Patent number: 10114428
    Abstract: An IT device includes a system board and a hybrid connector system including a standard connector portion and a supplemental connector portion. The standard connector portion is configured to receive a standardized expansion card and a combination of the standard connector portion and the supplemental connector portion is configured to receive a riser card.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: October 30, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Michael Gregoire, Robert P. Wierzbicki
  • Patent number: 10108567
    Abstract: An apparatus comprising a first circuit, a second circuit and a channel decoder. The first circuit may comprise (i) a controller port and (ii) a plurality of memory ports. The second circuit may comprise (i) input port and (ii) a plurality of output ports. The channel decoder may be configured to decode a selection signal. The channel decoder may be configured to select (i) one of the plurality of memory ports and (ii) one of the plurality of output ports in response to the decoded selection signal. The selection signal may be received by the controller port and the channel decoder in a first mode. The selection signal may be received by the input port and the channel decoder in a second mode.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: October 23, 2018
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventor: Yingnan Liu
  • Patent number: 10101875
    Abstract: An electronic apparatus comprising is provided. The electronic apparatus includes a keyboard to receive a user input to switch from a normal performance mode to a high performance mode, a processor to reassign a higher priority to a program, which has been active with a priority in the normal performance mode, such that the program is executed with the higher priority in the high performance mode that otherwise would have been executed with the priority previously assigned, and a display screen to display a mode indication visibly indicating at least one of the normal performance mode or the high performance mode.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: October 16, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-youl Kim, Min-sun Park, Keon-young Cho
  • Patent number: 10104706
    Abstract: A disclosed wireless tunneling system determines a suitable configuration of a wireless tunneling apparatus for tunneling communications between two processing apparatuses through a wireless link. Responsive to determining the configuration of the wireless tunneling apparatus, the wireless tunneling system establishes a communication with another wireless tunneling apparatus through the wireless link, while maintaining compliance of the communications between the two processing apparatuses with a wired communication protocol. Moreover, the wireless tunneling apparatus can supply power to or source power from a processing apparatus coupled to the wireless tunneling apparatus through a wired cable.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: October 16, 2018
    Assignee: Lattice Semiconductor Corporation
    Inventors: Brian Henry John, Nishit Kumar, Ron Zeng
  • Patent number: 10089117
    Abstract: An information handling system includes a management controller, which in turn includes a device access manager. The device access manager detects a new device within the information handling system, and performs a matching process between properties of the new device and matching criteria for a plurality of drivers in the information handling system. The device access manager also receives matching values from each of the plurality of drivers, and selects one of the drivers in response to the one driver having a highest matching value. The matching process for a driver is ended without a matching value being returned to the device access manager in response to a property of the new device not matching a corresponding matching criteria of the driver.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: October 2, 2018
    Assignee: Dell Products, LP
    Inventor: Andrew T. Miller
  • Patent number: 10089157
    Abstract: An Autonomous Concurrency Management (ACM) subsystem enables test instruments (operating as servers) to reliably and efficiently handle a variety of seamless multi-device-under-test (multi-DUT) scenarios and with minimal cooperation from the original equipment manufacturer (OEM) client software (e.g. test plans, hardware abstraction layer, etc.). Concurrency capability is built directly into the test instruments. Making the instrument based concurrency autonomous means the OEM software code base need not be specifically implemented for concurrency, potentially saving thousands of lines of OEM software code. To support basic concurrency scenarios where clients asynchronously share the instrument, as well as advanced concurrency scenarios such as a broadcast scenario, the ACM includes software lock, client separator, client rendezvous, and client observer functionality.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: October 2, 2018
    Assignee: NATIONAL INSTRUMENTS CORPORATION
    Inventor: Mark R. DeWitt
  • Patent number: 10078528
    Abstract: Novel tools and techniques might provide for implementing communications between two or more virtual machines (“VMs”) and client devices coupled to one or more ports. In some embodiments, an orchestration agent running on a host computing system might configure, using a VM-to-Port driver, a physical port of the host device to establish two or more virtual ports associated with the physical port, and might map, using the VM-to-Port driver, each of two or more VMs running on the host computing system with corresponding each of the two or more virtual ports. When a client device is communicatively coupled to the physical port, the orchestration agent might map, using the VM-to-Port driver, each of the two or more VMs with one or more functions of the client device via corresponding each of the two or more virtual ports associated with the physical port to which the client device is communicatively coupled.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: September 18, 2018
    Assignee: CenturyLink Intellectual Property LLC
    Inventor: Michael K. Bugenhagen
  • Patent number: 10073800
    Abstract: A coupling controller that performs coupling control of a device with a bus includes a decision circuit configured to decide whether a voltage level of a signal inputted from each of a plurality of signal lines included in the bus is lower than a given threshold value, and a switching controller configured to perform switching control for a switching unit, which is interposed between the bus and the device and switches coupling between each of the plurality of signal lines and the device, such that the signal line with regard to which it is decided by the decision circuit that the voltage level of the signal is lower than the given threshold value is coupled with the device.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: September 11, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Hiromiki Uekuri
  • Patent number: 10067898
    Abstract: In an example, a method for transmitting data includes determining, at a Universal Serial Bus (USB) host, a USB data transfer type of USB data being transmitted from the host device to a USB device, and determining a priority of the USB data based on the determined USB data transfer type. The example method also includes controlling transfer of the USB data from a protocol adaptation layer (PAL) of the USB host to a network layer of the USB host based on the determined priority.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: September 4, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Mu-Huan Chiang, Xiaodong Wang
  • Patent number: 10061707
    Abstract: A first device is determined as connected to a first one of a plurality of ports of a root complex. Addresses are assigned corresponding to a first hierarchy of devices including the first device. A second device is determined as connected through a mapping portal bridge at a second one of the ports of the root complex, the second device included in another second hierarchy of devices. A mapping table is generated that corresponds to the mapping portal bridge. The mapping table defines a translation between addressing used in a first view of a configuration address space of the system and addressing used in a second view of the configuration address space. The first view includes a view of the root complex and the second view includes a view corresponding to the second hierarchy of devices, the first hierarchy of devices being addressed according to the first view.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: August 28, 2018
    Assignee: Intel Corporation
    Inventors: Shanthanand Kutuva Rabindranath, David J. Harriman, Prashant Sethi, Vijayalakshmi Kothandan
  • Patent number: 10057209
    Abstract: Time-sequenced multi-device address assignment is provided. In this regard, an electronic device includes a plurality of client devices that are daisy-chained to a host interface port in a host controller by a reset line. The host controller is configured to assert the reset line to reset the daisy-chained client devices and then sequentially de-assert the reset line for the daisy-chained client devices according to a determined time sequence. Accordingly, the host controller assigns a unique client device address to each of the client devices when the reset line is de-asserted for the client device. By daisy-chaining the client devices via the reset line and sequentially assigning the unique client device addresses based on the determined time sequence, it is possible to assign the unique client device addresses from a single host interface port, thus reducing design complexity, footprint, and power consumption in the electronic device.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: August 21, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Lalan Jee Mishra, Radu Pitigoi-Aron, Richard Dominic Wietfeldt
  • Patent number: 10049075
    Abstract: Methods managing data communication between a peripheral device and host computer system are provided. A physical interface for communicating data between a peripheral device and the plurality of applications executing on the host computer system is opened and controlled by a software module. A first virtual interface and a second virtual interface of the software module are exposed to an operating system of the host computer system, and the operating system exposes the first virtual interface and the second virtual interface to the first application and the second application. The first virtual interface is used for communicating data between the peripheral device and the first application through the physical interface, and the second virtual interface is used for communicating data between the peripheral device and the second application through the physical interface.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: August 14, 2018
    Assignee: Honeywell International, Inc.
    Inventor: Aldo Caballero