Abstract: Reliability mechanisms for a connection can be selectively implemented based on the type of USB device that is redirected over a remote session. When a client attempts to redirect a device over a remote session, an agent on the server can be configured to detect the type of device that is being redirected. If the device is a mass storage device that implements the SCSI standard, and if a connectionless datagram protocol is employed to establish the connection, the agent can implement some reliability mechanisms such as reordering and windowing but not the recovery of lost packets. In contrast, if the device does not implement the SCSI standard, the agent can implement each reliability mechanism including the recovery of lost packets.

Abstract: A media switch device includes at least one media input port, a media input/extension composite port, a media output port, a media switch unit and a command switching and control module. The command switching and control module receives a response command from the media input/extension composite port to determine whether the media input/extension composite port is connected to a source device or to another media switch device. The command switching and control module receives a query command from the media output port to determine whether the media output port is connected to a sink device or to another media switch device. Related media switch system and method are also disclosed.

Abstract: An apparatus for addressing electronic circuits includes a host device comprising an address output, and a number of addressable electronic circuits, each comprising an address input, an address selection input and an address selection output, wherein the addressable electronic circuits are connected serially with each pair of the serially connected addressable electronic circuits connected by the address selection input and the address selection output.

Abstract: A device is provided that has a bus including a first line and a second line. A first set of devices are coupled to the bus and, in a first mode of operation, configured to use the first line for data transmissions and use the second line for a first clock signal. One or more additional lines are connected between two or more of the devices in the first set of devices for transmitting signaling between the two or more devices. A second set of devices are configured to use the bus and at least one of the additional lines for data transmissions in a second mode of operation, where in the second mode of operation symbols are encoded across the first line, the second line, and the at least one of the additional lines.

Abstract: The invention relates to a signal processing device, a signal processing method, an information processing program and a recording medium, which removes wide-range frequency noise. In a signal processing device (10), a cycle of acquiring a signal from a sensor is a data acquisition cycle, which is shorter than a cycle of forwarding time sequence data from which noise is removed to a controller, that is, a forwarding cycle.

Abstract: A receiver front end arrangement comprises a radio frequency signal input suitable to be connected to an antenna arrangement, a filter bank of non-overlapping band filters associated with respective band for the multi-band reception, a signal conditioning arrangement connected to the filter bank, and a low-noise amplifier arrangement connected to the signal conditioning arrangement. The low-noise amplifier arrangement comprises a path for each band of bands of the multi-band reception. For each path associated with a band for the multi-band reception the low-noise amplifier arrangement comprises a low-noise amplifier. The respective low-noise amplifier has band pass characteristics, or has a band filter connected where the band filter output has a direct connection to the input of the low-noise amplifier, corresponding to a band of the multi-band reception, respectively.

Abstract: An information handling system including a first memory to store data as a system memory for operations of a first processor in the information handling system, a second memory to store data as a cache memory for input/output operations of a second processor, and an interrupt handler. The interrupt handler is configured to monitor an input/output bus to determine whether a number of the input/output operations is above a first threshold level, if the number of the input/output operations is above the threshold level, to re-allocate a portion of the first memory from the first processor to the second processor, to monitor the utilization of the first memory to determine whether a utilization level is above a second threshold level, and if the utilization level is above the second threshold level, to re-allocate a portion of the second memory from the second processor to the first processor.

Abstract: Apparatuses and methods for asymmetric input/output interfaces for memory are disclosed. An example apparatus may include a receiver and a transmitter. The receiver may be configured to receive first data signals having a first voltage swing and having a first slew rate. The transmitter may be configured to provide second data signals having a second voltage swing and having a second slew rate, wherein the first and second voltage swings are different, and wherein the first and second slew rates are different.

Abstract: In one embodiment, a first computing device receives a communication from a second computing device. If the communication is a keep-alive ping from the second computing device for a network connection between the first computing device and the second computing device, then the first computing device sends a response to the ping to the second computing device using a secondary processor of the first computing device.

Abstract: An approach is provided for preventing access to mis=plugged devices by a service processor (SP). The SP retrieves an expected device identifier of a device associated with a hot-plug event. The hot-plug event was received in response to the device being connected to a selected port of a service processor, and the port is one many ports included in the SP. The SP sends a request for a device identifier via the port and actual device identifier is received from the device. The device is validated by comparing the expected device identifier with the actual device identifier. If the identifiers match, a link between the SP and the device is maintained. On the other hand, if the identifiers do not match, the link between the SP and the device is terminated or otherwise inhibited.

Abstract: Embodiments generally relate to hot-plug technology. The present technology discloses hardware and software specifications that can enable hot-plug functions for high-bandwidth and low-latency data transmission within a computing system. The present technology can provide hot-plug functions to PICe devices within a server rack by utilizing various controllers and power indicators embedded in the system. In addition to PCIe, the present technology can provide hot-plug functions to other high-throughput computer I/O (Input/Output) expansion technologies.

Abstract: A method and system are provided for generating customized program logic operable to control hardware devices of a target system and to boot said target system. The system is connected to one or more target systems via a network, the server system being adapted for: receiving a first list of device identifiers from one of the target systems; automatically selecting, for each of the device identifiers in the received first list, at least one driver operable to control the identified device from a set of drivers, thereby generating a sub-set of said set of drivers; providing a core program logic to the target system; and providing the sub-set of drivers to the target system, wherein a combination of the sub-set of drivers and the core program logic constitutes a customized program logic operable to control the devices of said target system.

Abstract: Aspects include techniques for implementing a clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry for encoding and correction of a chip. A computer-implemented method may include initializing a scan of the chip including data and a set of check bits protecting the data; applying a global control bit to a latch on the chip; and applying an additional clock to the latch so the check bits are updated using the on-chip circuitry.

Abstract: Component circuitry for a replaceable printer component, including a dynamic address generator which selectively generates component addresses, wherein substantially immediately following an event, the component circuitry performs in succession a plurality of sets of operations, each set of operations including receiving an address change request from a master and generating a new component address by the dynamic address generator in response, a last one of the new component addresses generated being available as the component address for the component circuitry in one or more subsequent communications with the master.

Abstract: Aspects include techniques for implementing a clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry for encoding and correction of a chip. A computer-implemented method may include initializing a scan of the chip including data and a set of check bits protecting the data; applying a global control bit to a latch on the chip; and applying an additional clock to the latch so the check bits are updated using the on-chip circuitry.

Abstract: A controller may drive a first digital value onto a first address terminal of a first peripheral. The controller may transmit a data message on a data bus while driving the first digital value onto the selected address terminal. The first peripheral is coupled with the data bus, in accordance with at least one embodiment. A second peripheral having a second address terminal may also be coupled to the data bus. The first peripheral may be configured to accept the data message over the data bus when the first digital value is received on the first address terminal. The second peripheral may be configured to accept the data message over the data bus when the first digital value is received on the second address terminal.

Abstract: Aspects include techniques for bypassing an encoded latch on a chip during a test-pattern scan and using on-chip circuitry to generate a desired encoded pattern, which is inserted into a scan-bypassed latch, to test the on-chip circuitry for defects. A computer-implemented method may include applying a global control bit to the chip; initializing a scan of the chip while bypassing the encoded latch; and applying an extra scan clock to initiate the encoded latch after completing the scan, wherein the encoded latch is updated with check bits generated by the on-chip circuitry.

Abstract: Aspects include techniques for bypassing an encoded latch on a chip during a test-pattern scan and using on-chip circuitry to generate a desired encoded pattern, which is inserted into a scan-bypassed latch, to test the on-chip circuitry for defects. A computer-implemented method may include applying a global control bit to the chip; initializing a scan of the chip while bypassing the encoded latch; and applying an extra scan clock to initiate the encoded latch after completing the scan, wherein the encoded latch is updated with check bits generated by the on-chip circuitry.

Abstract: Initiating data transactions on a system bus is disclosed. In some implementations, a controller receives first information from a first peripheral requesting a first data transaction. The first information is received over a first communication link between the controller and the first peripheral. The controller receives second information from a second peripheral requesting a second data transaction. The second information received over a second communication link between the controller and the second peripheral. The controller determines first and second ranks for the first and second data transactions, respectively, based on the first and second information, and initiates based on the first and second ranks, the first and second data transactions on a system bus.

Abstract: In a serial transmission method using a two-wire serial interface, a master device transmits a first synchronous serial signal via the two-wire serial interface to wake-up a slave device followed by an asynchronous data transmission on one of the two-wires of the two-wire serial interface. The asynchronous data signal directly controls a function of the slave device.

Abstract: A system that performs a bus transaction includes a transaction controller and a protection code processing circuit. The transaction controller identifies a set of parameters corresponding to the bus transaction based on address and received control information, and modifies at least one parameter or splits the bus transaction into sub-transactions depending on the parameter values to map the bus transaction to a memory address space. The protection code processing circuit generates and inserts a protection code into data to be written to the memory, and removes a protection code from data read from the memory. The system facilitates error checking without requiring modification of the channels (e.g., bus width) used to read and/or write data to memory.

Abstract: An extensible host controller applied to a host includes a universal serial bus (USB) module, a control unit, and a peripheral component interconnect express (PCIE) bus. The USB module includes a USB unit and a predetermined unit. The PCIE bus is coupled to the control unit, wherein the PCIE bus supports a USB mode and a predetermined mode. When a first host with a first extensible host controller is connected to the USB module, the control unit makes the host utilize the USB mode and the USB unit, or the predetermined mode and the predetermined unit to communicate with the first host according to a determination way.

Abstract: The present application provides a method and device for evaluating network performance, which relate to the field of communications technologies. The method includes: obtaining statistical data characterizing network performance; according to the statistical data, obtaining performance of neighbor relationship adjustment, or obtaining a degree to which the neighbor relationship adjustment affects the network performance. The present application determines impact of ANR algorithm on a network or a UE by collecting related status data, and solves a problem that whether degradation of UE performance or user experience is caused by the ANR algorithm cannot be determined in the prior art. Then a factor of ANR operation may be excluded from numerous factors which may affect a system or user experience, analysis capability of automatic troubleshooting is improved, and problem solving capability of operators is improved.

Abstract: A first set of signal carriers of a plurality of signal carriers may be determined to be faulty. The first set of signal carriers may be for transmitting a first set of respective lane signals of a plurality of lane signals. A second set of signal carriers of the plurality of signal carriers may be identified as not faulty. The second set of signal carriers may be for transmitting a second set of lane signals of the plurality of lane signals. Based on the determining and identifying, one or more of the first set of lane signals may be routed from the first set of signal carriers through a first subset of the second set of signal carriers, the routing of the one or more of the first set of lane signals may cause a bandwidth capacity to increase to a highest available bandwidth.

Abstract: According to one embodiment, there is provided a storage controlling device including a receiving unit and a controlling unit. The receiving unit receives a read command or a write command for a storage device, from an internal or external command issuing device. The controlling unit holds the write command received by the receiving unit until at least a first interval time has elapsed after outputting a write command received most recently before the write command is received, and then outputs the write command which is held after the first interval time has elapsed. The controlling unit outputs the read command received by the receiving unit, prior to outputting the write command that is held, when the read command is received during a time when the write command is held.

Abstract: Various embodiments of the present invention methods for discovery, configuration, and coordinating data communications between master and slave devices in a communication system. Exemplary embodiments are described with reference to a two-wire point-to-point bus system, although the method can be used in other communication systems. Provisions are included for controlling the sequential powering of the bus and slave devices.

Abstract: A method and system for determining a device identifier assigned to a device within an installation of devices connected via a network is provided. A system determines the device identifier of a device that has been repaired and reinstalled so that the device can be placed in service. Upon receiving an indication that a repaired device has been reinstalled, the system requests and receives a possible device identifier of the repaired device from an interconnect device that connects the repaired device to the network. To verify that the possible device identifier is the actual device identifier, the system directs the repaired device to reboot so that it broadcasts its device identifier. When the repaired device reboots, it broadcasts its device identifier. Upon receiving the broadcast device identifier, the system verifies that the possible device identifier is the same as the broadcast device identifier.

Abstract: A method and host computing device that restricts access by one or more applications to a configurable hardware logic device over a bus. At least a portion of the configurable hardware logic device is reconfigured. A determination is made when unplug and plug events have been generated by the configurable hardware logic device. The unplug and plug events are generated without disconnecting power supplied to the configurable hardware logic device. The configurable hardware logic device is re-enumerated on the bus when the determining indicates the unplug and plug events have been generated by the configurable hardware logic device.

Abstract: A USB hub includes a plurality of downstream ports; at least one dual mode port, the dual mode port configured to be switchable from a downstream port to an upstream port; and host detection circuitry for detecting whether, when operating as an upstream port, a host is connected.

Abstract: Technologies are generally described for server resource allocation for distributed games. In one example, a method includes allocating a first set of resources for a first player instance on a first server, a second set of resources for a second player instance on the first server, and a third set of resources for a third player instance on a second server. The method also includes comparing a first relationship strength defined between the first player instance and the second player instance with a second relationship strength defined between the first player instance and the third player instance. Further, the method includes distributing at least one of the first set of resources, the second set of resources, or the third set of resources between the first server and the second server based on a result of the comparing.

Abstract: A method for maintaining the functional ability of a field device of automation technology, wherein the method comprises the following steps: monitoring the field device for at least one achieved parameter change (?nx), wherein the parameter change (?nx) converts an old parameter set (nx-1) into a new parameter set (nx), storing all parameter changes (?nx) achieved in the field device in a parameter change history, monitoring the field device for an occurring malfunction (F); and, performing a remediation measure, wherein the parameter change history and/or a parameter to malfunction, linking element is accessed for remediating the malfunction occurring in the field device.

Abstract: Methods and systems for managing reset of a physical function of an I/O device in a computing system are disclosed, where the physical function is included in a single-root PCI manager. One method includes maintaining a count of active virtual functions associated with the physical function included in the single-root PCI manager, and, upon determining that no active virtual functions are associated with the physical function, allowing the physical function to be reset within the single-root PCI manager. The method further includes while resetting the physical function, persisting a configuration memory space associated with the physical function, and associating the persisted configuration memory space with the physical function after the physical function is reset.

Abstract: A Hardware Abstract Data Structure (HADS) includes a General Interface (GI), a Coherence Interface (CI), a Control and Configuration Logic (CCL), an Intelligence Logic (IL) and a Memory Pool (MP), wherein the GI is arranged to implement intercommunion between the HADS and a processor; the CI is arranged to implement coherence storage between multiple processors; the CCL is arranged to, in response to a command received by the GI, configure a hardware data structure for the MP; the IL is arranged to complete a large amount of simple and frequent data processing; and the MP is arranged to store data. Correspondingly, a method and data processing system are also disclosed. Through the disclosure, the HADS which is dynamically configurable, flexible, efficient, universal in interface and good in interconnectivity can be implemented to improve the data processing efficiency.

Abstract: Examples of techniques for transparent north port recovery of an error in an input/output device are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processing device, a command timeout; sending, by the processing device, an input/output (I/O) error signal to a host processing system connected to the hardware device via a north port of the hardware device; terminating, by the host processing system, a link between the north port of the hardware device and the host processing system; enabling, by the processing device, halt command forwarding on the hardware device; halting, by the processing device, commands upon detecting the halt command forwarding; and resetting, by the processing device, the link between the north port of the hardware device and the host processing system.

Abstract: A multi-mode base station and an operating method and a wireless communication system thereof are provided. The multi-mode base station includes: at least two protocol processing modules, vested in at least two modes respectively, and adapted to process data and/or signaling of the mode according to the protocol corresponding to the mode; and an interface processing module, adapted to distinguish the mode of the data and/or the signaling while receiving the data and/or the signaling, and distribute the data and/or the signaling to the protocol processing module corresponding to the mode. Thus, the reconfiguration of the multi-mode base station can be performed more conveniently and quickly.

Abstract: A tablet information handling system manages thermal conditions with selective installation of either a wireless wide area network interface card or an air moving device in an internal communication link card slot, such as an M.2 card slot. If an air moving device is installed, then greater thermal demands may be managed at the tablet information handling system, such as greater CPU clock speeds for a given CPU, internal housing or skin temperature. For example, a piezoelectric bellows-based fan having substantially the same footprint as a WWAN NIC and powered from the communications slot interface aids distribution of thermal energy whether or not the tablet housing has air vents.

Abstract: A fault-tolerant computer system architecture includes two types of operating domains: a conventional first domain (DID) that processes data and instructions, and a novel second domain (MM domain) which includes mentor processors for mentoring the DID according to “meta information” which includes but is not limited to data, algorithms and protective rule sets. The term “mentoring” (as defined herein below) refers to, among other things, applying and using meta information to enforce rule sets and/or dynamically erecting abstractions and virtualizations by which resources in the DID are shuffled around for, inter alia, efficiency and fault correction. Meta Mentor processors create systems and sub-systems by means of fault tolerant mentor switches that route signals to and from hardware and software entities. The systems and sub-systems created are distinct sub-architectures and unique configurations that may be operated as separately or concurrently as defined by the executing processes.

Abstract: Methods and apparatus, including computer program products, are provided for cable, connectors, and/or other devices. In one aspect there is provided an apparatus. The apparatus may include a first interface configured to enable coupling to a universal serial bus device; a controller circuitry configured to at least determine an amount of current and/or voltage available at a mobile high-definition link device when coupled and adjust, based on the determined amount, a value of pull up circuitry coupled to the first interface; and a second interface configured to enable coupling to Mobile High-definition link device. Related apparatus, systems, methods, and articles are also described.

Abstract: In one embodiment, a system includes: a plurality of compute nodes to couple in a chassis; a first shared power supply to provide a baseline power level to the plurality of compute nodes; and an auxiliary power source to provide power to one or more of the plurality of compute nodes during operation at a higher power level than the baseline power level. Other embodiments are described and claimed.

Abstract: The present invention relates to a multimedia server means, comprising a plurality of universal serial bus, USB, connections and a processing means configured to establish a one-by-one data connection between a USB data storage device connected to a first one of the plurality of USB connections and an electronic device connected to a second one of the plurality of USB connections.

Abstract: Information representative of a graph-based program specification has a plurality of components, each of which corresponds to a task, and directed links between ports of said components. A program corresponding to said graph-based program specification is executed. A first component includes a first data port, a first control port, and a second control port. Said first data port is configured to receive data to be processed by a first task corresponding to said first component, or configured to provide data that was processed by said first task corresponding to said first component. Executing a program corresponding to said graph-based program specification includes: receiving said first control information at said first control port, in response to receiving said first control information, determining whether or not to invoke said first task, and after receiving said first control information, providing said second control information from said second control port.

Abstract: In accordance with embodiments of the present disclosure, a controller may be communicatively coupled to each of a plurality of slots and configured to identify the type of module received in each of the plurality of slots, and, based on one or more deterministic rules, assign each particular peripheral node type module to a corresponding compute node type module such that information handling resources of the particular peripheral type node are used by a compute node on the corresponding compute node type module as a peripheral of the compute node.

Abstract: A memory subsystem has multiple memory devices coupled to a command/address line and an error alert line, the error alert line delay-compensated to provide deterministic alert signal timing. The command/address line and the error alert line are connected between the memory devices and a memory controller that manages the memory devices. The command/address line is driven by the memory controller, and the error alert line is driven by the memory devices.

Abstract: A building block includes an XSCF that controls the building block and an XBU that performs communication with another building block. The XSCF includes a hardware controller that instructs crossbar diagnosis to the XBU. The XBU includes a port information storage unit that stores therein diagnosis information related to the crossbar diagnosis and a test module that performs the crossbar diagnosis on the basis of the diagnosis information stored in the port information storage unit.

Abstract: A computing device writes data across storage devices in an erasure-coded system. The computing device computes data blocks and parity blocks from data and computes a portion of the data to be stored in the system. The computing is performed by one or more controllers included in a redundant array of an independent disks controller. The computing device provides the locations of the data blocks and the parity blocks in storage devices of an erasure-coded system. The location is determined using one or more placement nodes. The placement nodes are configured for managing placement schemes of data blocks and parity blocks on the storage devices.

Abstract: Systems, methods, circuits and computer-readable mediums for peripheral sequencing using an access sequence are disclosed. In some implementations, a control register and status register in a peripheral are initialized with control data for selecting peripheral registers of the peripheral to be refreshed during an access sequence. For each peripheral register to be refreshed during the access sequence: a data register of the peripheral register is accessed; the peripheral register is refreshed; and the status register is updated with a current status of the access sequence. The access sequence is determined to be completed based on contents of the status register.

Abstract: A fault isolation method, computer system, and apparatus, which are capable of monitoring a state of a second endpoint device in the extended domain, and setting a device state record according to the state of the second endpoint device; after an access request between the second endpoint device and the primary domain is received, querying the device state record according to identifier information that is of the second endpoint device and in the access request, and determining the state of the second endpoint device; and if the state of the second endpoint device is a fault state, discarding the access request to prevent communication between the faulty second endpoint device and the primary domain and prevent spreading a fault to the primary domain, thereby ensuring system reliability.

Abstract: A constantly power-ON domain and a standby-time power OFF domain are included on the same chip, and the constantly power-ON domain includes: a shutoff control circuit shutting off a signal inputted and outputted between the constantly power-ON domain and the standby-time power OFF domain when the first power source is ON and the second power source is OFF; and a shutoff control circuit outputting a first control signal indicating that shutoff of an emergent shutoff control circuit unit is to be enabled or disabled, the standby-time power OFF domain includes the emergent shutoff control circuit unit shutting off, based on the first control signal from the shutoff control circuit, the signal inputted between the emergent shutoff control circuit unit and the constantly power-ON domain.

Abstract: Systems and methods consistent with the present disclosure include techniques for automatically switching a non-transparent bridge enabled root port (NeRP) device from a non-transparent bridge configuration state and a root port configuration state. A NeRP agent consistent with the present consistent includes a root port agent within a computing fabric network coupled to a first multiplexer and to a second multiplexer. The root port agent includes training circuitry to initiate a root port configuration state upon detection of a root port. Furthermore, the training circuitry also initiates a device configuration state upon detection of an endpoint port. A non-transparent bridge device is coupled to the first multiplexer and second multiplexer. In addition, an input/output (I/O) connector is coupled to the root port agent during the root port configuration state and coupled to the local NTB device and root port agent during the device configuration state.

Abstract: Described herein is a processing apparatus, film scanner and associated method, such as a processing apparatus for processing motion picture film, comprising an identification module for identifying selected regions of one or more digital images or digital video clips of the film; and an image modification module configured to access or produce data; and modify at least one of the one or more digital images or the digital video clip so as to provide the data in at least one of the selected regions. Advantageously, the selected regions correspond to perforations in the film.