Abstract: An example replaceable print material supply cartridge that is removably couplable to a host printer is disclosed. The example replaceable print material supply cartridge includes an ink reservoir and a logic circuitry package. The logic circuitry package includes logic circuitry and a serial data bus interface, wherein the serial data bus interface is to interface with a serial data bus of the host printer. In response to a first command sent to the logic circuitry package via the serial data bus connected to the serial data bus interface, the first command including a time period, the logic circuitry is to cause generation of a low voltage condition on the serial data bus for a duration based on the time period, and, after the duration, cause a return to a default voltage condition on the serial data bus.

Abstract: According to an embodiment, a memory system comprises a resistive memory device configured to perform a read operation and a write operation based on a command and an address, wherein the resistive memory device includes a plurality of banks each including a plurality of memory cells; and a memory controller configured to schedule a request from a host to generate the command and the address, wherein, when a time interval is less than a first time, the memory controller is configured to stop generation of the command and re-schedule the command corresponding to the request, the time interval spanning from a time of generation of a prior write command for a same memory cell to a time of generation of the command generated according to the request.

Abstract: A method for conducting bus arbitration in a hardware tester system comprising a single master controller and a multi-master controller comprises configuring the single master controller with arbitration logic operable to communicate on a bus in the hardware tester system using a same arbitration scheme as the multi-master controller, wherein the single master controller and the multi-master controller are connected to the bus. Further, responsive to a determination by the arbitration logic that the multi-master controller controls the bus, the method comprises withdrawing the single master controller from attempting to control the bus.

Abstract: A data storage device includes: a data storage medium; a processor comprising a plurality of processor cores; a plurality of application acceleration black-box (AABB) slots including reconfigurable logic blocks, interconnects, and memories; a host interface that receives a host command from a remote application running on a remote host computer, wherein the host command includes an image file including a register-transfer level (RTL) bitstream and a firmware driver; and a configuration controller that downloads the RTL bitstream to an AABB slot of the plurality of AABB slots and reconfigure the AABB slot, and load the firmware driver to a processor core of the processor. The processor core loaded with the firmware driver runs a data acceleration process of the remote application to access and process data stored in the data storage medium using the RTL bitstream downloaded in the AABB slot.

Abstract: A motor control system includes: a d-q target module configured to, based on a target torque of an electric motor, determine a first target d-axis current and a first target q-axis current; an offset module configured to, based on a capacitor current through capacitors connected across phases of the electric motor, determine a d-axis current offset and a q-axis current offset; an adder module configured to determine a second target d-axis current based on a sum of the first target d-axis current and the d-axis current offset and to determine a second target q-axis current based on a sum of the first target q-axis current and the q-axis current offset; and a driver module configured to, based on the second target d-axis current and the second target q-axis current, switch switches of a current source inverter (CSI) module configured to apply power to the phases of the electric motor.

Abstract: A network-on-package (NoPK) for connecting a plurality of chiplets may include a plurality of interface bridges configured to convert a plurality of protocols used by the plurality of chiplets into a common protocol, a routing network configured to route traffic between the plurality of interface bridges using the common protocol, and a controller configured to program the plurality of interface bridges and the routing network based on types of the plurality of chiplets connected to the NoPK. The NoPK may provide a scalable connection for any number of chiplets from different ecosystems using different communication protocols.

Abstract: The subject of the invention is a system (1), having a master (900), a first slave (100), a second slave (200), and a bus (40), wherein the master (900) and the first slave (100) and the second slave (200) are connected to one another by the bus (40) in order to transmit a data packet (4) from the master (900) via the first slave (100) and back to the master (900) via the second slave (200), in which the master (900) is configured to generate the data packet (4) with a header (4.1) and a data unit (4.2) and to send the generated data packet (4) on the bus (40), in which the first slave (100) is configured to write its first address (A1) and first payload data (D1) into a first segment (10) of the data unit (4.2) of the data packet (4), in which the second slave (200) is configured to write its second address (A2) and second payload data (D2) into a second segment (20) of the data unit (4.

Abstract: A data processing system may include a plurality of memory systems and a host configured to provide commands for the memory systems. A first memory system among the memory systems may receive the commands from the host, check each of the memory systems where a plurality of command operations corresponding to the commands are to be performed, transmit respective commands among the commands to respective remaining memory systems except for the first memory system among the memory systems through a plurality of dedicated channels, and perform a first command operation corresponding to the first memory system in at least one of the remaining memory systems.

Abstract: A data storage device includes: a data storage medium; a processor comprising a plurality of processor cores; a plurality of application acceleration black-box (AABB) slots including reconfigurable logic blocks, interconnects, and memories; a host interface that receives a host command from a remote application running on a remote host computer, wherein the host command includes an image file including a register-transfer level (RTL) bitstream and a firmware driver; and a configuration controller that downloads the RTL bitstream to an AABB slot of the plurality of AABB slots and reconfigure the AABB slot, and load the firmware driver to a processor core of the processor. The processor core loaded with the firmware driver runs a data acceleration process of the remote application to access and process data stored in the data storage medium using the RTL bitstream downloaded in the AABB slot.

Abstract: Disclosed herein is a convolutional neural network (CNN) operation apparatus, including at least one channel hardware set suitable for performing a feature extraction layer operation and a classification layer operation based on input data and weight data, and a controller coupled to the channel hardware set. The controller may control the channel hardware set to perform the feature extraction layer operation and perform a classification layer operation when the feature extraction layer operation is completed.

Abstract: Aspects are directed to systems in which control node communicates through a peripheral-side wired communications bus for data communications with other bus-coupled nodes. The control node acts as a master with a main-circuit domain during an initialization mode and when the main-circuit domain is deactivated, and acts as a slave, after completion of the initialization mode and when the main-circuit domain is not deactivated. An isolation circuit is used to isolate the main-circuit domain from the control node and, while the main-circuit domain is deactivated, to facilitate communications over the peripheral-side wired communications bus between the control node and another node connected to the peripheral-side wired communications bus.

Abstract: To perform communication more definitely and efficiently. In order to perform communication in which a group address is used setting a plurality of arbitrary slaves to a single group and setting the group to a destination, a slave having a group-belonging capability capable of belonging to the group and performing communication is recognized. Then, in a state in which a slave having the group-belonging capability and a slave having no group-belonging capability mixedly join in a bus, the group address is assigned to the slave recognized to have the group-belonging capability. The present technology is, for example, applicable to a bus IF.

Abstract: Methods, systems, and devices for drive strength calibration for multi-level signaling are described. A driver may be configured to have an initial drive strength and to drive an output pin of a transmitting device toward an intermediate voltage level of a multi-level modulation scheme, where the output pin is coupled with a receiving device via a channel. The receiving device may generate, and the transmitting device may receive, a feedback signal indicating a relationship between the resulting voltage of the channel and an value for the intermediate voltage level. The transmitting device may determine and configure the driver to use an adjusted drive strength for the intermediate voltage level based on the feedback signal. The driver may be calibrated (e.g., independently) for each intermediate voltage level of the multi-level modulation scheme. Further, the driver may be calibrated for the associated channel.

Abstract: Embodiments of an N-channel serial peripheral interface are described, and N-channel serial communication links comprising the same. Also described are methods of communication using N-channel serial communication interfaces and links.

Abstract: A self-detection mechanism for an IC is disclosed that determines whether the IC's internal bus is in a hanging state. An initialization sequence can be modified after a soft reset by reading data from an internal DRAM of the IC using a Direct Memory Access (DMA) controller as part of the initialization sequence. The read command is issued over the internal bus and, if the bus is hanging, the read command is not completed. Monitoring can be performed by waiting a predetermined period of time (e.g., 100 ms) to determine if the read was properly completed. If so, no further action is needed. If the read was not completed, then a hard reset is requested to be performed. Thus, an initialization sequence can be modified to run dummy transactions through the internal bus, and validate that all paths are functional.

Abstract: A processing in memory (PIM) device includes a memory configured to receive data through a first path from a host processor provided outside the PIM device, and an information gatherer configured to receive the data through a second path connected to the first path when the data is transferred to the memory via the first path, and to generate information by processing the data received through the second path.

Abstract: Methods, systems, and apparatus described herein make a multi-level PAM signal (PAM-N signal) at a transmitter using CMOS-based components. By forming the PAM-N signal at the transmitter, receivers do not have to recombine and/or realign multiple signals and only employs a single transmission line channel (or two transmission line channels in differential implementations) to convey the data stream to the receiver from the transmitter.

Abstract: An access control method of the disclosure includes: allowing one master device of a plurality of master devices to generate a request for access to a device to be accessed; allowing a slave device to identify, on a basis of the request for the access, the one master device that has generated the request for the access; and allowing the slave device to make a response to the one master device, at response timing that corresponds to the one master device identified.

Abstract: A system includes a plurality of items of master equipment, each having a programing interface, and a plurality of slave equipment. An interconnect circuit is coupled between the items of master equipment and the items of slave equipment. Each transaction is assigned an attribute capable of taking on at least two attribute values corresponding to at least two states for the master equipment. Each item of slave equipment is associated with an identifier capable of taking on at least two values corresponding respectively to at least two properties for the slave equipment. Each item of master equipment automatically inherits the property of its programing interface. A filtering circuit is configured to, in the presence of a transaction intended for an item of slave equipment, compare the corresponding attribute value with an identifier value of the intended slave equipment and reject or not reject the transaction based on the comparison.

Abstract: A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A controller or primary device coupled to the SPI bus can generate a message with read or write instructions for one or more secondary devices. In an example, the primary device can be configured to use information on a data input port or data input bus to determine a communication status of one or multiple secondary devices on the bus.

Abstract: In an example, a logic circuitry package is configured to communicate with a print apparatus logic circuit. The logic circuitry package may be configured to respond to communications sent to a first address and to at least one second address. The logic circuitry package may comprise a first logic circuit, wherein the first address is an address for the first logic circuit. The package may be configured such that, in response to a first command indicative of a task and a first time period sent to the first address, the package is accessible via at least one second address for a duration of the time period.

Abstract: A CPU needs to perform reset operation when a secondary arithmetic processing unit controlled by the CPU controls a signal processing circuit. CPU A controls module A. CPU B controls module B. Module A and module B control a signal processing circuit. CPU A and CPU B issue a reset request to the signal processing circuit. The signal processing circuit performs a reset process based on the reset request accepted from the CPU and a control origin identification signal that identifies a CPU as an origin of controlling the module having started a signal processing section.

Abstract: A method assigns addresses from a master unit to a number of slave units. The slave units are connected to the master unit for the transmission of information. An address output of the master unit is connected to an address input of a first slave unit and the address output of an n-th slave unit is connected to the address input of an n+1-th slave unit. The slave units, when a first level is applied to their address input, set the level at their address output to the first level and change to the first, “non-addressed” state, in the event of a transition of the level at their address input from the first level to a second level, change to the “addressable” state, upon receiving an address from the master unit, check the received address for validity in the “addressable” state and, acknowledge the reception to the master unit.

Abstract: In one embodiment, an apparatus includes: a peer-to-peer (P2P) control circuit to issue a P2P communication request to a bus master of a multi-drop interconnect to request authorization to send a P2P transaction to at least one slave device coupled to the multi-drop interconnect; a transmitter to transmit the P2P transaction to the at least one slave device when the bus master grants the authorization for the P2P transaction; and another transmitter to output the clock signal to the multi-drop interconnect during the P2P transaction. Other embodiments are described and claimed.

Abstract: Systems, methods, and apparatus managing access to a power management device are disclosed. A system has a primary integrated circuit and a power management integrated circuit. The primary integrated circuit has a communication controller configured to control access to a first serial bus for a plurality of subsystems in the primary integrated circuit. The power management integrated circuit is coupled to the first serial bus and to a second serial bus. An access control circuit in the power management integrated circuit is configured by the primary integrated circuit to control access to the power management integrated circuit through the second serial bus. The primary integrated circuit may be configured to write an access control configuration to the power management integrated circuit. The access control configuration may define write access rights for a secondary integrated circuit coupled to the power management integrated circuit through the second serial bus.

Abstract: Disclosed are apparatus and methods for programming a plurality of nonvolatile memory (NVM) devices. Each NVM device self-generates and stores a unique encryption key. Each NVM device concurrently receives an image from a multiple-device programming system to which all the NVM devices are communicatively coupled. Each NVM device encrypts the received image using such NVM device's unique encryption key to produce a unique encrypted image for each NVM device. Each NVM device stores its unique encrypted image within a nonvolatile memory of such NVM device. The unique encryption key can then be securely transferred to a host device for decrypting the image accessed from one of the NVM devices.

Abstract: A slave device includes an SPI bus with a mode detection circuit configured to detect an SPI operating mode that has been applied by a master device. The slave device is configurable to operate in a first or a second mode depending on the detection of the SPI operating mode as applied by the master device.

Abstract: An information handling system may include a bus initiator, a plurality of bus endpoints, and a bus communicatively coupled between the bus initiator and the plurality of bus endpoints, wherein the bus comprises a multiplexer topology of a plurality of multiplexers. The bus initiator may be configured to perform in-band addressing to select a communications channel through the multiplexer topology via an addressing protocol that uses pulse bursts for initiation of the addressing, identification of the communications channel, and termination of the addressing. Pulses of the pulse bursts may be sufficiently short in duration to pass through filters of the bus endpoints such that the pulse bursts are not processed by the endpoints.

Abstract: A System on Chip (SoC), including a plurality of processor cores including a secure master, which is configured to run security software, and a non-secure master, which is configured to run non-security software; a resource configured to be shared by the secure master and the non-secure master; and a state machine configured to protect the resource by allowing only the secure master to transition the resource to a particular state of the state machine, and allowing only the non-secure master to transition the resource to another particular state of the state machine.

Abstract: Circuitry comprises attribute storage circuitry having a plurality of entries to hold data defining at least a transaction attribute of one or more respective data handling transactions initiated by transaction source circuitry; comparator circuitry to compare a transaction attribute of a given data handling transaction with data held by the attribute storage circuitry to detect whether the given data handling transaction would be resolved by any data handling transaction for which attribute data is held by a respective entry in the attribute storage circuitry; and control circuitry to associate the given data handling transaction with the respective entry in the attribute storage circuitry to form a set of associated data handling transactions when the comparator circuitry detects that the given data handling transaction would be fulfilled by the data handling transaction for which attribute data is held by the respective entry in the attribute storage circuitry; the control circuitry comprising output circu

Abstract: In one embodiment, the clock management circuitry includes a first master clock controller configured to provide a first command to a first slave clock controller via a first channel based on a received first clock request. The clock management circuitry also includes the first slave clock controller configured to control outputting a first clock signal based on the first command.

Abstract: A semiconductor device capable of executing a plurality of tasks in real time and improving performances is provided. The semiconductor device comprises a plurality of processors and a plurality of DMA controllers as master, a plurality of memory ways as slave, and a real-time schedule unit for controlling the plurality of masters such that the plurality of tasks are executed in real time. The real-time schedule unit RTSD uses the memory access monitor circuit and the data determination register to determine whether or not the input data of the task has been determined, and causes the task determined to have the input data determined to have been determined to be executed preferentially.

Abstract: A bus architecture is disclosed that provides for transaction queue reallocation on the modules communicating using the bus. A module can implement a transaction request queue by virtue of digital electronic circuitry, e.g., hardware or software or a combination of both. Some bus clogging issues that affect conventional systems can be circumvented by combining an out of order system bus protocol that uses a transaction request replay mechanism. Modules can evict less urgent transactions from transaction request queues to make room to insert more urgent transactions. Master modules can dynamically update a quality of service (QoS) value for a transaction while the transaction is still pending.

Abstract: Systems and methods for functionality management of devices are disclosed. Multiple computing devices may be located in the same environment and/or space and at least two of those computing devices may be configured to perform a given functionality. In these and other examples, one of the devices may be identified as a primary device and the other devices may be identified as secondary devices based on, for example, historical usage data, audio-signal data, computer-vision analysis, and/or one or more other criteria. The functionality may be disabled on the secondary devices until the secondary devices are utilized and/or until a triggering event occurs.

Abstract: A logic circuitry package for association with a replaceable print apparatus component comprises: logic and a serial data bus interface, wherein the serial data bus interface is to interface with a serial data bus of a print apparatus, and, wherein the logic is, in response to a first command sent to the logic circuitry package via the serial data bus connected to the serial data bus interface, the first command including a time period, to generate a low voltage condition on the serial data bus for a duration based on the time period, and, after the duration, return to a default voltage condition on the serial data bus.

Abstract: In one embodiment, an apparatus includes an input/output (I/O) circuit to communicate information at a selected voltage via an interconnect to which a plurality of devices may be coupled, and a host controller to couple to the interconnect. The host controller may include a supply voltage policy control circuit to initiate a supply voltage policy exchange with a first device to obtain a first supply voltage capability of the first device and to cause the I/O circuit and the first device to be configured to communicate via the interconnect at a first supply voltage based on the first supply voltage capability. Other embodiments are described and claimed.

Abstract: A method for identifying bus nodes in a bus system makes it possible to be able to operate bus slaves of two different types in mixed systems. The detection of which bus slave has not yet been allocated an address in an addressing phase is carried out differently depending on a type of the bus slave. In all cases, however, the bus slave connected to the bus line farthest away from the bus master is identified as that bus slave to which an address is to be allocated.

Abstract: Embodiments of the present disclosure may relate to a host controller that includes processing circuitry to identify an inter-integrated circuit (I2C) out-of-band interrupt (OBI) received on a general purpose input-output (GPIO) pin from an I2C device that is unable to generate an improved inter-integrated circuit (I3C) bus an I3C in-band interrupt (IBI). The processing circuitry may further generate, based on the I2C OBI, an I3C IBI that includes information related to the I2C OBI. The host controller may further include transmission circuitry to transmit the I3C IBI on an I3C bus. Other embodiments may be described and/or claimed.

Abstract: Systems and method include one or more die coupled to an interposer. The interposer includes interconnection circuitry configured to electrically connect the one or more die together via the interposer. The interposer also includes translation circuitry configured to translate communications as they pass through the interposer. For instance, in the interposer, the translation circuitry translates communications, in the interposer, from a first protocol of a first die of the one or more die to a second protocol of a second die of the one or more die.

Abstract: A cluster deployment and management system includes a networking device that is coupled to a network and to each of a plurality of node devices in a cluster system. The networking device discovers then validates using a cluster profile each of the plurality of node devices in the cluster system. The networking device may then configure itself and any other networking devices according to the cluster profile. The networking device may then configure each of the plurality of node devices according to the cluster profile and deploy one or more applications and data to the node devices. The networking device may negotiate which of at least two networking devices present on the network and may perform lifecycle management operations on the at least one of the node. The networking device performs lifecycle management on at least one of the node devices during operation of the cluster system.

Abstract: Each master issues an access request including a read request and a write request to a memory. A cache caches the write request issued by the master. A central bus control system performs access control for the read request issued by each master and the write request output by the cache. A central bus control system performs access control for the write request issued by each master. The central bus control system performs access control in accordance with a free situation of a buffer of a memory controller. The central bus control system performs access control in accordance with a free situation of the cache.

Abstract: In an embodiment, a method for writing to a set of serial peripheral interface (SPI) slaves coupled to an SPI bus includes: disabling master in slave out (MISO) drivers of the set of SPI slaves using the SPI bus; after disabling the MISO drivers, setting respective slave selection terminals of the set of SPI slaves to an active state; and after setting the respective slave selection terminals of the set of SPI slaves to the active state, simultaneously writing data to the set of SPI slaves using a master out slave in (MOSI) line.

Abstract: To perform communication more definitely and efficiently. In a case of transferring a communication initiative in accordance with a request by a secondary master, a master determines whether or not the secondary master that has performed the request has a group management capability. Then, when it is determined that the secondary master has no group management capability, the master instructs all communication devices connected to a bus to reset a group address, and when it is determined that the secondary master has the group management capability, the master transfers the communication initiative in a state in which the group address is set. The present technology is, for example, applicable to a bus IF.

Abstract: Providing collision avoidance protection to controllers sharing the same sensor. Each of a pair of asynchronous controllers changes the period of a sync pulse transmitted to the other controller to indicate to the other controller it is synchronized. When one of the controllers begins reading data from the shared sensor, the other controller waits to receive another sync pulse for indicating when the controller is finished reading data from the shared sensor. Thus, the asynchronous controllers avoid accessing the same sensor at the same time.

Abstract: A memory system includes a first substrate including a first signal terminal and a second signal terminal electrically connected to a bus, a first circuit in which a first switching element and a first resistor are connected in series between a first terminal and a second terminal, the first terminal connected to the first signal terminal, a second circuit in which a second switching element and a second resistor are connected in series between a third terminal and a fourth terminal, the third terminal connected to the second signal terminal, a first memory electrically connected to the second terminal, a second memory electrically connected to the fourth terminal, and a controller electrically connected to the bus and configured to control the first and second switching elements.

Abstract: Systems, methods, and apparatus for improving addressability of slave devices coupled to a serial bus are described. A method the slave device includes delaying transitions in a control signal received at an input pin of the slave device, enabling a counter after detecting a delayed first transition in the control signal, where the counter is configured to count pulses on a data line of a serial bus, transmitting a first pulse on the data line of the serial bus after enabling the counter, counting the first pulse and one or more additional pulses on the data line of the serial bus, and using an output of the counter to generate a unique identifier used for communicating over the serial bus. Each of a plurality of slave devices may be configured to transmit one of the additional pulses on the serial bus after the first transition occurs in the control signal.

Abstract: Logic circuitry packages for association with replaceable print apparatus components are disclosed herein. An example logic circuitry package includes a timer and a serial data bus interface including a data contact and a clock contact, the serial data bus interface to interface with a serial data bus of a printer. The example logic circuitry package also includes logic circuitry to, in response to a first command sent to the logic circuitry package via the serial data bus of the printer: initiate a low voltage on the data contact; wait for a time period tracked by the timer to expire, without reference to a clock signal at the clock contact from the serial data bus; and upon expiration of the time period, cause the data contact to assume a second voltage different than the low voltage. The first command specifies a duration of the time period and the example logic circuitry is to maintain the low voltage on the data contact based on the duration of the time period.

Abstract: A method for developing TDM data with embedded control data includes obtaining signal data and control data, formatting the signal data and the control data into a plurality of channels of a DIN signal, and transmitting the DIN signal on one line of a 3-bit TDM bus. A multichannel input device includes a control extractor receptive to the three-bit TDM bus and operative to extract CNTL data from the DIN data, a DAI receptive to the 3-bit TDM bus and the channel select input and operative to develop a SIGNAL data output, and a DAC block including a DAC, the DAC block being receptive to the SIGNAL data and the CNTL data.

Abstract: A peripheral device having a connector receptacle capable of identifying a master-slave mode includes a body and a connector module. The connector module includes a processing unit, an energy storage unit, and a connector receptacle. When the connector module is connected to an electronic device through a power positive terminal, a power negative terminal, a signal positive terminal, a signal negative terminal, and a transmission cable, the processing unit transmits a notification signal to the electronic device through the positive terminal of the signal and the negative terminal of the signal to notify the electronic device that the electronic device does not need to provide power to the peripheral device.

Abstract: A system and method for providing network information using a short-range wireless communication path between a communication device and a terminal device is described. In some examples, authentication information is required from the terminal device prior to communication of the network information. In some examples, the short-range wireless communication path is disconnected and reestablished in which one of the terminal device and the communication device changes operation modes of a short-range wireless interface.