Abstract: A method for minimizing skew in a High Bandwidth Memory (HBM) device is provided. The method includes grouping a plurality of information bits of the HBM device into at least two groups of information bits, wherein the plurality of information bits includes a plurality of data bits and a plurality of control bits, and the plurality of information bits are grouped such that each group of the at least two groups includes at least one control bit and the at least two groups form a byte of data. The method further includes delaying the plurality of information bits of each group of the at least two groups during a data transfer operation to minimize the skew between the at least two groups of information bits.

Abstract: Embodiments herein provide for avoiding address collisions in a memory device. In one embodiment, a memory controller includes a command scheduler operable to process a read-modify-write I/O command to a location in memory, to detect another I/O command to the same memory location while the read-modify-write I/O command is accessing the memory location, and to stall the other I/O command until the read-modify-write I/O command is complete while allowing a third I/O command to access the memory.

Abstract: Legacy bus operations, such as x86 I/O instructions having an address space separate from memory address space, are supported in a system in which I/O devices are coupled to a microcontroller connected via an SPI bus or other bit-serial bus. Each legacy bus operation is recognized and trapped by an interface controller, such as a south-bridge controller, which maps the trapped legacy bus operation into a corresponding bit-serial bus transaction, and transacts this corresponding bit-serial bus transaction on the bit-serial bus. Existing software infrastructure using x86 I/O instructions can remain intact, with I/O transactions bound for the SPI bus.

Abstract: A control method executed by an information processing device including a memory configured to store information on a plurality of temporary routes set for each kind of service, the control method includes receiving a routing request from a switch among a plurality of switches; extracting, from the memory, a temporary route corresponding to a service related to the routing request when it is determined that processing congestion of the information processing device occurs; setting the extracted temporary route for one or more related switches among the plurality of switches; determining a route corresponding to the service, based on a predetermined condition of the service, when it is determined that the processing congestion of the information processing device has subsided; and setting the determined route for the one or more related switches among the plurality of switches.

Abstract: A data processing system having a master device and a plurality of slave devices uses interconnect circuitry to couple the master device with the plurality of slave devices to enable transactions to be performed by the slave devices upon request from the master device. The master device issues a multi-transaction request identifying multiple transactions to be performed, the multi-transaction request providing a base transaction identifier, a quantity indication indicating a number of transactions to be performed, and address information. Request distribution circuitry within the interconnect circuitry analyses the address information and the quantity indication in order to determine, for each of the multiple transactions, the slave device that is required to perform that transaction. Transaction requests are then issued from the request distribution circuitry to each determined slave device to identify which transactions need to be performed by each slave device.

Abstract: This monitoring system for photovoltaic power generation includes: a first to n-th power collecting systems each for supplying a power conditioner with collected outputs from plural photovoltaic panels via a connection box; slave devices provided for connection boxes respectively belonging to the first to n-th power collecting systems, each slave device collecting measurement information about power generation and transmitting the collected measurement information by use of a direct current electrical path of the power collecting system thereof; a master device provided at a power collection end on an inlet side of the power conditioner to obtain the measurement information; a system selection unit for selecting one power collecting system upon reception of a selection signal from the master device and causing power line communication to be performed by use of a direct current electrical path of the selected power collecting system; and a monitoring device connected to the master device.

Abstract: A LIN communication system includes a master controller, and at least one slave controller connected to the master controller via local interconnect network (LIN) communication. The master controller allows the at least one slave controller to enter a sleep mode in a normal situation through a sleep mode message of an unconditional frame provided via the LIN communication and checks a failure state of the at least one slave controller in an abnormal situation.

Abstract: Wearable electronic apparatus providing sensory feedback is provided. The wearable electronic apparatus has master beads that can power slave beads. The beads have electronic circuitry enabling visual, auditory or haptic feedback to be initiated by the master beads. Master beads of one unit of a wearable electronic apparatus communicate with master beads of another unit of another apparatus. In the presence or proximity of an authorized apparatus, the master bead causes the slave beads to provide a user with sensory feedback.

Abstract: A system and method are provided for managing internal-computer system communications in an SPI management system. The system includes a storage device, at least one serial bus interface to interface with a serial bus, and a processing unit that accesses via the at least one serial bus interface, master data propagating from a master device along the serial bus. The processing unit stores, in the storage device, at least one of timing and phase data related to clock pulses associated with the master data, and a phase relationship between the clock pulses and at least one of the master data and return data propagating from a slave device in response to the master data.

Abstract: Disclosed herein is a power supply device including: a position detection signal output section configured to output a position detection signal to a line allowing a current flow in only one direction in response to an order to output the position detection signal from a power supply managing device connected to a bus line including the line; a position detection signal detector configured to detect the position detection signal that is output from another device and flows through the line; and a position detection signal responder configured to respond that the position detection signal is detected to the power supply managing device when the position detection signal is detected by the position detection signal detector.

Abstract: The present disclosure provides signaling control among multiple communication interfaces of an electronic device based on signal priority. According to an aspect, an electronic device includes multiple communication interfaces. The electronic device also includes a communication controller configured to determine priority of signals to be communicated on different communication interfaces among the plurality of communication interfaces. Further, the communication controller is configured to determine an order of communication of the signals among the different communication interfaces based on the priority of the signals to be communicated. The communication controller is also configured to control communication of the signals among the different communication interfaces based on the determined order of communication.

Abstract: A data storage system includes a storage server, including non-volatile memory (NVM) and a server network interface controller (NIC), which couples the storage server to a network. A host computer includes a host central processing unit (CPU), a host memory and a host NIC, which couples the host computer to the network. The host computer runs a driver program that is configured to receive, from processes running on the host computer, commands in accordance with a protocol defined for accessing local storage devices connected to a peripheral component interface bus of the host computer, and upon receiving a storage access command in accordance with the protocol, to initiate a remote direct memory access (RDMA) operation to be performed by the host and server NICs so as to execute on the storage server, via the network, a storage transaction specified by the command.

Abstract: The present disclosure is directed to an input/output module.

Abstract: A system and methodology for effectively managing, without interrupting the overall system, the power and control logic of the system during the removal, insertion and programming of programmable components that control the logic. The system and methodology detect a removal of a first programmable component from its socket and switch at least one control signal from being driven by the first programmable component to being driven by the second programmable component. Upon detecting an insertion of the first programmable component into its socket, the system and methodology switch the at least one control signal from being driven by the second programmable component to being driven by the first programmable component.

Abstract: A method, computer program product, and system to implement access control from a master device to a slave device over an inter-integrated circuit (I2C) interface are described. The method includes generating, using a processor, a control block defining the access control to the slave device over the I2C interface. The generating the control block is performed by the trusted code layer and the generating the control block is prohibited by the user-modifiable code layer. The method also includes controlling a command over the I2C interface to the slave device based on a generated command from the trusted code layer and the user-modifiable code layer in accordance with the control block.

Abstract: A method for a deterministic selection of a sensor from a plurality of sensors, having a control unit and multiple sensors connected to the control unit by means of a three-wire bus, wherein the sensors are connected to the three-wire bus through at least two lines in parallel to one another, and a protocol frame in conformity with the SENT specification is used between the control unit and the sensors for a data exchange, and a particular sensor is selected within the protocol frame by the control unit through the predefined duration of a selection signal, wherein the duration of the selection signal is determined by the interval between a first falling signal edge and a second falling signal edge.

Abstract: Embedded Universal Serial Bus (USB) debug (EUD) for multi-interfaced debugging in electronic systems are disclosed. Electronic systems contain complex integrated circuits (ICs) that require extensive testing and debugging to ensure good quality and performance. In exemplary aspects, an EUD is provided in an electronic system. The EUD is configured to send control information to and/or collect debugging information from multiple internal debugging interfaces in the electronic system. The EUD is also configured to convert the debugging information into a USB format so that the debugging information can be externally accessed through a USB interface provided by the electronic system. The EUD can provide non-invasive monitoring of the electronic system. The electronic system is able to use a USB port for communications in a mission mode while EUD is enabled. Additionally, the electronic system can turn on or off all system clocks during power-saving mode while the EUD continues to function.

Abstract: A memory interface apparatus 24 is provided with first interface circuitry 28, second interface circuitry 30 and transaction control circuitry 32. The first interface circuitry receives a first write request from a transaction master 20, 22 and issues a further transaction request associated with the memory address of the first write request via the second interface circuitry to a memory system. When an indication of the completion of the further transaction has been received at the second interface circuitry, then a second write request may be issued from the second interface circuitry to the memory system to write the target data associated with the first write request. After a write response signal in respect of the second write request is received at the second interface circuitry, then an acknowledge signal RACK indicating completion of the further transaction and that the write response signal has been received may be issued from the second interface circuitry.

Abstract: A slave device (20), which is a communication device, receives and analyzes commands, and returns the results to a master device (10). During the command analysis period, an IIC control unit (205) and a CPU (210), which form a control unit, control an SCL control unit (201) so as to stop an SCL signal. When the value of a timer (206) is equal to or less than a threshold value, transmit data are saved in a transmission FIFO (203), control for stopping the SCL signal is canceled, and in synchronization with the SCL signal, an SDA control unit (202) transmits the data saved in the transmission FIFO (203) to the master device (10). When the value of the timer (206) exceeds the threshold value, control for stopping the SCL signal is canceled, the clock control unit is placed in a state to receive the clock signal, and the SDA control unit (202) is placed in a state to receive a slave address indicating a communication device that operates in the slave mode.

Abstract: A system for efficient hub switching of mobile network devices is disclosed. The system includes a peripheral device (PD), a first control hub, and a second control hub. The PD includes a wireless long range transceiver and a microcontroller, and is controlled wirelessly by the first control hub. The first control hub and second network hub each have a wireless long range transceiver, hardware processors, and hardware memory that stores system operation information. The system operation information includes instructions for controlling the PD. Additionally, the system operation information includes instructions for listening for a response from the PD. The listening instructions include an expected response timeframe after the control instructions are sent. The system operation information further includes instructions for requesting the second control hub control the PD. Furthermore, the system operation information includes instructions for taking over control of the PD.

Abstract: An electronic device connected with numerous first load medias and numerous second load medias. The electronic device comprises a processor and a switch module. The processor is capable of switching between a first working mode and a second working mode. Under the second working mode, the processor generates a second control signal, the switch mode establishes independent electronic connections between a specified first load media and all of the second load medias, thus, the specified first load media simultaneously connects and communicates with all of the second load medias.

Abstract: An inter-integrated circuit (I2C) bus priority alert system includes sender device with a sender I2C connector. The sender device detects a first priority event and, in response, sends a first priority event alert signal through the sender I2C connector. A receiver device includes a receiver I2C connector that is connected to the sender I2C connector on the sender device over an I2C bus. The receiver device receives the first priority event alert signal from the sender device over the I2C bus and, in response, pauses a current data transmission operation that is being performed over the I2C bus. The receiver device then performs a first priority event action associated with the first priority event alert signal that addresses the first priority event such that no further actions are performed by the receiver device to address the first priority event. The receiver device may then resume the current data transmission operation.

Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

Abstract: A method and apparatus of managing a network connection of a network node comprising a NIC of a first type and a NIC of a second type. The method comprises: creating an interface device in the network node and setting the interface device to exchange data with a bridge connected to the NIC of the first type in response to detection of a failure in the NIC of the first type; determining a secondary node; instructing the secondary node to create and set a corresponding interface device; constructing a data channel between the interface device and the corresponding interface device, such that the data channel is capable of conducting data transmission using a network formed by the NICs of the second type. The apparatus corresponds to the above method.

Abstract: A method, computer program product, and system to implement access control from a master device to a slave device over an inter-integrated circuit (I2C) interface are described. The method includes generating, using a processor, a control block defining the access control to the slave device over the I2C interface. The generating the control block is performed by the trusted code layer and the generating the control block is prohibited by the user-modifiable code layer. The method also includes controlling a command over the I2C interface to the slave device based on a generated command from the trusted code layer and the user-modifiable code layer in accordance with the control block.

Abstract: A host device, coupled to a slave device through a bus interface, includes a frequency detector, a jitter detector, and a signal processing circuit. The frequency detector receives a first work frequency, and determines whether the first work frequency is the same as a second work frequency of the slave device. The jitter detector receives a first clock signal, and determines whether a jitter difference corresponding to the first clock signal exceeds a predetermined range. The signal processing unit includes a clock signal input pin, a data input pin, and an output pin. When the first work frequency is the same as the second work frequency, and the jitter difference is within the predetermined range, the signal processing circuit outputs a data signal to the slave device according to the first clock signal, data and Seems System Management Bus protocol.

Abstract: A low latency packet switching system comprising a switching device and a processing device. The switching device may include a first plurality of input/output (I/O) ports and a second plurality of I/O ports, wherein each port of the first plurality of ports may be electrically coupled to a pluggable transceiver socket configured to receive a cable connector. The processing device may include a plurality of transceivers electrically coupled to the second plurality of ports. The switching device may be configured to receive a first electric signal encoding one or more incoming data packets. The switching device may be programmed to output the first electric signal to one or more ports, in accordance with a programmable port mapping scheme. The processing device may be configured to receive the first electric signal and to output a second electric signal encoding one or more modified data packets derived from the incoming data packets.

Abstract: Using the ALTO Service, networking applications can request through the ALTO protocol information about the underlying network topology from the ISP or Content Provider. The ALTO Service provides information such as preferences of network resources with the goal of modifying network resource consumption patterns while maintaining or improving application performance. This document describes, in one example, an ALTO server that implements enhancements to the ALTO service to enable initiating incremental updates of network and cost maps to ALTO clients upon receiving status information from a content delivery network (CDN) node.

Abstract: A design assistance device includes: a design information storage section configured to store design information containing at least information of slave devices and information of a topology in a network system in accordance with a design created by a user; an actual configuration information generation section configured to generate actual configuration information containing at least the information of the slave devices and the information of the topology in the actual network system; a comparison section configured to compare the design information and the actual configuration information; and an output section configured to generate a comparison screen indicating the respective configurations of the designed network system and the actual network system along with their commonalities and differences and outputting the comparison screen to a display device.

Abstract: A method for managing power in a system, in which the system may include a first device configured to transmit serial data and a second device, coupled to the first device. The second device may include a transceiver and interrupt logic, and may be configured to activate the interrupt logic and enable a reduced power mode for the transceiver. Power consumption of the transceiver operating in the reduced power mode may be less than power consumption of the transceiver in an operating mode. The second device may also be configured to assert an interrupt signal responsive to a change in a voltage level of an input of the second device and then de-activate the reduced power mode for the transceiver responsive to the assertion of the interrupt signal.

Abstract: A memory system is deigned for impedance matching using a network of resistors that are tuned to reduce reflections on a shared bus. Any deviation from the matched state causes a mismatch and results in reflections on the bus. Overall signal reflections are reduced by balancing the back reflections occurring at a connector junction coupled to a pair of resistors and the back reflections occurring at the input of the DIMMs. This balance or tradeoff is achieved by changing the resistance value of the resistor pair to reduce the overall back reflections in the memory system.

Abstract: To provide different paths for communication of a serial signal required for high-speed communication and communication of transmission data that may be handled in low-speed communication, a circuit device includes a serial interface that receives a serial signal transmitted from a controller at a first communication speed, a transmission data input terminal that receives transmission data transmitted from the controller at a second communication speed slower than the first communication speed, and a transmission circuit that outputs a transmission signal corresponding to the transmission data based on the serial signal and the transmission data.

Abstract: An electronic apparatus is disclosed, where the apparatus revises the micro-program thereof reliably. The apparatus provides a master and slave CPUs each having a memory. The micro-program to be revised is temporarily set in the memory of the slave CPU. Interrupting the master CPU, and connecting the slave CPU with the master CPU via an auxiliary interface independent of the inner interface (bus), the micro-program to be revised and stored in the memory of the slave CPU is transferred to the memory of the master CPU through the auxiliary interface. Auxiliary interface is cut during the normal operation of the master CPU.

Abstract: An information processing device may include a master device and at least one slave device, which may be connected each other by using two types of signal lines comprising a serial clock line and a serial data line. A datum may be transmitted between the master device and the slave device according to a predetermined communication method by using the two types of signal lines. If either the master device resets the slave device, or a power supply to the master device and the slave device is turned on, the slave device may commence a starting operation. A notification of a starting condition may be provided to the master device by way of at least one of the serial clock line and the serial data line.

Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

Abstract: A start/stop condition detection circuit is coupled to receive the SDA and SCL signals from an IIC Bus. The circuit generates a first signal in response to an edge of the SDA signal and generates an inversion of the first signal as a second signal in response to an opposite edge of the SCL signal. The first and second signals are logically combined to generate an output signal. The particular directions of the edges of the SDA and SCL signals that the circuit is response to determines whether the output signal is indicative of a start condition detection or a stop condition detection.

Abstract: An electronic device associates first information and at least a first portion of a first image, and uses a second image that includes a portion corresponding to at least the first portion of the first image to access the associated first information.

Abstract: A bicycle wireless control system is basically provided with a first electric component and a second electric component. The first electric component includes a wireless transmitter that wirelessly transmits a plurality of control signals in response to a single operation of at least one operating member. Each of the control signals is transmitted for a predetermined transmission period at a predetermined non-transmission interval between adjacent ones of the control signals. The second electric component includes a wireless receiver and a controller. The wireless receiver wirelessly receives the control signal. The controller periodically operates the wireless receiver for at least two predetermined listening periods that each includes a set of predetermined listening periods with a non-listening interval therebetween.

Abstract: A processing unit exchanges data with another processing unit across a data connector that supports a particular communication protocol. When the communication protocol is updated to support a new packet type, a specification of that new packet type may be stored within software registers included within the processing unit. Under circumstances that require the use of the new packet type, packet generation logic may read the packet specification of the new packet type, then generate and transmit a packet of the new type.

Abstract: Trigger routing in computational hardware such as a digital-signal processor involves routing a trigger signal from a first, master module to a second, slave module, thereby initiating an event at the slave module without involving a core processing unit.

Abstract: Methods and systems for AXI ID compression are disclosed. Bus transaction data and an M-bit ID associated with the bus transaction data are transmitted by a master device via a bus to an ID mapper. The ID mapper is used to select, based on the M-bit ID, an N-bit ID from a plurality of N-bit IDs, where N may be less than M. The N-bit ID is associated with the bus transaction data. The bus transaction data and the N-bit ID associated with the bus transaction data are transmitted via the bus to a slave device.

Abstract: A stack method for executive devices includes the following steps: a present master-slave setting is detected of each execution device, such that the execution device is respectively set as a master device and a slave device. The master device generates coding information. It is detected if another execution device is connected successively to the current execution device, so as to process the coding information. If there is another execution device connected successively to the current execution device, the current execution device generates following coding information according to its coding information and writes the following coding information to the successive execution device as its coding information. If there is no execution device connected successively, the current execution device replies its coding information to the master device as end coding information.

Abstract: A multiprocessor system includes a master processor, at least one slave processor, and a synchronization unit. The master processor has a first flag indicating whether the master processor is in a task activation accepting state and a second flag reflective of a flag of a slave processor, iteratively updates the first flag at a frequency based on the volume of tasks processed by the master processor, and activates a task on the master processor or the slave processor based on the first flag and the second flag. Each slave processor has a third flag indicating whether the slave processor is in the task activation accepting state and iteratively updates the third flag at a frequency based on the volume of tasks processed by the slave processor. Tasks are allocated to the slave processor by the master processor. The synchronization unit synchronizes the third flag and the second flag.

Abstract: There is provided an adapter for adapting an electronic device to a modular electronic device system. The adapter generally has a housing having two lateral edges, a cavity between the lateral edges and being adapted to receive the electronic device, each of the two lateral edges of the housing having at least one magnetic coupler electrically connectable with at least one magnetic coupler of the modular electronic device system by magnetically engaging the at least one magnetic coupler of the adapter with the at least one magnetic coupler of the modular electronic device system, and an internal electric conductor network electrically connected to the magnetic couplers of the adapter and electrically connected to an internal connector which is electrically connectable to the electronic device when received in the cavity of the housing.

Abstract: A system and method can manage software services in virtualized and non-virtualized environments. A plurality of data collection components in a computing environment can include a plurality of virtual machines running on the one or more microprocessors, wherein the plurality of virtual machines are adapted to be deployed with services and applications. Each data collection component operates to use one or more data structures to communicate with a data consumer, wherein each data structure describes metrics to be collected by said data collection component and is capable of containing collected metric values.

Abstract: A method and a gateway for extending a network are disclosed. A method by which a gateway extends an EtherCAT network to a wireless network according to an embodiment of the invention includes: receiving first data from the EtherCAT network and converting the first data by a protocol conversion to second data suitable for the wireless network, and transmitting the converted second data to the wireless network, where the transmitting of the converted second data may include reducing the difference in communication speed between the EtherCAT network and the wireless network by using an internal buffer.

Abstract: The present invention discloses a method of to generate transaction ID(s) in a bus interconnection design. An encoding table for each slave can be derived by calculating all possible transactions from all the masters to the slave so as to determine the minimum width of the transaction ID received by the slave in the interconnecting bus design, thereby avoiding the routing congestion in the interconnecting bus.

Abstract: A method of operating a module is disclosed. The method includes determining if a voltage between a power connection and a ground connection exceeds a predetermined threshold and if so determined then setting a module communication address to a first address, responding to a first serial communication received via the serial communication connection addressed to the module communication address, and not responding to a second serial communication received via the serial communication connection addressed to a different address than the module communication address. Other methods and devices are disclosed.

Abstract: A network system includes a first data source device with a primary interface and one or more second data source devices with a secondary interface disposed in electrical communication with the first data source device. A common data source device communicates with the first data source device and the second data source device(s). A serial string with a backbone is electrically connected to the primary interface and to the secondary interface. At least one endpoint device is electrically connected to the backbone via an endpoint interface. The primary interface is constructed and arranged initially as a master communication source for the serial string. The secondary interface is constructed and arranged to monitor messages transmitted by the primary interface and to take over as the master communication source if the secondary interface does not detect messages from the primary interface after a predetermined amount of time.

Abstract: The present disclosure provides an improved point-to-point serial peripheral interface, a system comprising an improved point-to-point serial peripheral interface, and a method for use in a system comprising an improved point-to-point serial peripheral interface. A master comprises a SPI initiating port. Each slave comprises at least one SPI receiving port and at least one SPI forwarding port. The master provides a set of SPI signals to the SPI receiving port of the first slave in the chain, and the entire SPI signals are forwarded via the SPI forwarding port of each of the slaves until the SPI transaction reaches a target slave, which is identified by an in-band device addressing mechanism.