Abstract: A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an array of memory cells, addressing circuitry used to address the cells and an address storage circuit which stores a local address unique to each of the memory devices. The local addresses are sequentially assigned to the memory devices by selecting a first one of the devices and forwarding an address assign command to the selected device. A command decoder, having detected the address assign command, will permit a local address placed on the bus by the controller to be loaded into the selected memory device. This sequence will continue until all of the memory devices have been assigned local addresses at which time the memory devices can be accessed to perform memory read, program, erase and other operations.

Abstract: A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masers each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention.

Abstract: A computer system may include a processor, at least one memory coupled to the processor and having a plurality of scattered memory locations each having a pointer associated therewith, and a receiver interface circuit coupled to the at least one memory. The receiver interface circuit may include a scatter pointer queue for storing available pointers corresponding to available scattered memory locations. The scatter pointer queue may also store unavailable pointers corresponding to unavailable scattered memory locations. The receiver interface circuit may also include a receiver for receiving the data and writing the received data to the available scattered memory locations based upon the available pointers in the scatter pointer queue.

Abstract: A master entity is capable of broadcasting commands to a plurality of three-state-selection machine slaves. Transitions from one state to another are effected on instruction from commands in a sequence of commands broadcast from the master. Slaves move to another state when they satisfy a primitive condition specified in the command. By moving slaves among the three sets, a desired subset of slaves can be isolated in one of the sets. This desired subset of slaves then can be moved to one of the states that is unaffected by commands that cause the selection of other desirable subsets of slaves.

Abstract: The present relief module equipped random access memory avoids the need for enforced idle cycles for the processors, thereby enabling the State Machine to operate at its maximum speed. This relief module equipped random access memory also enables the Central Processing Unit to access the data in the single-port Random Access Memory as required to read and write the data contained therein. This is accomplished by the addition of a single-port Random Access Memory module to the plurality of Random Access Memory modules that are typically specified for a particular application. The extra Random Access Memory module alternates its output with each of the others of the plurality of Random Access Memory modules, on a sequential basis, thereby providing effectively extra clock cycles for each Random Access Memory module.

Abstract: To ensure fair access to upstream trunk bandwidth among a plurality of interface units, a plurality of queues is provided in a first unit. One of the queues is associated with the first interface unit. Each of the remaining queues is associated with one of a plurality of second interface units. Local data is received by the first interface unit and forwarded to the associated queue. Data received from a second, subtended interface unit is forwarded to a queue which associated with the second interface unit. Data is then issued from the queues according to a fairness algorithm. A unique identifier is assigned to each interface unit. Associating a queue with an interface unit is done by associating the queue with the respective interface unit's identifier. In each interface unit, local data is tagged with the instant interface unit's identifier, and received data is forwarded to a queue according to the data's tag.

Abstract: An arbitration circuit and a data processing system which ensure fair bus access are provided. An arbitration circuit (1) has a priority check block (21) and a round robin block (22). The priority check block (21) checks pieces of priority information provided from processors, specifies a processor that is presenting priority information with the highest priority, i.e. a processor with the highest priority level, and outputs the result of the check (CHK) to the round robin block (22). The round robin block (22), holding the results of the previous arbitration process, generates and outputs a processor selecting signal (SE) on the basis of the priority check result (CHK) and a round robin order generated from the previous results.

Abstract: The present invention provides a system and method for prioritizing, managing, and customizing the allocation and selection of items in a real-time basis in accordance with real-time assigned rules, attributes and parameters.

Abstract: A method in a computing system (100) includes the steps of enqueuing items in a functional queue prioritized according to sort criteria (132), modifying the sort criteria (132) while the functional queue contains the enqued items, and re-prioritizing the enqued items in the functional queue according to the modified sort criteria (132). The computing system (100) includes a set of functions (122) that operate on a queue data structure (130) to maintain enqued items prioritized in the queue data structure (130) after changes in the sort criteria (132). The set of functions (122) operate with an arbitrary number of sort criteria (132) and with arbitrary values for the sort criteria (132).

Abstract: A method of respectively reading and writing data to and from a plurality of physical disk units in response to I/O requests from a host computing system includes establishing a logical disk group having a number of logical disk elements, mapping each of the logical disk elements to corresponding physical disk units, receiving from the host computing system an I/O request for data to select a one of the number of logical disk elements, accessing the physical disk unit corresponding to the selected one logical disk to access for the data, and transferring the accessed data to the host computing system.

Abstract: A multiprocessor digital amplifier system is disclosed. A first processor is configured to decode a digital signal from a digital signal source. A second processor configured to provide control signals to the first processor. An expansion unit for communicating instructions and data between the processors and a memory device has a first port coupled to the first processor and a second port coupled to the second processor. The expansion unit includes a state generator with circuitry for selecting one of the first and second ports for receiving a memory device access grant. The first and second ports may be granted access in accordance with a selected arbitration protocol. A duration of the memory device access grant selectably constitutes one of a preselected number of accesses and a preselected timeslice. An amplifier amplifies the decoded digital signal from the first processor.

Abstract: Method and means to provide a mechanism by which a hypervisor can permit a real machine to interpretively execute certain I/O instructions independently of the value of an I-bit in the subchannel. This is necessary as the I-bit covers all I/O instructions that can be interpretively executed; however, there can be instances where the hypervisor cannot allow the interpretive execution of other I/O instructions but can permit the interpretive execution of the SIGA instruction.

Abstract: A multi-processing method, system and apparatus having a processor, a request order key issuer connected to the processor which may issue an request order key to a task to be performed by the processor. A resource access order provider may be connected to the processor and may issue access order values to a task in relation to the task's request order key.

Abstract: An arbiter apparatus for selecting an agent to use a shared resource such as memory. A normal round robin list is utilized in the selection process during boot operation. During the initialization process, a dynamic list is generated in accordance with system requirements. The dynamic list selection process may take any of several forms. In a first mode, it may select only priority listed agents, any one of which may be repeated during a given cycle of selection. In a second mode, it may select a designated buddy agent when the selected priority agent is idle. In either mode, and in accordance with a set of priority selection rules, one or more lowest priority default agents may be given access when the designated higher priority agents for a given list entry slot are idle.

Abstract: A method of adjusting an access sequencing scheme for a number of PCI (Peripheral Component Interconnect) compliant units coupled to a PCI bus system on a computer system. These PCI-compliant units are associated respectively with a set of request signals that allow these PCI-compliant units to request the use of the PCI bus system for data transfer. The access sequencing scheme includes a first-layer access sequence loop and a second-layer access sequence loop, with the first-layer access sequence loop having a higher priority over the second-layer access sequence loop The request signals are assigned to either the first-layer access sequence loop or the second-layer access sequence loop in a predetermined manner. The user can change the assignment of a certian request signal from one loop to the other through PC's BIOS (Basic Input/Output System), so as to allow the associated PCI-compliant unit to have a higher priority level to the use of the PCI bus system.

Abstract: The present invention provides round-robin arbitration between requests for access to a shared resource such as a data bus (7), shared by a plurality of hardware modules. A central counter (1) provides a count state bus (3) with cyclically altered count states. In each hardware module, the count state on the bus (3) is compared (4) with a count state associated with the hardware module. The output from the comparator (4) is used to enable the transmission of a request signal R to the central counter (1) and the transmission of a grant signal Gi to the hardware module. The request signal R disables the clock signal C to the counter (1) and the grant signal Gi grants access to the shared resource (7) from the hardware module. When the hardware module terminates its access to the resource (7) it deactivates the request signal R and the counter resumes cyclical counting. Hereby a simple arbitration of round-robin type is provided using simple logic gates and a counter.

Abstract: Methods and structure for enhanced bus arbitration providing a hybrid arbitration technique combining priority-based arbitration with round-robin arbitration within a priority level with improved fairness for all devices participating the a round-robin arbitration at a particular priority level. In particular, the invention provides a state retention technique and structure such that the present state of round-robin arbitration at each priority level is saved and restored when a higher priority master device interrupts the round-robin arbitration at a lower level. The restoration of saved state information allows the round-robin arbitration at a lower priority to resume at the saved state to thereby improve fairness of arbitration among devices at a given priority level.

Abstract: Data transfer between a master node (300) and plural memory nodes (301-308) follows a synchronous fixed latency loop bus (255). Each memory node includes bus interface (311-318) which passes command, write data, address and read data to a next memory node in the loop. Each memory node performs a read from its memory at the specified address if a read command is directed to it. Each memory node performs a write to its memory at the specified address if a write command is directed to it. This configuration provides a fixed latency between the issue of a read command and the return of the read data no matter which memory node is accessed. This configuration prevents collision of returning read data. This configuration retains the issued read and write order preserving proper function for read/write and write/read command pairs. This configuration provides fixed loading to each stage regardless of the number of memory nodes. Thus the design of large systems operating at high speeds is simplified.

Abstract: A method, system and circuit for performing a round robin arbitration, which includes an input operable to receive a plurality of requests, a conditional request masking logic to selectively send the plurality of requests to a priority encoder, a priority encoder to output a request from the selected plurality of requests from the conditional request masking logic for servicing, and a storage clement to store the most recently serviced request. Wherein the conditional request masking logic sends any request from the plurality of requests that has a lower priority according to said priority encoder than the most recently serviced request if such a request exists, otherwise all requests are sent to the priority encoder.

Abstract: A DMA transfer device transfers data from a first region to a second region in a memory allowing high-speed page access. The DMA transfer device includes: a first detecting unit for detecting a plurality of read areas that form the first region, each read area being located between page boundaries; a second detecting unit for detecting a plurality of write areas that form the second region, each write area being located between page boundaries; and an access unit for performing high-speed page access to each of the read areas and each of the write areas.

Abstract: A computer system module includes a system management controller to negotiate with other system management controllers to determine the controller's initial operational state. In an embodiment, negotiation with other system management controllers is based at least in part on one of controller capability, user configured preference, module type, and geographical address.

Abstract: Round robin arbitration system includes a first round robin arbitration module and a second round robin arbitration module. The first round robin arbitration module has a first bit width. It is configured to partition a plurality of requests into a plurality of blocks of requests, to select a block having one or more active requests using round robin arbitration, and to generate a first index corresponding to the selected block. The second round robin arbitration module has a second bit width. It is configured to store each request of the selected block, to select each active request of the selected block using round robin arbitration, to generate a second index corresponding to the selected active request, and to generate a first signal for synchronizing operation of the first and second modules. The round robin arbitration system has a bit width that a product of the first and second bit widths.

Abstract: A method and apparatus for arbitrating access to a memory, which has a plurality of banks. The method includes arbitrating with a plurality of processors. Each processor is associated with one of a plurality of data ports and has a plurality of arbitration cycles, including a current cycle and a most recent cycle preceding the current cycle. Each processor receives memory access requests from all of the data ports, wherein each memory access request is associated with one of the memory banks. Each processor selectively grants the data port associated with that processor access to the memory for the current cycle based on the banks associated with the memory access requests of each data port, the data port that was granted access to the memory during the preceding cycle, and the memory bank that was accessed during the preceding cycle.

Abstract: A mixed rotative and weighted arbiter for arbitrating the priority of request signals R1-Rn supplied from a plurality of devices is disclosed. The arbiter is composed of a token circuit which delivers a token vector having one position set active. The token vector as well as the plurality of request signals are input to a rotative arbitration circuit. The rotative arbitration circuit processes a round robin algorithm to output a rotative request vector having input requests ordered from a higher to a lower priority configuration according to the active position of the token vector. The arbiter further comprises a weighted arbitration circuit connected to the output of the rotative arbitration circuit for generating a weighted request vector determining a linear priority configuration of the rotative request vector.

Abstract: An apparatus and a method of arbitrating access to a common bus, for a first set of modules included in a message transmission system, are disclosed. Using the apparatus and method of the present invention, each module is able to send an access requesting signal to an access arbiter, only after its predetermined standby period is expired. The method includes setting a standby period of each module, identifying a second set of modules whose standby periods are determined to be expired, and allowing each of the second set of modules to send an access requesting signal. Therefore, each module of the system can avoid any message traffic congestion and, consequently, the stability of the whole system can be greatly enhanced.

Abstract: In the context of a bus-mastering system, a device selector selects the device to control the bus by assigning “combined” priority values to the devices and selecting the device with the highest combined-priority value. The combined-priority values include relatively high-significance device-specific values and relatively low-significance arbitrary-rank values. At any given time, no two devices share the same arbitrary-rank values, and thus cannot share combined-priority values. Thus, there are no unresolved selections due to equal priorities. In accordance with the present invention, the arbitrary-rank values are varied in a round-robin fashion to minimize the bias inherent in conventional schemes using a priority encoder. This makes the device selection process conform better to the device-specific values, which are presumable selected to optimize system performance.

Abstract: A method and apparatus for bus arbitration wherein each bus agent is assigned a weight that governs the percentage of bandwidth allocated to the agent. In addition, each bus agent may also raise the priority of its request based on the amount of time that agent's request has not been serviced. Specifically, the waiting period for the agent is selected so that the agent would be guaranteed access to the bus such that a worst case latency constraint is satisfied. Finally, the arbitration scheme of the present invention can be split into multiple levels of hierarchy, such that when an agent wins arbitration at one level, it is passed to the next higher level where it competes with other agents for bus access.

Abstract: A method of bus priority arbitration is disclosed. In a structure that comprises a bus and a plurality of peripheral devices, each comprising a master, a request from each of the master is responded to according to a predefined orderly rotation. When a data for one of the peripheral devices is ready, the response to the request of each of the master according to the predefined orderly rotation is stopped, and the highest priority is attributed to the peripheral device which data is ready for using the bus. The data transfer then is firstly performed.

Abstract: A method and apparatus for exchanging data in a network computing system having a main storage capable of connecting to at least one application server and an interface element with at least one adapter capable of establishing processing communication with at least one application user(s). A state change signalling protocol is used for transfer of data between the main storage and said adapter. In addition a queuing mechanism is established in the main storage having a plurality of queues each with a plurality of buffers. Some of these queues are dedicated to be input and others as output queues. By applying the protocol each input and output data buffer is associated with each of the active input and output queues. In this manner the input and output buffers are managed by placing the buffers into various states which are maintained in a special location that is set aside and is associated with each buffer.

Abstract: A method and apparatus for managing a log of information in a computer system including a host computer and a storage system that stores data accessed by the host computer. The computer system includes a plurality of logical volumes of data that are visible to the host and the storage system and that are perceived by the host computer as comprising a plurality of raw storage devices. The storage system includes at least one physical storage device and at least one mapping layer that maps the logical volumes to the physical storage device. In one aspect of the invention, the log includes information concerning at least one I/O operation. The information includes a first component relating to aspects of the I/O operation controlled by the host computer and a second component relating to aspects of the I/O operation controlled by the storage system. In one aspect, the host computer stores the log which includes information relating to aspects of the I/O operation controlled by the intelligent storage system.

Abstract: An arbitrator provided to a processor element requests the utilization of a bus sends a bus request signal and a bus request value according to a priority level of the processor element to the bus, determines the priority of utilizing the bus in accordance with utilizing situation of the bus and the priority level of the processor element. Since a common bus arbitrating circuit connected to the bus watches the bus and determines a processor element to utilize the bus according to the utilizing situation of the bus and the priority level of the processor elements requesting the utilization of the bus, the bus arbitration can be performed with high speed, and an increase of communication speed between the processor elements through a single bus can be realized.

Abstract: Apparatus for arbitrating between requests from a plurality of sources for access to a shared resource, the apparatus comprising: a register means having a plurality of stages, each stage containing a designation of one of said sources, a plurality of stages containing a designation of the same source, logic means for accessing the register stages according to a priority scheme and for comparing the designation in each stage with requests for access, and granting access according to the match between the highest priority source designation and a memory request, and means for changing the contents of the register means subsequent to access grant.

Abstract: A bus arbitration system is described which includes an arbitrator for controlling accesses to a memory bus by a plurality of memory users in response to requests made by those memory users. Each memory user reads the address if a current access to memory and generates a same-address-set signal when the address of the last access by that memory user lies in the same set as the address of the current access. The arbitrator holds for each memory user a predetermined number of accesses which are permitted by that memory user during an access span, and, responsive to a request, grants up to that predetermined number of accesses provided that the same-address-set signal is asserted.

Abstract: A system and method for prioritizing the delivery of information transfer requests using a least-recently-serviced rotational priority technique in a data processing system having one or more requesters to supply the information transfer requests. Active requesters have currently pending information transfer requests, and non-active requesters have no currently pending information transfer requests. Transfer authorization is granted to an information transfer request associated with an active requester that is currently assigned to the highest priority level in a range of priority levels. Each of the active and non-active requesters that have a priority level less than the priority level of the active requester that was granted the transfer have their priority levels incremented, while the non-active requesters having a priority level greater than the priority level of the active requester that was granted the transfer is maintained at its current priority level.

Abstract: A system and method of distributing telephone and passenger service signals from a zone interface unit to a plurality of seat electronic units in an in-flight entertainment system is described. The method uses a master/slave arrangement in which multiplexed telephone and passenger service signals are transmitted over a bus to the receiving seat electronic units.

Abstract: Computer-based devices, whether initiators or targets, are assured access to a bus having a fixed priority arbitration scheme (such as a SCSI bus) by assigning to each initiator a “fair share” of the bus bandwidth. This share is defined as a number of bytes per a unit of time such as a time period. The shares together total a fraction of the total bus bandwidth, with a margin of bus bandwidth left unassigned. To prevent initiator starvation, each initiator monitors its bus requests to determine if it is being prevented by higher-priority initiators from using its assigned share of the bandwidth. If not, the initiator periodically pings each higher-priority initiator to indicate that it is not being starved. So long as a higher-priority initiator continues to receive pings from all lower-priority initiators, the higher-priority initiator can continue to use as much bandwidth as it needs.

Abstract: A cascaded multimedia arbiter and method for arbitrating access to a shared multimedia memory, which is used to store multiple frame buffers for multiple monitors. Other buffers for multimedia agents such as for audio, camera input, digital-versatile disk (DVD) input, and three dimensional (3D) rendering share the same memory. The shared memory allows flexible memory allocation as graphics, audio, and multimedia modes change. Many real-time agents such as for graphics and audio read the memory to fill first-in-first-out (FIFO) buffers. These real-time agents are assigned a fixed slot in a round-robin arbitration. The last or final arbitration slot is used by all non-real-time agents, such as the host, 3D engine, and DVD playback. These non-real-time agents can wait, but need the most bandwidth to maximize performance. The last time slot uses a priority arbiter to grant access in a priority order to the non-real-time agents.

Abstract: A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.

Abstract: An access control system (10) for controlling access to a shared resource among a plurality of service requestors is described. When a service requestor seeks access to the shared resource, it generates a service request signal which includes its assigned unique service request priority number. The outputs of all the service requesters are applied to pipelined first and second OR-trees (75, 78) which produce an OR-ed output signal. The OR-ed output signal is then applied to an access control unit (38) which performs an arbitration protocol to determine the highest priority number. Each service requester includes a state machine which selectively applies the bits of its priority number to the OR-trees (75, 78). The use of pipelined protocol with two OR-trees (75, 78) reduces cycle consumption and permits arbitration within a single clock cycle.

Abstract: Round-robin arbitration circuit selects in clock cycle channel contending for arbitration; each arbitrated channel having channel number in sequence of channel numbers. Channel is designated as currently arbitrated; designated channel having designated number. Channels are masked from arbitration with designated channel, such that designated and unmasked channels are arbitrated to select channel. Channels having numbers sequenced after designated number are masked from arbitration, and channels having, numbers sequenced earlier than designated are also masked from arbitration. During subsequent cycle, designated channel is shifted to next channel in sequence of channel numbers by incrementing designated number. When designated number is last in sequence, designated channel is shifted to next having first number in sequence.

Abstract: The present invention is directed to a data output control device which stores input data within a queue, before outputting data to an output circuit from a queue that is storing data, so as to guarantee a minimum speed of data output, and therefore reduces processing time for the operation of selecting the output queue.

Abstract: A SCSI bus arbitration controller includes a hub to which each of the SCSI devices having access to the bus is connected. The hub includes a controller that monitors the data lines on the bus, as well as the BUSY and SELECT lines. The hub also includes a plurality of switches located between each of the devices and the data bus. For each set of device connections to a bus, the highest priority ID data line has a switch in it, as does the data line that corresponds to the ID associated with that particular device. During an initial arbitration cycle, the controller monitors the bus data lines, and determines which of the devices participate in the initial arbitration cycle. It then latches the identities of the participating devices in a register. Of the SCSI IDs of the system, the controller reserves the highest priority ID for itself.

Abstract: A scheme for arbitrating access to a data bus shared among a plurality of competing sources is provided. Each competing source is assigned an adjustable priority weighting value (PWV) which is initially set to an initial value based on the bandwidth requirements of the competing source. During arbitration, the PWVs of those competing sources requesting access to the bus are compared, and the competing source with the smallest PWV is granted access. The PWV of the competing source which was granted access to the bus is reset to its initial value and the PWV of each competing source which requested, but was denied, access is reduced by one for subsequent comparisons. The arbitration scheme of the present invention is further applied to two-level arbitration. Each competing source is classified into a competing source group, and the requests from the grouped competing sources are processed by first level arbitration. First level arbitration passes one competing source for each group to a second level arbiter.

Abstract: A data processing system is disclosed which includes a first processor having an m-byte data width, an n-byte data bus, where n is less than m, and a second processor electrically coupled to the bus which performs bus transactions utilizing n-byte packets of data. An adaptor is electrically coupled between the first processor and the bus which converts n-byte packets of data input from the bus to m-byte packets of data, and converts m-byte packets of data input from the first processor to n-byte packets of data, thereby enabling the first processor to transmit data to and receive data from the bus utilizing m-byte packets of data. In a second aspect of the present invention, a method and system are provided for arbitrating between two bus masters having disparate bus acquisition protocols. In response to a second bus master asserting a bus request when a first bus master controls the bus, control of the bus is removed from the first bus master.

Abstract: An improved data processing system and in particular an improved data processing system that more effectively manages a shared resource within a data processing system. More specifically, a method and apparatus for managing access to a shared resource between a plurality of devices simultaneously requesting access to the shared resource. The present invention implements a design that combines a priority configuration and a shifting sequential configuration. The access is controlled by an arbiter that determines access to the shared resource by granting first, to priority devices and then to the highest priority shifting sequential device requesting access within one clock cycle of a device terminating its request for access to the shared resource.

Abstract: A memory control device having a plurality of data transfer paths including a storage device group comprising a plurality of storage devices for storing data and a buffer memory group comprising multiple buffer memories for storing transferred data, dividing files into multiple blocks for storing blocks in multiple storage devices on different data transfer paths, and executing control to read data from the storage device to be output with a request from a connected terminal to the buffer memory wherein storage devices on different paths create multiple virtual storage device groups, and buffer memories create virtual buffer memory groups. The memory control device comprises a data output control for executing control in a first cycle, the data being temporarily dividedly stored in a prescribed virtual storage device group.

Abstract: A method and apparatus for controlling access to a shared memory in a network system is described. The apparatus includes at least one fast port interface circuit, each comprising a fast input port interface configured to sequentially receive data, address, and command information from a network client at a first data rate in segments of a first width. Each fast input port interface comprises a fast interface register configured to temporarily store the data and address information. Each fast input port interface further comprises a command decode circuit configured to receive the command information and, in response, sequentially store the segments of data and address information in the fast interface register until the fast interface register is full, the fast interface register further configured to be read out in parallel to the shared memory.

Abstract: An apparatus and method of assigning communication channels for transmitting data through a host bridge are provided. In a preferred embodiment, a determination is made as to whether data is being transmitted through any one of the channels. If data is not being transmitted through one the channels, that channel is designated as the transmission channel for the present data transaction. If data is being transmitted through all of the channels, a least most recently used channel is selected as the data transmission channel. If however, more than one channel is not transmitting data, the data transmission channel assignments are made among the idle channels from a lowest channel number (e.g., channel 0) to a highest channel number (e.g., channel 7) or vice versa.

Abstract: A configurable weighted round robin arbitration mechanism adapted to receive as input a vector of order N, wherein each bit in the vector represents the eligibility of a queue or other source of data to participate in the arbitration process. A bit set to `1` in the vector indicates that the corresponding queue is eligible to participate in the arbitration process. Conversely, a bit set to `0` in the vector indicates that the corresponding queue is not eligible to participate. The arbitration process of the present invention enables a user to assign each queue (which corresponds to one of the bits in the vector) an individual weight. This results in a modified vector that represents the incoming vector after being handled by the weighting process. By giving each bit in the vector a weight, the user can control the probability of each bit, i.e., queue, being selected in the arbitration process.

Abstract: A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.