Abstract: A round robin arbitration circuit arbitrating N requests has a register storing one of N values, a priority encoder selecting one of N priority patterns according to the value in the register and assigning priorities to the requests based on the selected priority pattern, thereby conducting arbitration between the requests, a circuit updating the value in the register among the N values in a predetermined order synchronously with the arbitration, and a circuit updating the value in the register among the N values in the predetermined order at regular intervals that are asynchronous with the arbitration. At the regular intervals that are asynchronous with the arbitration, a jump is made in the predetermined updating order of the values to be set in the register. Accordingly, even if live-lock occurs, it will be solved when such a jump is made to make the number of priority patterns disagree with the number of requests issued in a loop.

Abstract: A priority queue structure and algorithm for managing the structure which in most cases performs in constant time. In other words, most of the time the inventive algorithm performs its work in an amount of time that is independent on the number of priority classes or elements that exist in the queue. The queue itself consists of a linked list of elements ordered into subqueues corresponding to priority classes, with higher priority subqueues appearing earlier in the queue. An array of priority pointers contains an entry for each subqueue that points to the last element of each subqueue. Elements are removed for processing from the top of the queue. Removal takes constant time. Items are inserted into an appropriate subqueue by linking it at the end of its respective subqueue.

Abstract: Requests from CPU module units are arbitrated according to a two-level priority scheme, the first level being of a higher priority than the second level. The first level includes a specific CPU module unit, and the second level includes a predetermined sequence of values corresponding to the remaining CPU module units. During each arbitration cycle, a request from the first level CPU module is automatically granted. If the first level CPU module unit has not asserted a request, requests from the second level module units are arbitrated according to the above-mentioned predetermined sequence. The sequence value corresponding to the second level CPU module whose request was most recently granted is latched. Arbitration is then granted to the module unit corresponding to the sequence value which follows the latched value.

Abstract: The present invention is directed to providing a computer system which arbitrates control of a shared bus among plural devices included in the computer system. In accordance with the present invention, at least one of the devices is afforded a higher priority than the remaining devices, yet none of the remaining devices are effectively denied system bus access or control for extended periods of time. The present invention can therefore increase operating efficiency even as the number of devices included in the computer system is increased to achieve enhanced processing power. In addition, the present invention can provide sophisticated multimedia features, including real time signal processing, without sacrificing overall operating efficiency.

Abstract: The present invention provides for an on-chip communications method with fully distributed control combining a fully-pipelined, fixed-latency, synchronous bus with a two-level arbitration scheme where the first level of arbitration is a framed, time-division-multiplexing arbitration scheme and the second level is a fairly-allocated round-robin scheme implemented using a token-passing mechanism. Both the latency and the bandwidth allocation are software programmable in real-time operation of the system. The present invention also provides for a communications system where access to a shared resource is controlled by the above communications protocol. Access to and from the shared resource from the subsystem is through a bus interface module. The bus interface modules provide a level of indirection between the subsystem to be connected and the shared resource. This allows the decoupling of system performance requirements from subsystem requirements. Communication over the bus is fully memory mapped.

Abstract: At least two clusters of CPUs are present in a multiprocessor computer system. Each CPU cluster has a given number of CPUs, each CPU having an associated ID such as an ID number. An additional ID number, not associated with a CPU in the same cluster, is associated with the opposite CPU cluster that appears to the original cluster as a "phantom" processor. A round-robin bus arbitration scheme allows ordered ownership of a common bus within a first cluster until the ID reaches the "phantom" processor, at which time bus ownership passes to a CPU in the second cluster. This arrangement is preferably symmetric, so that when a CPU from the first cluster requests ownership of the bus, it is granted bus ownership by virtue of the first cluster's appearance to the second cluster as a "phantom" CPU.

Abstract: One aspect of the invention relates to a method for arbitrating simultaneous bus requests in a multiprocessor system having a plurality of devices which are coupled to a shared bus. In one version of the invention, the method includes the steps of receiving a plurality of bus requests from the devices; determining a device having the highest priority; determining whether the device having the highest priority is requesting the bus; granting bus access to the device having the highest priority if the device having the highest priority is requesting the bus; sequentially searching, beginning from the device logically adjacent to the device having the highest priority, for a next requesting device, and granting bus access to the next requesting device if the device having the highest priority is not requesting the bus; and assigning the highest priority to the device logically adjacent to the next requesting device.