Abstract: An integrated circuit including: a bus system including a bus master connected to a bus; and a memory controller connected to the bus system and controlling a connection between the bus master and a memory, in which the bus system includes a counter counting a waiting time from a time the bus master outputs a memory access request until a time a connection between the bus master and the memory controller is established, and the memory controller controls a memory access based on the waiting time counted by the counter.

Abstract: An information processing apparatus includes a plurality of modules connected in a ring shape via a bus, and each module processes a packet flowing in a single direction on the ring in a predetermined order. The module includes a communication unit for transmitting a packet received from a first direction in the ring via the bus to a second direction, a discrimination unit for discriminating a packet from among the packets received from the first direction as a processing packet to be processed by the module, and a processing unit which is connected with the communication unit one by one and configured to process the processing packet. The communication unit transmits the packet processed by the processing unit at an interval equivalent to processing time or more for a processing packet processed by a module in a latter stage in the predetermined order among packets transmitted by the communication unit to the second direction.

Abstract: A method for exchanging data in messages between at least two stations connected via a bus system. The messages contain the data being transmitted by the stations over the bus system, and the messages are controlled over time by a first station in such a manner that the first station repeatedly transmits a reference message containing time information of the first station over the bus system at least one specifiable time interval. The time interval is subdivided as a basic cycle into time windows of specifiable length, and the messages are transmitted in the time windows. When data is exchanged, a pause period of variable duration is provided at the end of at least one basic cycle, by which a time change of the beginning of the basic cycle is corrected by adaptation of the duration of the pause period.

Abstract: In a WUSB communication environment in which isochronous transfer cannot be used, priority communication is performed in units of devices. A WUSB host manages assigning of a band of reserved one or more MASs in a superframe by using a device information management table, in which device information entries each describing, in a bitmap format, a MAS for which a transaction can be executed are each provided for a WUSB device. The WUSB host assigns at least some of the reserved one or more MASs only to a particular WUSB device. Only a WUSB device marked in a corresponding device information entry serves as a target of transaction scheduling.

Abstract: A multimode communication integrated circuit comprising baseband processing circuitry with a shared radio interface. Various aspects of the present invention may comprise a processor module adapted to perform various processing (e.g., baseband processing) in support of multimode communications. A first radio module may be communicatively coupled to the processor module through a common communication interface. A second radio module may also be communicatively coupled to the processor module through the common communication interface. The common communication interface may, for example, be adapted to communicate information over a communication bus that is shared between the processor module and a plurality of radio modules (e.g., the first and second radio modules).

Abstract: Method for rapidly detecting identifier (ID) of tags, by radio frequency identification (RFID) reader in communication system that includes RFID reader and at least two tags communicating with RFID reader, is provided. RFID reader generates a prefix when IDs contained in at least two messages received collide with each other, prefix including a first colliding bit, which is set to ‘0’ or ‘1’, from high-order bits and non-colliding high-order bits. RFID reader sends a first message containing information that requests transmission of an assigned ID in a preset transmission period when the bits of the generated prefix match bits corresponding to the prefix, in the assigned ID. Tags receive a first message that contains a prefix including at least one bit, and sends a second message containing an assigned ID during a preset transmission period when the bits of the prefix match bits corresponding to the prefix, in assigned ID.

Abstract: Various methods and processing systems are disclosed which include sending and receiving components communicating over a bus having first and second channels. The sending component may broadcast on the first channel a plurality of read and write address locations, a plurality of transfer qualifiers, and write data. The receiving component may store the write data broadcast on the first channel at the receiving component based on the write address locations and a first portion of the transfer qualifiers. The receiving component may also retrieve read data from the receiving component based on the read address locations and a second portion of the transfer qualifiers, and broadcast the retrieved read data on the second channel.

Abstract: A priority control value, which is smaller as the priority of access by each of requesters is higher, decreases with the lapse of time when an access request is issued. When the access is completed, the priority control value increases by a priority decrease value (PERIOD). When there is no access request, the priority control value decreases to a reference priority value (TMIN) and is then maintained at the reference priority value. Access permission is given to the one of the requesters issuing requests which has the smallest priority control value. As a result, proper arbitration is performed at a high speed with a simple hardware configuration.

Abstract: For every sampling period of a DSP 100, a timing generator 200 requests a CPU 300 to release a bus and provides a DSP 100 access time period to make an external memory 400 access the DSP 100 by occupying the bus released according to the request. In the DSP 100, during the DSP access time period, a memory interface section 11 executes read/write processing in which waveform data read from the external memory 400 is stored in an internal memory 12 and waveform data read from the internal memory 12 is written into the external memory 400 according to the command stored in an access command memory 10. At the same time, an operation section 13 executes operation processing by using the waveform data stored in the internal memory 12 independently of the read/write processing.

Abstract: In a method for carrying out cyclic and conflict-free data communication for the subscribers of a data bus, which transmits data in non-overlapping time periods within a subscriber cycle interval and processes jobs, and whose fixed transmission time slots in a planning phase are allocated within the subscriber cycle interval, the task processing for a subscriber is carried out exclusively within an application time interval within the subscriber cycle interval, and in the planning phase the transmission time slots for each subscriber, within a transmission time interval which is disjunct with respect to the application time interval, are selected within the subscriber cycle interval, and the selected transmission time slots are communicated to the subscribers in a subsequent initializing phase.

Abstract: In a CAN system, an arrangement is incorporated for making possible more efficient utilization of available band-width on the system's bus connection between, from and/or to modules incorporated in the system and/or reduction of accuracy requirements for clock functions utilized in the system. The system operates with communication on the bus connection that is in accordance with rules set up in the system and constitutes a combination of event-driven and time-controlled communication functions. The said functions are, together with a rule change in the time-controlled communication function, arranged to achieve the said making more efficient and/or reduction. The rule change is arranged to bring about deliberate collisions between messages appearing on the bus connection. In this way, the bandwidth utilization, the clock function and the system's general construction and function can be simplified according to the requirements imposed.

Abstract: A scheduler provided according to an aspect of the present invention provides higher priority for data units in a low priority queue upon occurrence of a starvation condition, and to packets in a high priority queue otherwise. The scheduler permits retransmission of a data unit in the lower priority queue when in the starvation condition, but clears the starvation condition when the data unit is retransmitted a pre-specified number of times. As a result, the data units in the higher priority queue would continue to be processed, thereby avoiding a deadlock at least in certain situations.

Abstract: Systems, apparatuses and methods for timing access to a shared communications bus by a plurality of devices. Each of a plurality of nodes is successively provided an opportunity to gain access to a shared bus according to a time slot allocation referenced from a time reference. The successive time slot allocation occurs until one of the nodes has a message to send via the shared bus. The node that has the message to send transmits a frame onto the bus. A new time reference is established at each of the nodes based on an indication provided by the transmitted frame, whereby each of the nodes can then be afforded a new opportunity to gain access to the shared bus according to the time slot allocation referenced from the new time reference.

Abstract: A digital processing system employing multiple arbiters, all designed to allocate a resource to a same entity in response to a same condition. In an embodiment, the entities needing the resource may send a request to all the arbiters, and the specific entity to which the resource is allocated, receives indication of the allocation from a closest one of the arbiters. As a result, the latency in receipt of indication of allocation may be reduced. The features are described in the context of a bus as a resource.

Abstract: An apparatus and method for granting one or more requesting entities access to a resource in a predetermined time interval. The apparatus includes a first circuit receiving one or more request signals, and implementing logic for assigning a priority to the one or more request signals, and, generating a set of first_request signals based on the priorities assigned. One or more priority select circuits for receiving the set of first_request signals and generating corresponding one or more fixed grant signals representing one or more highest priority request signals when asserted during the predetermined time interval.

Abstract: Methods and systems for managing Serial Advanced Technology Attachment (“SATA”) affiliation transfers between a requesting controller and a granting controller of a storage system. After receiving an affiliation request from the requesting controller, the granting controller queries a number of commands that are queued locally at the granting controller. The granting controller grants the affiliation to the requesting controller after a period of time that is determined based on the queried number of commands that are queue locally.

Abstract: A system for providing bidirectional communication for a data bus includes a datalink interface component configured to interface into a datalink. The datalink interface component is configured to operate in at least one of a first data communication state, a second data communication state, and a wholly inactive state. The first data communication state causes a first data communication component to communicate via the datalink interface and a second data communication component to be in an inactive state. The second data communication state causes the first data communication component to exist in an inactive state and the second communication component to communicate via the datalink interface. The wholly inactive state causes the first and second data communication components to exist in the inactive state.

Abstract: A bus system includes a bus and first and second bus interfaces, along with at least one data line that transmits data between the first and second bus interfaces. The bus system also includes first and second bus control devices, where the first bus control device is allocated to the first bus interface and the second bus control device is allocated to the second bus interface. First and second signaling lines signal a respective state of each of the first and second bus control devices and a third signaling line signals an exchange of data. A clock line is included that synchronizes the bus system by a clock. The first and second bus control devices each generate a control word having control information that relates to the data transmitted on the at least one data line.

Abstract: A resource allocation method for performing resource competition between protocols based on a protocol in a home network environment using multiple protocols is provided. In the resource allocation method, a request of using a resource is received from an external device. An AIFS value is allocated according to a data type of the resource requested from the device. Then, the resource is not provided to the device for an AIFS period. After passing the period of the AIFS value, a back-off timer period is entered. In the back-off timer period, an application protocol of the external device requesting the resource is identified, and an idle time value is allocated according to a type of the identified protocol. Then, a corresponding resource is provided to the first device coming out of the allocated idle time.

Abstract: A storage controller receives an interrupt control directive from a host. The storage controller generates a first plurality of interrupts, in response to access requests received from the host for at least one storage device coupled to the storage controller, wherein the first plurality of interrupts indicates whether access to the at least one storage device is allowed to the host. The storage controller generates a second plurality of interrupts, wherein the second plurality of interrupts comprises unsolicited interrupts for the host that are different from the first plurality of interrupts. The storage controller controls how many of the first plurality of interrupts and how many of the second plurality interrupts to send to the host, based on the received interrupt control directive.

Abstract: A storage controller receives an interrupt control directive from a host. The storage controller generates a first plurality of interrupts, in response to access requests received from the host for at least one storage device coupled to the storage controller, wherein the first plurality of interrupts indicates whether access to the at least one storage device is allowed to the host. The storage controller generates a second plurality of interrupts, wherein the second plurality of interrupts comprises unsolicited interrupts for the host that are different from the first plurality of interrupts. The storage controller controls how many of the first plurality of interrupts and how many of the second plurality interrupts to send to the host, based on the received interrupt control directive.

Abstract: To provide a multi-core LSI capable of improving the stability of operation. A multi-core LSI comprises a plurality of CPUs coupled to a first shared bus, one or more modules coupled to a second shared bus, a shared bus controller coupled between the first shared bus and the second shared bus, for arbitrating an access to the module(s) by the CPUs, and a system controller that monitors whether or not a response signal to an access request signal of the CPUs is output from module to be accessed, wherein the system controller outputs a pseudo response signal to the first shared bus via the shared bus controller to terminate the access by the CPU while accessing if the response signal is not output from the module to be accessed after the access request signal is output to the second shared bus from the shared bus controller and before a predetermined time elapses.

Abstract: A fine-grained bandwidth control arbiter manages the shared bus usage of the requests of the masters which have real-time and/or bandwidth requirements, moreover, the masters are preset a ticket respectively. The arbiter consists of three components, a real-time handler, a bandwidth regulator, and a lottery manager with tuned weight. The real-time handler grants the most urgent request. The bandwidth regulator handles the bandwidth allocation and blocks the requests of masters that have met the bandwidth requirement. The lottery manager with tuned weight stochastically grants one of the contending masters according to the ticket assignment.

Abstract: A method of operating a processor bus, with which a central unit (processor) makes accesses to various peripheral units, is described. The processor bus has the ability to change the order of the accesses as a function of the operating state of the peripheral units, and the peripheral units can either reject or delay the access.

Abstract: Methods and systems for working around the timeout limitations of physical interface standards for detachable modules. By use of dummy data blocks to keep the bus active, the bus timeout requirements (in either direction) can be spoofed, to thereby permit more complex processing operations to be performed, which otherwise might not fit reliably within the timeout period. This permits a memory system to execute applications or process data for a time period that may exceed the bus timeout of a particular specification. A controller in the memory system deasserts the ready signal and holds the bus connecting the computer system in a “busy” state until the memory system is about to timeout. During a write operation, the controller receives dummy data blocks from the computer system before the write bus timeout period expires, causing the bus timeout period to be reset.

Abstract: A method and apparatus for traffic arbitration in a system are provided. In the system, a first module operating in a first protocol and a second module operating in a second protocol share one communication channel. An arbitration circuit schedules medium accesses thereof, in which a quota table maintains a utilization value updated in accordance with the amount of time slots consumed by a particular traffic type, and a time counter periodically resets the utilization value to a default value. When the arbitration circuit receives a request for medium access of the particular traffic type, the arbitration circuit grants the request according to the utilization value, such that the first module or the second module are not activated at the same time.

Abstract: A system and method for selective preclusion of bus access requests are disclosed. In an embodiment, a method includes determining a bus unit access setting at a logic circuit of a processor. The method also includes selectively precluding a bus unit access request based on the bus unit access setting.

Abstract: The present invention relates to a data processing system is provided which comprises at least one first processing unit (CPU), at least one second processing unit (PU), at least one memory module (MEM), and an interconnect. The memory module (MEM) serves to store data from said at least one first and second processing unit (CPU, PU). The interconnecting means couples the memory module (MEM) to the first and second processing units (CPU, PU). In addition, an arbitration unit (AU.) is provided for performing the arbitration to the memory module (MEM) of the first and second processing units (CPU, PU). The arbitration is performed on a time window basis. A first access time during which the second processing unit (PU) has accessed the memory module and a second access time which is still required by the second processing unit (PU) to complete its processing are monitored during a predefined time window by the arbitration unit (AU).

Abstract: An area efficient system that includes a first circuit to synchronize a clock signal and a data signal and a data retaining and processing device to receive data from said data bus to thereby generate a status signal indicating the receipt of data by said area efficient system; a reference bus address and said data bus. The system also includes a device to compare the reference bus address with the content of memory for generating an address matching signal and a control signal generator to govern the data write signal generation for said shifting means. The system further includes a sequencer to read and write data from/to said data retaining and processing device in a plurality of subcycles for efficiently accessing storage buffers and a direct storage access controlling means for generating interrupt signals and access request signals.

Abstract: A design structure for piggybacking multiple data tenures on a single data bus grant to achieve higher bus utilization is disclosed. In one embodiment of the design structure, a method in a computer-aided design system includes a source device sending a request for a bus grant to deliver data to a data bus connecting a source device and a destination device. The device receives the bus grant and logic within the device determines whether the bandwidth of the data bus allocated to the bus grant will be filled by the data. If the bandwidth of the data bus allocated to the bus grant will not be filled by the data, the device appends additional data to the first data and delivers the combined data to the data bus during the bus grant for the first data. When the bandwidth of the data bus allocated to the bus grant will be filled by the first data, the device delivers only the first data to the data bus during the bus grant.

Abstract: An I/O interface, compatible with industry standards, for interfacing a host to a peripheral device. The interface includes a clock signal, a bus, an address latch enable signal, a peripheral device ready signal, a command signal, a device selected backoff signal, and a reset signal, resulting in an I/O interface capable of ISA-compatible operation with only 22 pins. Address, data, command, interrupt request, and DMA request information are communicated between the host and the peripheral device via a single bus by multiplexing the information on the bus using phasing techniques.

Abstract: A method and apparatus are disclosed for performing dynamic arbitration of memory accesses by a CPU and at least one bus master interface module based on, at least in part, monitoring a CPU throttle control signal and monitoring CPU power and performance states, and making decisions based on the monitored parameters. Bus master memory access break events and memory read and write accesses are also monitored as part of the arbitration process in accordance with certain embodiments of the present invention. An arbitration (ARB) module performs the dynamic arbitration. A CPU throttle control module generates the CPU throttle control signal, indicating when the CPU is idle, and also monitors and outputs the CPU power and performance states. A memory controller (MC) module controls accesses to the memory subsystem based on, at least in part, the dynamic arbitration performed by the dynamic arbitration module.

Abstract: An electronic apparatus includes a memory, first and second bus masters, a counting unit and a control unit. The first and second bus masters are capable of accessing the memory. The counting unit counts an amount of addresses reserved by the second bus master for accessing the memory. The control unit controls to avoid permitting a request made by the second bus master if a value counted by the counting unit becomes larger than a first threshold value, until the value counted by the counting unit becomes smaller than a second threshold value. The request made by the second bus master is used to reserve addresses of the memory, and the second threshold value is smaller than the first threshold value.

Abstract: An I/O-request processing system which is capable of reducing the maximum value of the time required until the I/O request of each external device is registered. An I/O-request receiving section (501) receives an I/O request issued from an external device (600). A process-information storage section (510) stores an I/O-request delay time (512) for each external device (600). A priority-process judgment section (520) registers the I/O request having a maximum 1o I/O-request delay time (512) among the I/O requests which have been registered into an I/O-request cue (540).

Abstract: An integrated circuit including: a bus system including a bus master connected to a bus; and a memory controller connected to the bus system and controlling a connection between the bus master and a memory, in which the bus system includes a counter counting a waiting time from a time the bus master outputs a memory access request until a time a connection between the bus master and the memory controller is established, and the memory controller controls a memory access based on the waiting time counted by the counter.

Abstract: A bus station circuit (14) operates in an electronic system with a bus (10). The bus station determines an initial synchronization time point by detecting a synchronization signal pattern on the bus and switching to a synchronization enabled state upon detection of the synchronization signal pattern. Starting points of successive messages are determined head to tail from the end points of immediately preceding messages, when operating in the synchronization enabled state. The content of the messages is tested for validity. The bus station switches to a synchronization disabled state in response to detection of a message with invalid content. While in the synchronization disabled state, use of messages that are received is disabled in the bus station circuit. In the synchronization disabled state the bus station waits for a synchronization event to switch back to the synchronization enabled state.

Abstract: The signal integrity of a high speed heavily loaded multidrop memory bus is often degraded due the numerous impedance mismatches. The impedance mismatches causes the bus to exhibit a nonlinear frequency response, which diminishes signal integrity and limits the bandwidth of the bus. A compensating element, such as a capacitor which ties the bus to a reference plane (e.g., a ground potential), or an inductor wired in series with the bus, is located approximately midway between the memory controller and the memory slots. The use of the compensating element equalizes signal amplitudes and minimizes phase errors of signals in an interested frequency range and diminishes the amplitudes of high frequency signals which exhibit high degrees of phase error. The resulting bus structure has increased desirable harmonic content with low phase error, thereby permitting the bus to exhibit better rise time performance and permitting a higher data transfer rate.

Abstract: A method for determining a remote timeout parameter in a network comprising a link between a first bus and a third bus. The link is implemented through a first and a second bridge portal connected respectively to the first and the third bus, and is modelized as a second bus connected to the first bus and the third bus through bridges. Upon solicitation to provide its contribution to a timeout for a request subaction, the first bridge portal adds to the timeout contribution the first bridge portal's maximum request subaction processing time and either the link's maximum transmission time of half of the link's maximum transmission time, depending on the location of the destination node of the request subaction.

Abstract: An architecture for a Block RAM (BRAM) based arbiter is provided to enable a programmable logic device (PLD) to efficiently form a memory controller, or other device requiring arbitration. The PLD arbiter provides low latency with a high clock frequency, even when implementing complex arbitration, by using BRAM to minimize PLD resources required. The architecture allows multiple complex arbitration algorithms to be used by allowing the multiple algorithms to be stored in BRAM. With multiple algorithms, dynamic configurability of the arbitration can be provided without halting the arbiter by simply changing an algorithm stored in BRAM. Additionally, algorithms can by dynamically modified by writing to the BRAM. With BRAM memory used for arbitration, PLD resources that would otherwise be wasted are frees up to be used by other components of the system.

Abstract: Systems and methods for early fixed latency subtractive decoding are disclosed. The subtractive decoding device speculatively acknowledges a bus transaction within a fixed time period that is the same as the time period for positive decoding. Pipelining of a new bus transaction may therefore be accomplished each new time period. A bus transaction may be retried if no acknowledgement occurs within the fixed time period.

Abstract: A method and computer system apparatus for asynchronous data transfer between a source and sink without the use of an asynchronous control signal. includes metastability circuits, data change detection logic, a stability window delay counter, and a mux/register pair to allow for the holding of previous stable data during the transition. While the processing logic employed specifically applies to asynchronous logic, the logic can be extended to synchronous or untimed interfaces as well. Also disclosed is a programmable means to adjust the window delay.

Abstract: Provided is a simply structured multiprocessor system which equally distributes access performance for accessing a shared memory among plural master units accessing the shared memory. The multiprocessor system includes plural master units PU0 and PU1 each of which issues an access request for accessing the shared memory, a bus IF unit 4-10 which accesses a bus by a split transaction scheme and separately executes a request phase for accepting the access request; and a transfer phase for executing data transfer in response to the accepted access request. In the case where one of the master units consecutively issues plural access requests without an interval of a predetermined time period, the bus IF unit 4-10 restricts the number of consecutive transfer phase executions corresponding to the plural access requests to be not more than N.

Abstract: An integrated device for sampling data packets asserted sequentially on a system bus, including a clock input for receiving a bus clock signal, a data bus interface for receiving the data packets and for detecting at least one data strobe indicating data validity, and dynamic source synchronized sampling adjust logic. The dynamic source synchronized sampling adjust logic includes sampling logic which selects and latches each data packet in response to the data strobe and which provides latched data packets, and select logic which selects from among the latched data packets based on a read pointer. A method of sampling data packets asserted sequentially on a data bus for one or more bus clock cycles including detecting operative edges of a data strobe, selecting a data packet for each detected operative edge, and latching each selected data packet.

Abstract: A method and system for bus arbitration to be used in a system having a plurality of data handling units (110a, . . . 110d) and a shared bus (140) with a plurality of data-lines. The invention provides a method and an system to carry out the method, having steps of; receiving data transfer requests from the data handling units; selecting a set of data transfer requests the allowance of which serves a maximum number of data handling units and utilizes a maximum number of data-lines, and; allowing the data handling units that issued said selected set of data transfer requests to access said bus in a single bus cycle.

Abstract: Access to a bus is granted to one of a number of requesting communication circuits that each submitted a bus control request during a request period of an arbitration period in response to the entries in a priority table. If a requesting communication circuit has an identity and priority that match the identity and priority of a communication circuit stored in a row of the priority table that corresponds with the arbitration period, access to the bus is granted to the requesting communication circuit.

Abstract: A PCI bus time-based weighted round robin arbiter has a phase table divided into a plurality of phases. Each of the phases is assigned to one of the ports on the PCI bus. An arbiter state machine is coupled to the phase table and looks at the port assignment for the next plurality of phases, for example, 3 phases. If the arbiter determines that the next plurality of phases is assigned to a single port, that port is selected as the next bus master.

Abstract: Methods for accessing full bandwidth in an asynchronous data transfer and source traffic control system include permitting some bus users (e.g. networks cards) to access both odd and even frames while permitting other bus users (e.g. subscriber line cards) to access only odd or even frames. An apparatus according to the invention supports line cards numbering up to 32?(2×the number of network cards). An exemplary embodiment shows a single network card coupled to an OC-12 network link and twenty asymmetric digital subscriber line cards.

Abstract: An arbitration device arbitrates among master devices such that each master device is allowed to access a shared memory at a predetermined bandwidth, and the arbitration device permits an access request in a first period that a designer has set as desired if the access request has been made by a specific master device beyond a bandwidth that has been allocated in advance. The arbitration device masks an access request from the specific master device in a second period that follows the first period.

Abstract: It becomes possible for a user to set a transmission or reception channel arbitrarily and easily. Each of equipment connected to an IEEE 1394 bus may include a register provided within a RAM 113 to thereby set a transmission or reception default channel. If channels used in the transmission and the reception are not set when the transmission is started, then default channel may be used. When equipment is set to a channel setting mode by operating an operation section 116, a control section 112 may display a channel setting picture on a display section 115. In this state, a user may select a set channel by operating an up-key 116a and a down-key 116b of the operation section 116. Thereafter, when a user operates a “YES” key 116c, the control section 112 may write a selected channel in the above-mentioned register, and ends a default channel setting operation. A user can set the transmission or reception channel arbitrarily and easily.

Abstract: Systems and methods for early fixed latency subtractive decoding are disclosed. The subtractive decoding device speculatively, or conditionally, acknowledges a bus transaction within a fixed time period that is the same as the time period for positive decoding. Pipelining of a new bus transaction may therefore be accomplished each new time period. A bus transaction may be retried if no acknowledgement occurs within the fixed time period.