Abstract: A user terminal (1) having a communications processor (10) that carries out a cyclic data transmission. During a cyclic part (ZYK,x) of a cycle (Z,x) in which user data are transmitted, a DP application may not access the memory (14, 15). In the communications processor (10), the memory (14, 15) stores a process image. The communications processor (10), for the purpose of synchronization, transmits at the beginning of a cycle a cycle start interrupt (ZSI,x) and at the end of the cyclic part (ZYK,x) a cycle end interrupt (ZEI,x). Once the arithmetic unit (5, 7, 8) has accessed the memory it releases the interrupts. The duration (&Dgr;T′s2,1; &Dgr;T′e2,1) between two successive interrupts serves to detect access violations and to initiate appropriate fault treatment measures.

Abstract: A method of half duplex transmission of a packetized digital data includes the steps of inputting a new packet to be transmitted to a first-in-first-out storage, determining whether the new packet contains time information related to synchronization with other electronic device, responsive to the determination that the new packet contains time information, updating a local timer of the electronic device with a prescribed value, continuously incrementing the local timer, responsive to a timing enabling transmission of the new packet by the transmitting/receiving unit of the electronic device, reading the new packet from the first-in-first-out storage, determining whether the new packet contains time information or not, changing the time information by using a value of the local timer to prevent mismatch in synchronization with other electronic device, and outputting to the bus through the transmitting/receiving unit.

Abstract: The present invention is directed to a method and apparatus for scheduling a resource to meet quality of service guarantees. In one embodiment of three levels of priority, if a channel of a first priority level is within its bandwidth allocation, then a request is issued from that channel. If there are no requests in channels at the first priority level that are within the allocation, requests from channels at the second priority level that are within their bandwidth allocation are chosen. If there are no requests of this type, requests from channels at the third priority level or requests from channels at the first and second levels that are outside of their bandwidth allocation are issued. The system may be implemented using rate-based scheduling.

Abstract: Data transfer between a master node (300) and plural memory nodes (301-308) follows a synchronous fixed latency loop bus (255). Each memory node includes bus interface (311-318) which passes command, write data, write address, and read data and read address to a next memory node in the loop. Each memory node performs a read from its memory at the specified address if a read command is directed to it. Each memory node performs a write to its memory at the specified address if a write command is directed to it. Simultaneously read and write to a single node is prohibited. This configuration provides a fixed latency between the issue of a read command and the return of the read data no matter which memory node is accessed. This configuration prevents collision of returning read data and of incoming write data. This configuration provides fixed loading to each stage regardless of the number of memory nodes. Thus the design of large systems operating at high speeds is simplified.

Abstract: A method for granting access to a bus is disclosed where a fair arbitration is modified to account for varying conditions. Each bus master (BM) is assigned a Grant Balance Factor value (hereafter GBF) that corresponds to a desired bandwidth from the bus. Arbitration gives priority BMs with a GBF greater than zero in a stratified protocol where requesting BMs with the same highest priority are granted access first. The GBF of a BM is decremented each time an access is granted. Requesting BMs with a GBF equal to zero are fairly arbitrated when there are no requesting BMs with GBFs greater than zero wherein they receive equal access using a frozen arbiter status. The bus access time may be partitioned into bus intervals (BIs) each comprising N clock cycles. BIs and GBFs may be modified to guarantee balanced access over multiple BIs in response to error conditions or interrupts.

Abstract: A system and method for automatically assigning resources to a slave device inserted into a PCI backplane utilizes pairs of PCI GNT/REQ lines as bus lines of a time division multiplexed multiplexer control bus. The slave device generates a random delay number and utilizes the number to select an unassigned time slot to be assigned to the slave device. Configuration data is transferred to the slave utilizing the already existing PCI GNT/REQ lines so that no additional bus lines and card space are required to automatically assign resources to the slave device.

Abstract: A method for adapting a bus to data traffic in a system comprising several functional units (311, 312, . . . , 31n) and a bus structure. The functional units are divided into at least two sets so that units, which mainly transfer data with each other belong to a same set and are interfaced with the same separate sub-bus (321; 322). The sub-buses can be united by switches (SW) into a more extensive bus, which is only used when data must be transferred between different sets. Supply voltage of each sub-bus is adjustable and is set the lower the less traffic there is on the bus. The parallel transfer operation makes it possible to increase the transfer capacity of the bus structure without increasing it's clock frequency. Furthermore energy consumption can be reduced by dropping the supply voltage of the bus circuits so that the bus retains the transfer capacity needed.

Abstract: A wearable computer system includes a processing unit (102) and a number of peripherals. The processing unit and peripherals are coupled in a daisy-chain fashion utilizing a serial bus (120). The processing unit has a single connector for implementing the serial bus, and peripherals each have two connectors for propagating the serial bus. The wearable computer system has only one unused connector at any one time, thereby reducing excess bulk and weight due to excessive unused connectors. When a peripheral interrupts the processing unit, the processing unit relinquishes the serial bus to the interrupting peripheral. Alternatively, peripherals are assigned time slots within which the peripherals can utilize the serial bus.

Abstract: A system is configured to prioritize streaming disk I/O over non-streaming disk I/O by providing high priority queuing to streaming disk I/O and/or to throttle non-streaming disk I/O when the total disk I/O (streaming+non-streaming) exceeds a threshold amount for a given time quantum. When disk throttling is utilized, streaming disk I/O is processed in a first time quantum. Non-streaming disk I/O is processed, as much as possible, in the remainder of the first time quantum. Other non-streaming disk I/O remaining to be processed is deferred to a subsequent time quantum.

Abstract: Circuits and associated methods for operation thereof for gathering real-time statistical information regarding operation of the arbiter circuit in a particular system application. The real-time statistical information so gathered is useful for off-line analysis by a system designer for determining optimal configuration and parameter values associated with operation of a particular arbiter in a specific system application. In a first exemplary preferred embodiment, a timer circuit associated with the arbiter measures a predetermined period of time during which statistical data is to be gathered. Counter circuits associated with the arbiter count the number of occurrences of events of interest to the designer during the time period measured by the timer circuit. Each counter circuit preferably senses and counts a particular event of interest to the designer.

Abstract: A bus bandwidth consumption profiler for measuring and reporting bus cycle utilization in a system having multiple bus masters, including master counters paired with the masters to count cycles of bus ownership, and a realtime counter to count elapsed cycles between profile events generated by either a realtime counter roll-over, or a system read signal. Upon a profile event, the counts of the master counters are simultaneously output to the system and the realtime count is determined. Alternatively, the profiler includes a total counter for counting the combined bus cycles owned by all masters, and fewer master counters than masters, each configurable to count a selected master. Upon a profile event, the counts of the master counters, the total counter, and the realtime counter are simultaneously output to the system. Accordingly, the bandwidth consumption of the selected masters and the combined, non-selected masters, can be calculated using fewer counters.

Abstract: An apparatus and method for distributing data transmission from a plurality of data input queues in a memory buffer to an output. The method includes associating a priority indicator with each data input queue, determining a priority indicator having a highest priority level among the plurality of priority indicators and selecting the data input queue associated with the priority indicator having the highest priority level to transmit to the output.

Abstract: The present invention is built on a time out control apparatus to control the time out when a packet is transferred between terminal units connected to different buses. In the time out control apparatus, delay measuring means measures the delay time required for a response packet to be received after a request packet is sent to a terminal unit (control unit) connected via a bus. Delay information list generating means generates a delay information list in which the delay times measured by the delay measuring means are related to the individual identification information on the respective terminal units. Information output means reads out the delay time from the delay information list in accordance with a request from the terminal unit and outputs the delay time to the terminal unit. This sets the delay time on the time out register of the terminal unit.

Abstract: A method for use with a computer system includes permitting a first bus agent to access a bus during predetermined windows of time and preventing a second bus agent from accessing the bus outside of the windows. The first bus agent has a higher priority than the second bus agent. The method includes monitoring the use of the bus by the first bus agent during the window and the regulation durations of the windows are selectively regulated based on the use.

Abstract: Disclosed is a method of data rate adaptation based on channel conditions. In the present invention, data is initially transmitted at a first data rate based on a measured first channel condition and, if a NACK is received, the data is retransmitted. The data retransmitted is at a rate which is based on the condition of the channel during or before the transmission of the NACK. The data retransmission rate can also be based on the actual channel condition at the time of the first transmission plus the condition of the channel before or during the transmission of the NACK.

Abstract: In a storage environment or storage area network having multiple host devices and at least one storage array, the host devices access logical data volumes stored on the storage array through array controllers disposed in the storage array. Multiple host devices can request access to shared ones of the logical data volumes through multiple paths to multiple array controllers, but each logical data volume is controlled or owned by only one array controller at a time. Thus, ownership of shared logical data volumes is transferred between the array controllers as necessary on behalf of the requesting host devices. To prevent ownership transfers from occurring too often, however, ownership of the logical data volumes is made exclusive, or “sticky,” for a period of time after each transfer. During the exclusive ownership period of time, the ownership cannot be transferred.

Abstract: A method adaptively controls admission of a plurality of resources to a peripheral bus having a finite bandwidth. It monitors the actual data transfer rate of each resource having a bandwidth guarantee on the peripheral bus for data communications. Upon receiving a request for admission to the peripheral bus from an additional resource, a utilization value representative of the extent to which the plurality of resources utilizes the guaranteed bandwidth on the peripheral bus is obtained. The additional resource is admitted to the peripheral bus if the utilization value indicates that the amount of unutilized bandwidth on the peripheral bus is approximately sufficient to satisfy the data transfer rate of the additional resource.

Abstract: A method for use with a computer system includes permitting a first bus agent to access a bus during predetermined windows of time and preventing a second bus agent from accessing the bus outside of the windows. The first bus agent has a higher priority than the second bus agent. The method includes monitoring the use of the bus by the first bus agent during the window and the regulation durations of the windows are selectively regulated based on the use.

Abstract: A modular electronic device has a cabinet frame, a plurality of push-in modules with module frames retained in the cabinet frame side-by-side, and printed circuit boards mounted in the module frames, and electronic components carried by said printed circuit boards. Each of these modules has autonomous data transmitting connections for communicating directly with each of the other ones of the modules.

Abstract: An apparatus and method for intercepting messages between the bus controller and a device attempting to connect over the bus. Based on the intercepted message, the existing device using bandwidth can determine whether it can relinquish some of its bandwidth allocation while maintaining sufficient transmission quality. Thus, the already connected devices will make the determination if they can relinquish bandwidth, to allow a new device to connect.

Abstract: In a system integrating modules (PROC) designed for a time-slotted resource-accessing scheme and modules (PROC′) designed for accessing a common resource based on request-arbitration, a request-arbitration scheme is used for managing access to a common resource. The module(s) (PROC) designed for a time-slotted resource-accessing scheme are associated with an anticipatory request generator (ARG) adapted to generate, and forward to the arbiter (P_ARB), anticipated requests produced ahead of the time instants when the associated modules are designed to make access requests. A data buffer (DATA BUF) is also associated with each of the modules designed for a time-slotted resource-accessing scheme, so as to hold data obtained as a result of an anticipated request until the time instant when the module generates the request associated with this data.

Abstract: In plural master apparatus connected to a bus, a master apparatus issues, to an arbiter, a request signal requesting the use of the bus after a lapse of a predetermined interval when the use of the bus becomes necessary, while another master apparatus issues, to the arbiter, a request signal requesting the use of the bus immediately when the use of the bus becomes necessary. The arbiter grants a right to use the bus by equally handling the request signals from the master apparatus. Also there is prepared a signal indicating a traffic in the bus, and the request signal is issued after the lapse of the interval in case of a high traffic but it is issued immediately in case of a low traffic. It is thus possible to adjust the practical priority of the but use right in detail or to dynamically change such priority by the presence or absence of such interval or a length thereof.

Abstract: Several peripheral entities are provided, with each peripheral entity being clocked by its own internal clock signal and being able to access a single-access memory. A priority entity is defined from among the peripheral entities, and the other peripheral entities are defined as auxiliary entities. A repetitive time frame is formulated, regulated by the internal clock signal of the priority entity, and subdivided into several groups of time windows that are allocated to the peripheral entities. One of the peripheral entities is a microprocessor that is disabled for a fixed duration after each memory access request.

Abstract: Disclosed is a method of data rate adaptation based on channel conditions. In the present invention, data is initially transmitted at a first data rate based on a measured first channel condition and, if a NACK is received, the data is retransmitted. The data retransmitted is at a rate which is based on the condition of the channel during or before the transmission of the NACK. The data retransmission rate can also be based on the actual channel condition at the time of the first transmission plus the condition of the channel before or during the transmission of the NACK.

Abstract: The present invention provides a fault tolerant bus architecture and protocol for use in an Integrated Hazard Avoidance System of the type generally used in avionics applications. In addition, the present invention may also be used in applications, aviation and otherwise, wherein data is to be handled with a high degree of integrity and in a fault tolerant manner. Such applications may include for example, the banking industry or other safety critical processing functions, including but not limited to environmental control.

Abstract: The present invention provides a method and a system for connecting together, in a VLSI chip, a plurality of macros which require data flow connections between each other. A simple standard interface is realised between all macros. Any number of macros can be connected together, also allowing concurrent transactions between 4 or more macros using a cross-bar switch. Each macro may be a master (capable of requesting connections), a slave (capable of receiving connections from a master) or both. The centralised inter-connect logic includes three major components: the cross-bar switch, which makes the connections between the macros, the address decoder, which determines which slave each master wishes to connect to and an arbiter, which arbitrates between the macros when two or more masters request a connection simultaneously.

Abstract: Systems and methods by which voice/data communications may occur in multiple modes/protocols are disclosed. In particular, systems and methods are provided for multiple native mode/protocol voice and data transmissions and receptions with a computing system having a multi-bus structure, including, for example, a TDM bus and a packet bus, and multi-protocol framing engines. Such systems preferably include subsystem functions such as PBX, voice mail and other telephony functions, LAN hub and data router. In preferred embodiments, a TDM bus and a packet bus are intelligently bridged and managed, thereby enabling such multiple mode/protocol voice and data transmissions to be intelligently managed and controlled with a single, integrated system. A computer or other processor includes a local area network controller, which provides routing and hub(s) for one or more packet networks. The computer also is coupled to a buffer/framer, which serves to frame/deframe data to/from the computer from TDM bus.

Abstract: An arbitration protocol is provided for determining between a pair of subsystems within a networking system having a plurality of subsystems which subsystem might obtain access to a common hardware resource. The protocol allows the networking system to determine which subsystem becomes the sender and which becomes the receiver. The protocol is based on a point-to-point communication between two peer subsystems . It is based on an asymmetrical quality such that the first or priority subsystem has a zero latency in accessing the switch while the second subsystem must wait at least one clock cycle before obtaining access to the network system after requesting it and after the end of control by the first subsystem.

Abstract: A system for time-ordered execution of load instructions. More specifically, the system enables just-in-time delivery of data requested by a load instruction. The system consists of a processor, an L1 data cache with corresponding L1 cache controller, and an instruction processor. The instruction processor manipulates an architected time dependency bit field of a load instruction to create a Distance of Dependency (DoD) bit field. The DoD bit field holds a relative dependency value which is utilized to order the load instruction in a Relative Time-Ordered Queue (RTOQ) of the L1 cache controller. The load instruction is sent from RTOQ to the L1 data cache at a particular time so that the data requested is loaded from the L1 data cache at the time specified by the DoD bit field. In the preferred embodiment, an acknowledgement is sent to the processing unit when the time specified is available in the RTOQ.

Abstract: The invention concerns an arbitration scheme for permitting access to the bus of a computer. The arbitration scheme has the ability to control and reduce the delay experienced by any device by monitoring the queue length of the device and using information concerning the device, such as device rate, phase, data transfer size and queue length. Specifically, the arbiter prevents periodic accessing devices, such as audio and video samplers, from being delayed or interrupted for long periods of time once they have begun accessing the bus.

Abstract: To transfer information between modules which are connected to a common bus, the module that wants to send information sends a request signal via a common bus request line. The module (bus master) which controls the bus activities, receives this signal, sends a command via the bus to all bus users, and thus starts a cycle of clock pulses. A particular clock pulse within a cycle is assigned to each bus user, during which it can send or receive one signal each along one or several predefined bus lines (FIG. 1).

Abstract: A bus management system for dynamically allocating bandwidth comprises a bus and a plurality of slave cards coupled to the bus. The slave cards communicate data to the bus and receive data from the bus. The system also includes a master card coupled to the bus. The master card communicates data to the bus and receives data from the bus. The master card comprises a memory, a communication module, and a control module. The memory stores bandwidth information indicating bandwidths allocated to the slave cards. The communication module, coupled to the bus and the memory, communicates with the slave cards according to the bandwidths indicated by the bandwidth information The control module, coupled to the memory, allocates a new bandwidth to a selected slave card and modifies the bandwidth information to indicate the new bandwidth allocated to the selected slave card.

Abstract: A point-to-point serial communication link between a system interface unit and a peripheral bus interface unit is provide. The system bus interface unit may interface between a CPU bus and a peripheral bus, such as the PCI bus, and may be referred to as a north bridge. The system interface unit may also interface to main memory and to an advanced graphics port. The peripheral bus interface unit may interface between a first peripheral bus, such as the PCI bus, and a second peripheral bus, such as an ISA bus, and may be referred to as a south bridge. The serial communication link between the system interface unit and the bus interface unit may be a one wire serial bus that uses a bus clock from the first peripheral bus as a timing reference. This clock may be the PCI clock. The serial communication link may use a single pin on the system interface unit and a single pin on the bus interface unit to transfer commands between the interface units.

Abstract: An integrated circuit contains a microprocessor core, program memory and separate data storage, together with analogue and digital signal processing circuitry. The ALU is 16 bits wide, but a 32-bit shift unit is provided, using a pair of 16-bit registers. The processor has a fixed length instruction format, with an instruction set including multiply and divide operations which use the shift unit over several cycles. No interrupts are provided. External pins of the integrated circuit allow for single stepping and other debug operations, and a serial interface (SIF) which allows external communication of test data or working data as necessary. The serial interface has four wires (SERIN, SEROUT, SER-CLK, SERLOADB), allowing handshaking with a master apparatus, and allowing direct access to the memory space of the processor core, without specific program control.

Abstract: Multimedia applications including a video and an audio are transmitted at respective adapted transfer rates in a server connected with a networks. The server operates on an operating system which permits a multithreading by allocating time slices to thread. For each application, data on a required transfer rate indicative of a permitted lowest transfer rate for the application is prepared. Threads are generated for respective applications. An initial number of slices are allocated to each thread to let said threads transmit said respective applications. A transfer rate of each thread is measured at a time interval. A number of slices to be allocated to each thread is calculated such that the measured transfer rate of each thread (i.e., each application) becomes equal to the required transfer rate of the application transmitted by the thread.

Abstract: In this method, access to the bus is controlled by a policy assigning graded priorities to the various masters so that a new priority master succeeds a current master on the bus as soon as that current master leaves the bus. The priority assignment policy is implemented by logic gates integrated into a circuit, for example an application-specific integrated circuit. Each master is assigned a time slot for occupying the bus, said slot constituting a modifiable parameter specific to the master to which it is assigned. The priority assignment policy is preferably a last recently used policy whereby the highest priority level is assigned to the least recently used master.

Abstract: A bus controller for a CCD digital still camera arbitrates competing requests by multiple microcontrollers for a shared memory. One of the microcontrollers is designated to have a higher priority than the other microcontroller(s). In the case of competing requests, while one microcontroller is granted access to the memory, the other microcontroller performs other processing, and polls a memory status register to determine when the memory is available. Since the waiting processor performs other operations, as opposed to idling, the efficiency of the microcontroller is improved.

Abstract: A method and device for the exchange of data in messages between at least two users which are connected by a bus system and have separate time bases, the messages containing the data being transmitted by the users via the bus system; and a first user, in a function as timer, controls the messages as a function of time in such a way that it repeatedly transmits a reference message, which contains time information regarding the time base of the first user, via the bus at a specifiable time interval; the at least second user forms its own time information, using its time base, as a function of the time information of the first user; a correction value is ascertained from the two pieces of time information; and the second user adapts its time information and/or its time base as a function of the correction value.

Abstract: A system architecture for a high speed serial bus compatible with the 1394 standard is disclosed. A transaction interface coordinates data packets received from or sent to a 1394 bus. A kernel/scheduler/dispatcher is used to allocate memory resources, and start a variety of tasks and services. The tasks and services vary depending on protocols used in a transport layer and application layer used in conjunction with the 1394 layers. Each task operates according to a state machine progression. The transaction interface accepts data information from the tasks and forms data packets for delivery to the 1394 bus. The data packets are initially sent via an associated hardware register, but if busy, the transaction interface polls for other available registers. In addition, all queued transactions are loaded into registers in the most expedient manner.

Abstract: A control device manages status and dual information of respective boards in a clock distributor for use in a CDMA base station controller. The device forms a TD-bus communication path and an address map for TD-bus communication, so as to manage the status and dual information of the respective boards in the clock distributor. The device periodically checks installation/uninstallation, normality/abnormality, and dual status of the respective boards in the clock distributor through the TD-bus communication using the address map, and reports changed status information to an operator.

Abstract: Data transfer scheme wherein data transfer rates can be effectively doubled with no increase in the clock speed of the interface. This is accomplished by allowing more than one data transfer to occur on a single clock cycle. This transfer scheme increases the transfer rate of the interface by multiplexing two data groups on the same interface. These data groups are transmitted from a source phase latch at approximately the same time as two strobe signals which have low skew with respect to the data. The master and slave strobe signals are logically combined to create an even latch enable signal and an odd latch enable signal that are used to latch and de-multiplex the multiplexed data groups at a receiving end of a pair of flow-though source synchronous latches.

Abstract: An arbiter connects a plurality of devices to a bus. The arbiter determines priority among the devices based on minimum access intervals associated with the devices and timers which keep track of the elapsed time since each device last had access to the bus. The timers can be configured to either count up from zero to the minimum access interval of each device or count down from the minimum access interval of each device to zero. The arbiter can also adjust the minimum access intervals of the various devices based upon factors such as the amount of data required by the device, the amount of data most recently received by the device and the transfer rate of the device. The arbiter thus optimizes bus usage while minimizing the likelihood of a given device not functioning based on an ability to access the bus due to contention with other devices.

Abstract: Low-latency arbitration is provided for a super-priority communications device such as modems and ISDN/DSL routers, LAN switches and routers. Phantom arbitration slots are inserted between each pair of permanent slots. When a request from the super-priority agent is received, the next phantom slot is used to service the request. The initial latency is just one slot period rather than the whole arbitration loop. Other phantom slots are skipped until the same phantom slot is again activated at the same point in the arbitration loop during subsequent rounds of arbitration. Thus only the initial latency is reduced; subsequent requests from the super-priority agent are handled just once for each arbitration cycle. The low initial latency allows the communications device to quickly respond to an incoming call. Other real-time agents are assigned a fixed slot in a round-robin arbitration. The last arbitration slot is used by all non-real-time agents.

Abstract: A system and method for arbitrating amongst a plurality of applications requesting bus access. Based on the applications requesting bus access, a bus frame is calculated, and a plurality of bus duration time slots within the bus frame are determined. For each bus duration time slot, a priority is assigned to each application requesting bus control and a bus allocation table is created. A bus master controller then allocates control during each bus duration time slot in accordance with the priorities in the bus allocation table.

Abstract: An arbiter implements an arbitration scheme that allows a requestor that has been granted use of a resource to use the resource for a predetermined number of data transfers before relinquishing the resource. At the time a requestor is granted use of the resource, a register is loaded with a value that defines a limit on the how much the requestor can use the resource. More particularly, the value defines a number of bytes that the requester is allowed to transfer before being required to relinquish use of the resource. The value is decremented each time the requestor makes a data transfer, as long as there is also a pending request from another requestor. If there is no pending request from another requester, the value is not decremented even though the requestor has transferred data. Until the time that the value is decremented to zero, the requester may repeatedly make requests to the arbiter for use of the resource, and the arbiter will continue to grant them.

Abstract: An improved data processing system and in particular an improved data processing system that more effectively manages a shared resource within a data processing system. More specifically, a method and apparatus for managing access to a shared resource between a plurality of devices simultaneously requesting access to the shared resource. The present invention implements a design that combines a priority configuration and a shifting sequential configuration. The access is controlled by an arbiter that determines access to the shared resource by granting first, to priority devices and then to the highest priority shifting sequential device requesting access within one clock cycle of a device terminating its request for access to the shared resource.

Abstract: A scalable multiport switch that receives and transmits data through a plurality of ports is provided with a plurality of internal buses, an external memory interface, and a slot manager. The external memory interface is coupled to the internal buses and has an external memory port for coupling the external memory interface to an external memory. The slot manager schedules access to the external memory through the internal buses and the external memory interface in a series of time slots. Each slot consists of m clock cycles to transfer n bytes of data. The slot manager is operable at a selectable one of multiple frequencies, the operating frequency of the slot manager being selected to match an operating frequency of the external memory. The slot manager increases the number of slots per given period of time with increasing operating frequency of the slot manager, but maintains the number of clock cycles per slot constant, thereby providing greater access to other sources of data.

Abstract: A solution to the problem of undesired serialization of bus controlled instrument measurement delays for multiple instances of programmatically controlled measurement processes is to configure the bus operations and the control programs to allow the issuance of a command within the context of a first collection of such instruments, without having to wait for the corresponding data before issuing commands within the context of a second collection. This is done by instructing the equipment in the collection to signal that they have data instead of the more customary immediately issued "@ address talk", which is then followed by the delay needed by the equipment to make the measurement. Instead, the "have data" signals are associated with the devices that originated them and then the bus instructions that request the data are issued. In conjunction with this, the usual bus I/O commands in the controlling programs may be replaced with calls to a library that operates in just this fashion.

Abstract: Methods and associated apparatus for improving the fairness of bus allocation in association with standard SCSI bus arbitration. The present invention provide a plurality of time slots each of which define a delay period following the SCSI specified minimum period before arbitration is allowed to begin. Each device which requires arbitration on the SCSI bus pseudo-randomly selects one of the time slots before attempting SCSI bus arbitration. The device then delays the associated period of time before commencing SCSI bus arbitration. At any time before the end of the delay period, if the device senses that the SCSI bus has again become busy, then the device has already lost the arbitration without actually competing therefore. A second device, having selected a time slot with a shorter delay period, has won control of the SCSI bus before the first device attempted arbitration. The time slots are selected with a probability associated with each slot.

Abstract: The present invention comprises a method and system for implementing prioritized communications in a computer system. The present invention is implemented on a computer system having a microprocessor and a plurality of peripheral devices coupled to the computer system. The system of the present invention determines a first priority level and determines a second priority level. The system of the present invention receives a bandwidth allocation request from a software process to transfer data at the first priority level between two or more peripheral devices. The system subsequently allocates a first priority data transfer bandwidth between the devices in response to the request and performs a first data transfer between the devices using the first priority data transfer bandwidth. In addition, the system of the present invention performs a second data transfer between other devices using a second priority data transfer bandwidth. The second data transfer occurs at a second priority level.