Abstract: The Sharing arbiter is an arbiter which, under certain conditions, permits two or more Done signals to be received before the Sharing arbiter issues a grant signal and, under certain conditions, is permitted to issue more than one grant signal before receiving a Done signal. A Sharing arbiter can be implemented by adding a queue onto the Done input of a Sequencer arbiter. In a Sharing arbiter with a Sharing-number of N and K request inputs, the Sharing arbiter is permitted to issue M grant signals concurrently if M input requests have been received (where M≦K and M≦N) without enforcing mutual exclusion between the grants if at least M Done signals have also been received. Where less than M Done signals have been received (P Done signals, for example), the Sharing arbiter arbitrates among the M input requests and is permitted to issue P grant signals concurrently.

Abstract: A method and apparatus for arbitrating on a high performance serial bus is disclosed. The invention provides for a plurality of arbitration phases and an arbitration advancing means.

Abstract: A cell bus arbitration system comprises a data bus and a plurality of modules operative for sending data in data cell. The modules are connected to the data bus and each one of the modules is in communication with each one of the other modules via at least one control line such that each one of the modules is capable of receiving control signals generated by each other module. Arbitration logic assigns bus mastery to one of the modules.

Abstract: A method of communicating between an initial device and a target device connected by a plurality of intermediate segments in a distributed arbitration system is provided. The method includes establishing an arbitration timer for a communication request by the initial device. Furthermore, use of each of the intermediate segments is arbitrated based on the arbitration timer.

Abstract: A bus architecture is provided to facilitate communication between independent bus masters and independent bus slaves by having two or more bus arbiters in a system-on-chip (SOC) system. Each bus master in the system is coupled to all bus arbiters in the system, so that each bus master can access a corresponding bus slave concurrently as well as sequentially. Such concurrent communication carries not only read and/or write data but also a target address of the corresponding bus slave, thereby enabling true concurrency in data communication between bus masters and bus slaves.

Abstract: A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by node controllers. A node controller receives transactions from a master device, communicates with a master device as another master device or as a slave device, and queues transactions received from a master device. Since the achievement of coherency is distributed in time and space, a node controller helps to maintain cache coherency. The node controllers must give simultaneous address bus grants to the address switch to initiate a snoop. Livelocks are detected individually by each node controller in an uncoordinated manner from a lack of successful snoops from the address switch to the node controllers.

Abstract: In a first embodiment, multi-speed concatenated packet strings are transmitted by a first node on a serial bus. To accommodate multi-speed packets, a speed signal is transmitted immediately prior to the packet. In a second embodiment, ACK-concatenation is used to allow a node to transmit a data packet immediately after transmitting an acknowledge signal on the bus. The data packet need not be related to the ACK packet. In a third embodiment, a node which receives a first data packet followed by a data end signal on a child port, concatenates a second data packet onto the first data packet during retransmission. The second data packet is also transmitted down the bus in the direction of the node which originally transmitted the first data packet.

Abstract: A system for limiting fracturing of write data by a PCI bus adapter which queues operation commands in a command queue. The write data is in the form of bursts comprising a plurality of contiguous words. Fracture detection logic senses fracturing of the write data. A bus arbiter is responsive to the sensed fracturing of write data by the target, and blocks access to the PCI bus. Queue level detection logic is employed, subsequent to the blocking, to monitor completion of the queued operation commands of the PCI bus target. The bus arbiter is then responsive to the queue level detection logic indicating that the PCI bus target has completed enough operations that a predetermined number (such as one) of the operation commands remain queued at its command queue, and grants access to the PCI bus to complete the burst write operation without fracturing.

Abstract: A source module, a destination module, or both modules, that are used in a data transfer, signal over an internal communication bus to a bus master when the addressed storage location in the data transfer comprises a single point address type memory, the addressed module drives an active signal on an address increment disable line in the control bus. In response to the active signal on the address increment disable line, the bus master inhibits changing the address for the duration of the data transfer. The module also drives an active signal on an expansion address off boundary line in the control bus when an internal expansion address of the module is not aligned with a natural boundary of a data bus of the internal communication bus to allow the bus master to adjust the width of the data transfer.

Abstract: A method and implementing system is provided in which multiple nodes of a PCI bridge/router circuit are connected to corresponding plurality of PCI busses to enable an extended number of PCI adapters to be connected within a computer system. Multiple enhanced arbiters are implemented to enable non-blocking and deadlock-free operation while still complying with PCI system requirements. An exemplary PCI-to-PCI router (PPR) circuit includes the arbiters as well as PPR buffers for temporarily storing transaction-related information passing through the router circuit between adapters on the PCI busses and/or between PCI adapters and the CPUs and system memory or other system devices. A buffer re-naming methodology is implemented to eliminate internal request/completion transaction information transfers between bridge buffers thereby increasing system performance.

Abstract: A method for implementing scheduling mechanisms with selectable resource modes comprises at least one resource characterization set that includes a plurality of resource characterizations that each have resource requirements for executing a requested process. The plurality of resource characterizations may include a most mode, a best mode, and a worst mode. An allocation manager may then select a resource mode, and compare the corresponding resource requirements for the requested process to the currently-available device resources. The allocation manager may then authorize or deny the requested process depending upon whether the currently-available resources are sufficient to adequately service the resource requirements of the requested process.

Abstract: A computer system is disclosed with a host bridge that arbitrates access to a system resource from a CPU via a host bus and from a set of bus agents via a peripheral bus. A separate set of priority classes are provided to the CPU and to the bus agents and programmable timers are included to tune system resource allocation between the host and processor busses.

Abstract: A method and apparatus performs high bandwidth low latency programmed I/O (PIO) write operations by passing tokens. A computer system in accordance with the present invention includes a plurality of CPUs, with each CPU coupled to a CPU agent. Each CPU agents is coupled to an interconnection fabric, which in turn is coupled to an I/O agent and memory. The computer system may also have multiple I/O agents. Each I/O agent is coupled to an I/O card, and the computer system may have multiple I/O cards. The CPU agents and the I/O agents have token slots, and tokens circulate between the token slots. When a CPU seeks to write to an I/O card, the CPU forwards a PIO write request to the CPU agent. If the CPU agent does not have the token, the CPU agent sends the write data along with a request for the token to the I/O agent. If the token is currently owned by the I/O agent, it is sent to the CPU agent.

Abstract: An electronic apparatus uses a bus conductor driven by wired logic to arbitrate between stations. When arbitration is decided, the apparatus switches to a higher speed mode by supplying additional current to the bus conductor, so that the winning station pulls the potential on the bus conductor against a greater current and the potential rises faster when the station stops pulling the potential.

Abstract: A method and apparatus allowing efficient access control to a common data bus by including an isolation device to separate the common data bus, a priority-based arbiter to control access to the internal portion of the common data bus including a processor or other bus master, and a time slot arbiter to control access to the external portion of the common data bus including multiple bus masters, an external memory interface, etc. The common external memory may be allocated for exclusive or non-exclusive use by the various devices utilizing either portion of the isolated common data bus. External devices accessing the external memory may communicate directly with one or more bus masters, e.g., on the internal portion of the common data bus.

Abstract: In the context of a bus-mastering system, a device selector selects the device to control the bus by assigning “combined” priority values to the devices and selecting the device with the highest combined-priority value. The combined-priority values include relatively high-significance device-specific values and relatively low-significance arbitrary-rank values. At any given time, no two devices share the same arbitrary-rank values, and thus cannot share combined-priority values. Thus, there are no unresolved selections due to equal priorities. In accordance with the present invention, the arbitrary-rank values are varied in a round-robin fashion to minimize the bias inherent in conventional schemes using a priority encoder. This makes the device selection process conform better to the device-specific values, which are presumable selected to optimize system performance.

Abstract: The method of the present invention includes maintaining a first tier 101 and a second tier 102 of devices 30 that have access to a secondary bus 42 that a PCI to PCI bridge 38 services. Each device 30 that has access to secondary PCI bus 42 is categorized into either first tier 101 or a second tier 102. The devices 30 in first tier 101 are provided more frequent opportunities to gain access to secondary PCI bus 42 than devices in low tier 102. Next, a pending transaction is recognized when an initiating device 30 that has been categorized into second tier 102 accesses secondary PCI bus 42 and attempts a transaction that crosses PCI to PCI bridge 38 to primary PCI bus 26. However, PCI to PCI bridge 38 is unable to complete the transaction on primary PCI bus 26. Therefore, PCI to PCI bridge 38 is unable to provide access to any other device 30 on secondary bus 42 until the pending transaction completes.

Abstract: In a first embodiment, multi-speed concatenated packet strings are transmitted by a first node on a serial bus. To accommodate multi-speed packets, a speed signal is transmitted immediately prior to the packet. In a second embodiment, ACK-concatenation is used to allow a node to transmit a data packet immediately after transmitting an acknowledge signal on the bus. The data packet need not be related to the ACK packet. In a third embodiment, a node which receives a first data packet followed by a data end signal on a child port, concatenates a second data packet onto the first data packet during retransmission. The second data packet is also transmitted down the bus in the direction of the node which originally transmitted the first data packet.

Abstract: One embodiment of the present invention provides a method for flexibly allocating I/O pins used for bus grant signals between bus controllers located on a semiconductor chip. The method operates by receiving a first set of grant lines from a first bus arbitration circuit. This first set of grant lines is used to grant control of a first bus to devices on the first bus. The method divides the first set of grant lines into a first subset of grant lines and a second subset of grant lines. The method also receives a second set of grant lines from a second bus arbitration circuit. This second set of grant lines is used to grant control of a second bus to devices on the second bus. The method divides the second set of grant lines into a third subset of grant lines and a fourth subset of grant lines. Next, the method selects outputs from between the first subset of grant lines and the third subset of grant lines, and drives the outputs off of the semiconductor chip through a first set of output pins.

Abstract: A method and an system are provided for servicing a plurality of agents requesting access to a bus. The agents are arranged in a hierarchical order of groups, each having first and second pairs of the agents. Within each group, flags are set to indicate which pair was last serviced and which agent in each pair was last serviced.

Abstract: A bus arbitration regulates access to a common bus by a plurality of devices by assigning each device a priority rank. A current weighted bandwidth of each device is set equal to a desired weighted bandwidth. A request to access the common bus is granted to the device having the highest priority rank among a set of requesting devices. The current weighted bandwidth the first device is decremented. The priority rank of the serviced device is set equal to a lowest value if its current weighted bandwidth is equal to a minimum value. The priority rank of a set of devices which previously had a lower priority rank than the first device is increased. The current weighted bandwidth of the serviced device is set equal to the desired weighted bandwidth. After a number of bus transactions have been completed, the desired weighted bandwidth of the devices may be adjusted to based upon system performance.

Abstract: One embodiment of the present invention provides an apparatus that selectively encodes bus grant lines to reduce I/O pin requirements. This apparatus includes a semiconductor chip with bus arbitration circuit. A number of grant lines emanate from the bus arbitration circuit. An encoder circuit encodes the grant lines into a smaller number of encoded grant lines. A selector circuit selects outputs from between the encoded grant lines and a first subset of grant lines. These outputs pass through output pins off of the semiconductor chip. During a first mode of operation, the first subset of grant lines is driven through the plurality of output pins. During a second mode of operation, the encoded grant lines are driven through the output pins. A variation on the above embodiment includes a number of bus request lines, which are divided into a first subset and a second subset. The first subset of request lines feeds through a number of input pins into the bus arbitration circuit.

Abstract: One embodiment of the present invention provides a method for selectively encoding bus grant lines to reduce I/O pin requirements. The method includes receiving a number of grant lines emanating from a bus arbitration circuit and encoding the grant lines into a smaller number of encoded grant lines. The method selects outputs from between the encoded grant lines and a first subset of the grant lines. These outputs are driven off of a semiconductor chip through a number of output pins. During a first mode of operation, the first subset of grant lines is selected to be driven through the output pins. During a second mode of operation, the encoded grant lines are selected to driven through the output pins. In a variation on the above embodiment, the method additionally receives a number of bus request lines. These request lines are divided into a first subset and a second subset. The first subset of request lines is received through a number of input pins from off of the semiconductor chip.

Abstract: A method and apparatus of improving serial bus efficiency. Improvement of bus efficiency through the reduction of enforced subaction gaps can be accomplished by attaching an explicit end of subaction (EOS) token to packets that are the last packet of a subaction. The EOS should be selected to be an encoding that is not easily confused with any encoding used for normal data encoding. The presence of the EOS token permits arbitration to begin without waiting for a subaction gap after the EOS token is seen on the bus. Additionally, it permits fly by concatenation with packets containing an EOS token. In some cases multiple concatenations are possible. Because the EOS token is independent of subaction type, this technique expands readily as new subactions are developed. Employing the features overall bus efficiency can be increased.

Abstract: According to one embodiment, a computer system comprises a central processing unit (CPU), a memory control hub (MCH) coupled to the CPU, a point to point interface coupled to the MCH; and an input/output control hub (ICH) coupled to the point to point interface. The MCH delays arbitration of a request to access the point to point interface until the access request is received at the ICH, and ICH delays arbitration of a request to access the point to point interface until the access request is received at the MCH.

Abstract: A computer system, method, and controller bus agent for control access to a computer bus. The computer system includes a parallel architecture in which plural bus agents are directly coupled to the computer bus. Each bus agent includes plural bus requester ports each coupled to a different bus requester. As such, the computer system employs a relatively flat, parallel architecture that handles bus requests from the bus requesters in parallel. The controller bus agent includes an internal arbiter and an external arbiter. The internal arbiter arbitrates between bus requests received from the plural bus requesters coupled to the controller bus agent. The external arbiter arbitrates between the bus requests received from other bus agents and from the internal arbiter.

Abstract: A methodology and implementing system are provided in which pipelined read transfers or PRTs are implemented. The PRTs include a request phase and a response phase. The PRT request phase involves a PRT request master delivering to a PRT request target, a source address, a destination address and the transfer size for the data being requested. In the PRT response phase, the PRT request target becomes a PRT response master, i.e. a PCI bus master, and initiates a completion of the transaction that was requested in the originating PRT request. Pipelined read transfers are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlocks.

Abstract: A PCI-to-PCI bridge having a processor configured for performing various routing mode operations based upon the addresses of transactions carried on interconnected PCI buses. The various routing modes operate on decoded PCI addresses and are known as “programmable decode modes.” In one programmable decode mode, private address spaces are defined for allowing two or more devices interconnected to a secondary PCI bus to communicate directly using private transactions. In another programmable decode mode, subtractive routing operations are provided wherein a secondary PCI interface captures any transactions not claimed on the secondary PCI bus after a predetermined number of clock cycles. Another programmable decode mode is “intelligent” bridging wherein conventional inverse positive decode operations are disabled for the entire primary address space of the secondary PCI bus.

Abstract: A data processing system having one or more processor modules and a plurality of shared memory busses to increase its total system performance. Processor modules send bus requests to a bus arbiter, when they attempt to make access to shared memories or memory-mapped peripheral control modules. When such memory access requests are received, the bus arbiter checks the availability of each bus that will be used to reach the requested memories, and send bus grant signals to the requesting processor modules after resolving conflicts, if any. Since the system provides separate paths to reach the individual shared memories, two or more processor modules can be granted their access requests at the same time.

Abstract: A port card employable in a cell switch including a host computer having a processor and a bus for interconnecting a plurality of port cards and a method of switching cells in the cell switch. The port card includes: (1) bus master circuitry for gaining control of the bus to allow the port card to place cells to be switched in the cell switch on the bus and (2) interface circuitry, coupled to the local memory and the bus master circuitry, that places the cells on the bus when the bus master circuitry has gained control of the bus, the cells communicated directly from the interface circuitry to another port card in the cell switch via the bus. The processor (or, more generally, the host computer) is relieved of having to participate directly in switching the cells.

Abstract: A method of providing a lock to a requester, the method including the steps of storing a lock indicator at a storage location on a storage medium; receiving a lock command from a requester on a host computer, wherein the lock command identifies the storage location on the storage medium and represents a lock request; in response to receiving the lock command, retrieving the lock indicator from the storage medium; performing an exclusive OR operation on the lock request and the retrieved lock indicator to produce a lock request result; and sending an indication back to the host computer indicating whether the lock request was granted.

Abstract: A system and method for managing access by a user to a reusable resource. An integer pool is provided, along with program and hardware structures for obtaining an integer from the integer pool, for returning an integer to the integer pool. Responsive to the integer pool being empty, the user is waited. The integer pool includes a NEXT control structure from which a next integer is obtained for use and into which an integer is loaded upon being made available for reuse. The integer pool includes, for holding integers received from or to be provided to said NEXT control structure, (a) a LIFO stack or (b) a linked list by proxy. Reusable resources include data buffers, hardware status bits, logical connections and/or data channels.

Abstract: An adaptive tree-based contention resolution media access control protocol for a local area network using orthogonal frequency division multiplexing. The invention uses constant tones in frequency bins to resolve contention between multiple transmitting nodes. All nodes are synchronized to transmit “contention tones” in a “contention frame.” Each node is assigned a unique identification (ID) number, and this ID number is mapped to frequency bins by transmitting a tone in each bin corresponding to each 1-bit in the binary representation of the node's ID number. The result of multiple nodes each transmitting its unique ID during a contention frame is a complex frequency signal which each participating node decodes. The nodes then participate in a “resolution frame” in which all nodes again transmit tones in frequency bins.

Abstract: An Expandable communications bus system for transferring data between a plurality of devices. The expandable communications bus system is comprised of a plurality of communication busses each capable of transferring n bits of data between devices. A device may be connected to any multiple of the communication busses. Mn bits of data may be transferred at one time between devices using m busses. Other busses in the system transfer can data between other devices while the transfer over m busses is occurring allowing for more efficient use of bus resources. For each communications bus that is connected to a device, the device has an interface that controls the transfer of data over the communications bus. Arbitration for a bus is performed by the interface of each device connected to the bus.

Abstract: A computer system includes a secondary bus bridge device in a portable computer and a another secondary bus bridge device in an expansion base to which the portable computer connects (docks). A peripheral in the expansion base may initiate a delayed cycle to read or write data to memory through a primary bus bridge device that also couples to a CPU. Both secondary bus bridge devices include an arbiter for controlling arbitration of a peripheral bus that connects both secondary bridge devices. The arbiter in the secondary bridge of the portable computer determines which of the arbiters will have arbitration control of the expansion bus to run cycles. When read data is available, in the case of a delayed read cycle initiated by a peripheral device in the expansion base, the primary bridge strobes a delayed cycle control signal to the arbiter in the portable computer which then gives arbitration control to the arbiter in the expansion base.

Abstract: A computer system is disclosed with a host bridge that arbitrates access to a system resource from a CPU via a host bus and from a set of bus agents via a peripheral bus. A separate set of priority classes are provided to the CPU and to the bus agents and programmable timers are included to tune system resource allocation between the host and processor busses.

Abstract: The design of an integrated circuit device is simplified by employing reusable modules to avoid or reduce the need to design special purpose glue logic otherwise needed to interconnect the modules. Functional modules comprise interface circuits that are interconnected by buses and operate according to prescribed bus-access protocols. In a preferred embodiments, bus access is arbitrated in an adaptive manner that may be controlled by a principal module in the device. In other embodiments, bus arbitration is not required. The operation of each functional module may be programmed under the control of the principal module.

Abstract: A method of providing an interconnection between one or more peripheral devices and a system bus of a computer system selectively establishes and removes a connection from a primary peripheral bus to a secondary peripheral buses, and determines a target from among the one or more peripheral devices when a bus bridge is a master of the primary peripheral bus, using an address decoder. Access to and from the primary peripheral bus is controlled using an arbiter to select a master for the primary peripheral bus from among the one or more peripheral devices, to allow both (i) selective establishing and removing of a connection from the primary peripheral bus to one of the secondary peripheral buses in response to the selection of the master, and (ii) isolating of the master prior to establishing the connection to the secondary peripheral bus.

Abstract: By doubling an arbitration circuit for bus access command to be requested to a bus, the number of bus cycles occupied per one bus access command is reduced by one cycle to allow the bus to be operated at high speed. A first in-module arbiter selects a bus access command having the highest priority to be issued to the bus, and a second in-module arbiter selects the bus access command having the highest priority excepting the bus access command previously requested last time by the one module. If the module had already acquired the bus last time, then the result of the second in-module arbiter is selected as a current bus access command. On the other hand, if the module did not acquire the bus last time, then the result of the first in-module arbiter is selected as a current bus access command.

Abstract: A source module, a destination module, or both modules, that are used in a data transfer, signal over an internal communication bus to a bus master when additional time is needed to participate in the data transfer. If either the source module, destination module or both modules require more time, the bus master, in response to an active stretch bus access signal or signals for the module or modules, automatically extends the bus access cycle until all modules requiring additional time signal over the internal communication bus that they are ready to proceed with the data transfer. Consequently, the source module, destination module, or both modules can re-time a bus access cycle to accommodate the characteristics of that particular module. When the addressed storage location in the data transfer comprises a single point address type memory, the addressed module drives an active signal on an address increment disable line in the control bus.

Abstract: A verification system and method for verifying operation of an HDL (Hardware Description Language) design of a computer system component are disclosed. The computer system is configured to interface between a first bus and second bus. During verification, a simulated model of the HDL design is coupled to a simulated first bus and a simulated second bus. A designated stimulus is applied to the simulated model through the simulated first bus. A stimulus file stored in the computer system memory is configured to specify the designated stimulus to be applied. In response to the designated stimulus, the simulated model initiates bus cycles on the simulated second bus. A transaction checker is provided in the computer system memory to receive information relating to these bus cycles from said simulated second bus.

Abstract: A method for hot docking and hot undocking a portable computer and a docking station. The portable computer and docking station are physically coupled via a shared PCI bus and an expansion connector. Varying length pins in the expansion connector generate docking and undocking handshaking signals used by microcontrollers in the portable computer and docking station. The portable computer and docking station are functionally connected via low onresistance switches located in the portable computer. Following a docking event, closure of the switches connects the portion of the shared PCI bus in the docking station with the PCI bus in the portable computer. When the switches are open, the PCI busses are functionally isolated. Both the portable computer and the docking station also include a local arbiter for arbitrating and granting bus control requests from devices coupled to the shared PCI bus.

Abstract: A data storage system wherein a main frame computer section having main frame processors for processing data is coupled to a bank of disk drives through an interface. The interface includes a bus having: an bus-select/address/command portion; bus-grant/data/clock-pulse portion; a bus queue portion; and an ending-status portion. A plurality of addressable memories is coupled to the bus. A plurality of controllers is coupled to the bus. Each one thereof being adapted: to assert on the bus-select/command/address portion of the bus, during a controller initiated bus select assert interval, a command. The addressed memory is adapted to produce on the queue portion of the bus a queue signal a predetermined time after a controller initiated bus select assert interval. The queue signal terminates the bus select interval. Another one of the controllers is adapted to provide on the bus-select/address/command portion of the bus another address and command after the queue signal terminates the bus select assert interval.

Abstract: A CAM including a set of priority registers for storing information from one port and a set of non-priority registers for storing information from a second port. The CAM also includes a memory array that is coupled to both sets of registers. A port arbiter within the CAM determines which set of registers is given access to the memory array. Also described is a method for controlling access to the memory array. A lock interval is indicated before the priority registers initiate access to the memory array. During the lock interval, access to the memory by the non-priority registers is delayed if the access cannot be completed before the priority registers begin access.

Abstract: It is determined that, when starting of direct memory access is newly requested, whether or not the direct memory access can be started, using a rate of using the bus at the present time by data transfer performed by all the direct memory access controllers which have already started direct memory access until then and all the processors, a data transfer rate needed by the newly requested direct memory access, a size of data which is transferred in one direct memory access operation or a size of data which a memory can accept, a latency for accessing the memory, and a latency for bus-right arbitration. The newly requested direct memory access is started when it is determined that the direct memory access can be started. Starting of the newly requested direct memory access is kept waiting when it is determined that the direct memory access cannot be started.

Abstract: A memory control system comprises a main memory including a plurality of banks; two or more requesters each of which includes an MPU or an I/O section which outputs a request that is addressed to a bank of the main memory; and a pipeline-controlled system bus connecting the main memory and each requester. Each requester includes a request sending control circuit, a system bus arbitration circuit, and a bank busy management section. The request sending control circuit which received a request from the MPU or the I/O section executes a system bus acquisition request to the system bus arbitration circuit of the requester and other requesters after confirming that the bank to which the request has been addressed is not busy for the request by referring to the bank busy management section.

Abstract: An improved I/O processor (IOP) delivers high I/O performance while maintaining inter-reference ordering among memory reference operations issued by an I/O device as specified by a consistency model in a shared memory multiprocessor system. The IOP comprises a retire controller which imposes inter-reference ordering among the operations based on receipt of a commit signal for each operation, wherein the commit signal for a memory reference operation indicates the apparent completion of the operation rather than actual completion of the operation. In addition, the IOP comprises a prefetch controller coupled to an I/O cache for prefetching data into cache without any ordering constraints (or out-of-order). The ordered retirement functions of the IOP are separated from its prefetching operations, which enables the latter operations to be performed in an arbitrary manner so as to improve the overall performance of the system.

Abstract: A multiprocessor system of the present invention has an address bus, a data bus, first and second processors, four access queues, first and second arbiters, and a shared memory divided into four banks. The four access queues are constituted by first-in first-out memories for buffering a plurality of access-request addresses transmitted through the address bus. When a processor requires data from the memory bank, the processor sends a processor ID with a data access request. When the memory bank sends data in return, the memory bank outputs the processor ID of the request originator with the required data. Even if continuous access requests are addressed to one bank of the shared memory, a succeeding access requested need not wait for a previous access request to be finished. According, the throughput of the system can be improved greatly. The first and second arbiters serve to decide ownership of buses.

Abstract: An arbiter uses a history based bus arbitration scheme to more fairly allocate a shared resource among multiple devices. The arbiter uses a history queue to dynamically update the priorities of the devices using the shared resource, and makes the grant decision in a single calculation using the combination of the history queue and requests from bidding devices. The priority for granting master to each device is dynamically modified so that the least recently serviced requestor will be granted the shared resource. A hidden arbitration scheme provides more fair history based resource allocation. A bus retry scheme demotes priority for processing devices that are assigned bus master but do not perform bus operations within a predetermined number of clock cycles. The arbiter also prevents bus grants during hot swap operations.

Abstract: An apparatus is provided that improves memory storage and access speed by repackaging various types of memories, SRAM, DRAM, and Disk, into a single storage unit. Each unit contains a slice of all the various memories along with programmable logic to control the accessing of the memories. This unit appears to the central processing unit (CPU) of a computer system as an extremely large secondary cache. Independent management of each unit greatly reduces bus traffic to implement any particular address space. By using a plurality of these memory units, an extremely large amount of memory can be accessed by the CPU with the speed of accessing a cache system.