Abstract: An arbitration method for access to a serial bus includes the steps of monitoring for the presence of an arbitration reset gap on the serial bus, and arbitrating for an access, if needed, upon recognizing the presence of an arbitration reset gap on the serial bus. The method further comprises the steps of determining if immediately arbitrating for an additional access without waiting for the presence of another arbitration reset gap on the serial bus is authorized, upon successfully arbitrating for an access. If immediately arbitrating for an additional access is authorized, and the additional access is needed, arbitration for the additional access is immediately made. A method for controlling arbitration for access to a serial bus includes the step of programming bus agents with information for the bus agents to determine whether immediately arbitrating for additional accesses to the serial bus are authorized.

Abstract: A process and implementing computer system in which an arbitration circuit is comprised of a plurality of state machines 301, 303 and 305 which combine to receive various system timing signals and provide a data bus grant signal effective to enable data streaming of sequential data blocks of information from an L2 cache memory 109 without intervening wait states between the data blocks.

Abstract: A shared resource lock mechanism is provided which enables processors in a multi-processor system which each share common resources to obtain locks on those resources using a transactions which minimizes the amount of time system resources are unavailable, while also allowing system resources to be available for other processing tasks.

Abstract: Low-latency distributed round-robin arbitration is used to grant requests for access to a shared resource such as a computer system bus. A plurality of circuit board cards that each include two devices such as CPUs, I/O units, and ram and an address controller plugs into an Address Bus in the bus system. Each address controller contains logic implementing the arbitration mechanism with a two-level hierarchy: a single top arbitrator and preferably four leaf arbitrators. Each address controller is coupled to two devices and the logical "OR" of their arbitration request is coupled via an Arbitration Bus to other address controllers on other boards. Each leaf arbitrator has four prioritized request in lines, each such line being coupled to a single address controller serviced by that leaf arbitrator. By default, each leaf arbitrator and the top arbitrator implement a prioritized algorithm.

Abstract: In a computer including two buses, a main memory, a write back cache, and a peripheral device, a method and apparatus for providing an inter-bus buffer to support successive main memory accesses from the peripheral device is disclosed. The buffer is included in a bridge device for interfacing the two computer buses and controlling when the peripheral device may access the main memory. When the peripheral device attempts to read data from the main memory that is duplicated in the cache and that has become stale, the bridge device initiates a write back operation to update specific data portions of the main memory corresponding to the read request. The bridge device uses look-ahead techniques such as bursting or pipelining to streamline the data coming from the cache to the main memory and to the peripheral device.

Abstract: This invention presents the serial arbitration method and system for rapidly and accurately identifying a station with the highest priority when a plurality of stations with different transmission rates are simultaneously requesting the use of a bus in a multi-point communication network where a plurality of communication stations share a common serial bus.This invention intends to improve the bus throughput by not only avoiding the collision of signals in a common serial bus, but also removing the possibility of arbitration failures when a plurality of contending stations have different transmission rates.For this purpose, a plurality of contending stations transmit modulated unique identity address serially in a form of self-clocking pulse on the OR-type single channel bus when the arbitration start signal is detected in multi-point networks.

Abstract: An arbitration scheme for a computer system having multiple arbiters for arbitrating access to a plurality of buses. In the preferred embodiment, a computer system is divided into a detachable laptop portion and an expansion base unit coupled through a shared PCI bus. Each of the two portions of the computer system includes separate PCI arbitration circuitry for arbitrating requests for the PCI bus from potential PCI and ISA bus masters. Included within the laptop portion of the computer system is a top level arbiter that determines whether the PCI arbiter in the laptop or expansion base unit has access to the PCI bus. Either PCI arbiter normally must receive a grant from the top level arbiter before it runs a cycle. While the laptop computer is docked, the top level arbiter selects between the PCI arbiters on an essentially time multiplexed basis. While the expansion base and laptop computer are undocked, the top level arbiter grants bus access to the laptop PCI arbiter.

Abstract: A communication system and method of communicating including a slave function connected to a master function by a single address bus, a write data bus and a read data bus so as to allow for overlapping multiple cycle read and write operations between the master function and the slave function. Preferably the communication system includes a plurality of slave functions connected to a master function by the single address bus, the write data bus and the read data bus. A plurality of master functions may be connected to the slave functions through a bus arbiter connected to the plurality of master functions by an address bus, a write data bus and a read data bus for each master function. The bus arbiter receives requests for communication operations from the plurality of master functions and selectively transmits the communication operations to the slave functions.