Abstract: It becomes possible for a user to set a transmission or reception channel arbitrarily and easily. Each of equipment connected to an IEEE 1394 bus may include a register provided within a RAM 113 to thereby set a transmission or reception default channel. If channels used in the transmission and the reception are not set when the transmission is started, then default channel may be used. When equipment is set to a channel setting mode by operating an operation section 116, a control section 112 may display a channel setting picture on a display section 115. In this state, a user may select a set channel by operating an up-key 116a and a down-key 116b of the operation section 116. Thereafter, when a user operates a “YES” key 116c, the control section 112 may write a selected channel in the above-mentioned register, and ends a default channel setting operation. A user can set the transmission or reception channel arbitrarily and easily.

Abstract: Systems and methods for multiple input instrumentation buses are disclosed. In one embodiment, a bus assembly includes a control module adapted to be coupled to a network, and a plurality of nodes operatively coupled in a linear topology. A plurality of interface modules are coupled to the nodes. At least one node is adapted to receive a primary response signal from the correspondingly coupled interface module, and a secondary response signal from at least one other node, and to determine which of the primary and secondary response signals arrived first, and to output a corresponding one of the primary and secondary response signals that arrived first.

Abstract: A system and method for guaranteeing transactional fairness among multiple requesters contending for a common resource in a cache-coherent multiprocessor system is described. Batch processing is used to control servicing of multiple requests made by multiple requesters (such as processors) of a common resource in a cache-coherent multiprocessor system. Specifically, identification numbers are assigned to requests as they are received from the multiple requesters. The identification numbers are then used in conjunction with batch processing to prioritize and guarantee servicing of the requests.

Abstract: In one embodiment, a node comprises a first network interface and a second network interface. The node further comprises a first bus guardian that asserts a first bus guardian signal when the second network interface is allowed to transmit and a second bus guardian that asserts a second bus guardian signal when the first network interface is allowed to transmit. The first network interface is not allowed to transmit unless the second bus guardian asserts the second bus guardian signal. The second network interface is not allowed to transmit unless the first bus guardian asserts the first bus guardian signal.

Abstract: The invention is essentially a motherboard design for personal computers which uses DSP hardware in conjunction with a general or specific purpose CPU to process command and continuous speech. The DSP hardware serves as a bridge between the audio input of the sound card or integrated sound module and the microprocessor. The DSP chip itself can serve as a processor and embedded speech engine for processing command and control speech. It can also serve as a pre-processor for continuous speech, converting the digital bit stream representing the speech to phonemes for processing by the CPU and software-based speech engine and can facilitate digital mobile phone functions and text to speech conversion.

Abstract: According to embodiments of the present invention, a peripheral component interconnect (PCI) standard hot-plug controller (SHPC) includes a command register to store PCI slot operation commands for one or more target PCI slots and a programmable register that may be programmed with one timing parameter value (e.g., Tpccc, Tpece, Tcebe, Tbkrk, etc.) for a signal sequence for execution of one PCI slot operation command and another timing parameter value for a signal sequence for execution of another PCI slot operation command depending on the particular target PCI slot, the particular PCI slot operation command loaded into the command register, and/or the number of times a particular PCI slot operation command has been loaded into the command register, for example.

Abstract: In wireless USB data transfers over UWB, software configures hardware thresholds to control data transfer in a manner that uses bandwidth for good connections over bad connections, given the high error rate experienced with wireless USB. Periodic transfers are first attempted before asynchronous transfers, as long as the periodic transfers are successful. When failures are occurring, the hardware includes a mechanism having a software-configurable threshold specifying the number of errors a given endpoint can tolerate before it is paused in the schedule. By pausing transfer attempts that are likely to again fail, endpoints with successful transfers are favored over those experiencing errors. When the number of active transfers pending exceeds a software-configurable notification threshold for isochronous endpoints, the hardware notifies the software of this state, corresponding to a low-buffer condition at the receiver.

Abstract: Systems and methods for controlling access by a set of agents to a resource, where the agents have corresponding priorities associated with them, and where a monitor associated with the resource controls accesses by the agents to the resource based on the priorities. One embodiment is implemented in a computer system having multiple processors that are connected to a processor bus. The processor bus includes a shaping monitor configured to control access by the processors to the bus. The shaping monitor attempts to distribute the accesses from each of the processors throughout a base period according to priorities assigned to the processors. The shaping monitor allocates slots to the processors in accordance with their relative priorities. Priorities are initially assigned according to the respective bandwidth needs of the processors, but may be modified based upon comparisons of actual to expected accesses to the bus.

Abstract: A system prevents disruption of one or more system buses. The system monitors communication on the one or more system buses during an input mode and an output mode and detects changes between the input mode and the output mode. The system determines whether a predetermined time period has elapsed after a change from the input mode to the output mode and changes from the output mode to the input mode when the predetermined time period has elapsed after a change from the input mode to the output mode.

Abstract: A bus system has a bus, a number of units which can be connected to one another via the bus, and a bus controller. The units request the bus controller for bus access when they require a connection to one or more other units, and the bus controller decides which unit will be allocated to the bus. The bus system is distinguished in that at least some of the units which can request bus access are allocated values which indicate how long and/or how frequently the relevant unit can be allocated the bus or has been allocated the bus, and in that these values are used to decide whether a unit which is requesting bus access is allocated the bus, or whether a unit which requires bus access is requesting the bus at all.

Abstract: An invention is provided for hiding an input/output device from an operating system. A window of time is provided wherein a specific input/output processor (IOP) has exclusive access to a bus. An IOC memory map register, which is utilized by an input/output chip (IOC), is configured during the window of time using the IOP. In addition, a hide indicator is configured to indicate the IOC should be hidden. In this manner, data is communicated between the IOP and the IOC using the IOC memory map register. In one aspect, the hide indicator can be configured, before the window of time, to indicate the IOC should be hidden. In addition, the hide indicator can be configured during the window of time to indicate the IOC should be exposed.

Abstract: A method and apparatus are disclosed for performing dynamic arbitration of memory accesses by a CPU and at least one bus master interface module based on, at least in part, monitoring a CPU throttle control signal and monitoring CPU power and performance states, and making decisions based on the monitored parameters. Bus master memory access break events and memory read and write accesses are also monitored as part of the arbitration process in accordance with certain embodiments of the present invention. An arbitration (ARB) module performs the dynamic arbitration. A CPU throttle control module generates the CPU throttle control signal, indicating when the CPU is idle, and also monitors and outputs the CPU power and performance states. A memory controller (MC) module controls accesses to the memory subsystem based on, at least in part, the dynamic arbitration performed by the dynamic arbitration module.

Abstract: A bus has a local section (10a,b) and a shared section (11a,b). An arbiter circuit (16) issues an arbited grant (25) to access the shared section (11a,b) in response to a request (22) to perform a bus access transaction. A bus station (12) has a request output (17a) for issuing the request to the arbiter (16), the bus station (12) having a grant input (19c) arranged to receive a local grant (24) in response to the request (22), independently of the arbited grant (25). The bus station (12) is arranged to start the transaction, applying an address to the local section (10a,b) in response to the local grant (24) in a bus cycle following the local grant (24). A bridge circuit (16) provides a coupling between the local section (10a,b) and shared section (11a,b). The bridge station receives the arbited grant (25) and enables the coupling to pass the address to the shared section (11a,b) in said bus cycle conditional on the arbited grant (25).

Abstract: A method for use with a computer system includes permitting a first bus agent to access a bus during predetermined windows of time and preventing a second bus agent from accessing the bus outside of the windows. The first bus agent has a higher priority than the second bus agent. The method includes monitoring the use of the bus by the first bus agent during the window and the regulation durations of the windows are selectively regulated based on the use.

Abstract: A transmission managing apparatus included in an information transmitting system comprising a communication bus (B), an indicating device (NI), which has a transmission state memory (5) for storing a channel used for an information transmission executed in a time division manner on the communication bus and a transmission occupation period occupied for the information transmission, for indicating the channel and the transmission occupation period and an information processing apparatus (N) for reserving a non-used channel and a preservable period, while referring to a memory content of the transmission state memory.

Abstract: A method and device for the exchange of data in messages between at least two users which are connected by a bus system and have separate time bases, the messages containing the data being transmitted by the users via the bus system; and a first user, in a function as timer, controls the messages as a function of time in such a way that it repeatedly transmits a reference message, which contains time information regarding the time base of the first user, via the bus at a specifiable time interval; the at least second user forms its own time information, using its time base, as a function of the time information of the first user; a correction value is ascertained from the two pieces of time information; and the second user adapts its time information and/or its time base as a function of the correction value.

Abstract: Data is received which is transmitted through a serial bus in a predetermined transmission band. The serial bus is preferably in conformity with the IEEE 1394 standards. One of recording modes for different recording rates is selected in accordance with the transmission band of the received data. The data is recorded in the selected recording mode. Data is reproduced which has been recorded in a recording mode for a predetermined recording rate. A transmission band is allocated, based on the recording mode, for transmitting the data through a serial bus.

Abstract: A signal communication device for use within a computer includes a set of optical fibers configured to form an optical computer bus between a set of computer sub-system elements of a computer. A set of input optical connector cards are connected to the set of optical fibers. Each of the input optical connector cards includes a transmitting dynamic bandwidth allocator responsive to an optical bus clock signal operating at a multiple of a computer system clock signal such that a set of bus time slots are available for each computer system clock signal cycle. The transmitting dynamic bandwidth allocator allows a light signal to be applied to the optical computer bus during a dynamically assigned bus time slot. In this way, the optical computer bus bandwidth can be dynamically allocated to different computer sub-system elements during a single computer system clock signal cycle.

Abstract: An application specific integrated circuit, ASIC, having an advanced high-speed bus, AHB, operating in Advanced Microcontroller Bus Architecture, AMBA, and a bridge for connecting to an off-chip device is disclosed. The bridge includes a logical section and a buffer section for modifying AMBA signals to accommodate the differing clock speeds, voltages and signals required by the off-chip device. The logic section includes clock division and registers to store variables identifying the off-chip device and data being transferred from the AHB to the off-chip device. The buffer section provides any conversion of signal voltage levels between the core ASIC voltages and the input/output voltages required by the off-chip device.

Abstract: The present invention is directed to a method and apparatus for scheduling a resource to meet quality of service guarantees. In one embodiment of three levels of priority, if a channel of a first priority level is within its bandwidth allocation, then a request is issued from that channel. If there are no requests in channels at the first priority level that are within the allocation, requests from channels at the second priority level that are within their bandwidth allocation are chosen. If there are no requests of this type, requests from channels at the third priority level or requests from channels at the first and second levels that are outside of their bandwidth allocation are issued. The system may be implemented using rate-based scheduling.

Abstract: A networking method is disclosed. At least one silent slot is included in either a collision detection prefix disposed before a preamble of one or more frames of data to be transmitted across a media or in the one or more frames of data to be transmitted across the media. Transmission collision is detected during the at least one silent slot included. In one embodiment, the method is embodied in a network interface controller having a media access control block to control access to a media, and a physical signal block to physically signal data to be transmitted. The media access controller includes the at least one silent slot in either the collision detection prefix or in the data, and the physical signaling block performs the transmission collision detection during the included at least one silent slot.

Abstract: A system is configured to prioritize streaming disk I/O over non-streaming disk I/O by providing high priority queuing to streaming disk I/O and/or to throttle non-streaming disk I/O when the total disk I/O (streaming+non-streaming) exceeds a threshold amount for a given time quantum. When disk throttling is utilized, streaming disk I/O is processed in a first time quantum. Non-streaming disk I/O is processed, as much as possible, in the remainder of the first time quantum. Other non-streaming disk I/O remaining to be processed is deferred to a subsequent time quantum.

Abstract: A processing system comprises: a shared system resource; a plurality of control devices, each assignable with a task having a predetermined maximum time to complete, the control devices time sharing the system resource in the process of performing their assigned tasks in accordance with a predetermined sequence; and an arbiter circuit for regulating access of said control devices to the system resource. Each control device includes a throttle circuit coupled to the arbiter circuit and individually programmable to control in cooperation with the arbiter circuit utilization of the system resource by the corresponding control device so that each control device may perform its task within the predetermined maximum completion time thereof.

Abstract: Circuits and associated methods for operation thereof for gathering real-time statistical information regarding operation of the arbiter circuit in a particular system application. The real-time statistical information so gathered is useful for off-line analysis by a system designer for determining optimal configuration and parameter values associated with operation of a particular arbiter in a specific system application. In a first exemplary preferred embodiment, a timer circuit associated with the arbiter measures a predetermined period of time during which statistical data is to be gathered. Counter circuits associated with the arbiter count the number of occurrences of events of interest to the designer during the time period measured by the timer circuit. Each counter circuit preferably senses and counts a particular event of interest to the designer.

Abstract: A multimedia bus is an internal bus for which two transfer modes, a band-guaranteed cycle and an event-driven type asynchronous (async) cycle, are defined. In the band-guaranteed cycle, stream data is transferred between nodes in peer-to-peer mode by using a reserved band for each cycle time. There are three ways to control the band-guaranteed cycle using the reserved band cycle: (1) flow control for stopping data transmission in a reserved band cycle under the control of a receiver node, (2) control for executing a stream access in the async cycle and (3) control for accepting the async cycle even during the reserved band cycle. This can permit data transfer between nodes on the internal bus in peer-to-peer mode, thereby improving the performance of a system which deals with both an AV stream and computer data.

Abstract: In a storage environment or storage area network having multiple host devices and at least one storage array, the host devices access logical data volumes stored on the storage array through array controllers disposed in the storage array. Multiple host devices can request access to shared ones of the logical data volumes through multiple paths to multiple array controllers, but each logical data volume is controlled or owned by only one array controller at a time. Thus, ownership of shared logical data volumes is transferred between the array controllers as necessary on behalf of the requesting host devices. To prevent ownership transfers from occurring too often, however, ownership of the logical data volumes is made exclusive, or “sticky,” for a period of time after each transfer. During the exclusive ownership period of time, the ownership cannot be transferred.

Abstract: A method for use with a computer system includes permitting a first bus agent to access a bus during predetermined windows of time and preventing a second bus agent from accessing the bus outside of the windows. The first bus agent has a higher priority than the second bus agent. The method includes monitoring the use of the bus by the first bus agent during the window and the regulation durations of the windows are selectively regulated based on the use.

Abstract: A synchronous dynamic random access memory (“SDRAM”) operates with matching read and write latencies. To prevent data collision at the memory array, the SDRAM includes interim address and interim data registers that temporarily store write addresses and input data until an available interval is located where no read data or read addresses occupy the memory array. During the available interval, data is transferred from the interim data register to a location in the memory array identified by the address in the interim array register. In one embodiment, the SDRAM also includes address and compare logic to prevent reading incorrect data from an address to which the proper data has not yet been written. In another embodiment, a system controller monitors commands and addresses and inserts no operation commands to prevent such collision of data and addresses.

Abstract: A transmission managing apparatus included in an information transmitting system comprising a serial bus, an IRM node, which has a resource register for storing a channel used for an information transmission executed in a time division manner on the serial bus and a transmission occupation period occupied for the information transmission, for indicating the channel and the transmission occupation period and a general node for insuring a non-used channel and a preservable period, which is the transmission occupation period, that can be occupied, while referring to a memory content of the transmission state memory, to thereby carry out the information transmission. The transmission managing apparatus is provided with: a comparator for monitoring whether or not the memory content is updated; and a command generator for reporting a fact of the updating through the serial bus to the general node when updated.

Abstract: A device for arbitrating access to a resource by a plurality of agents includes logic configured to associate requesting ones of the agents with access tokens. The number of the access tokens assigned to each requesting agent is proportional to its bandwidth or speed in comparison with the other requesting agents. A is selector configured to sequence through the access tokens and select respective ones of the requesting agents associated with the access tokens. The logic may dynamically reconfigure token allocation and distribution to only those agents having a pending service request or may skip tokens allocated to agents not having a pending request. The distribution of tokens is preferably uniform over the total bandwidth space of the agents or requesting agents. In one implementation tokens are in the form of binary numbers.

Abstract: A technique to reduce accumulated latencies in bus transmission time when a bus inversion scheme is employed. The bus inversion scheme inverts all the data bits whenever more than one-half of the data bits are active, so that the bus never has more that one-half of the bits active during a data transfer. This minimizes the number of driver circuits that are actively driving the bus at any given time. Since it takes a certain amount to time to determine if more than one-half of the bits are active, this process can add to overall latency, or data transfer time on the bus. By placing the bus inversion function in parallel with another function that also contributes to bus latency, such as error correction code (ECC) calculation, only the more time-consuming of the two functions will increase bus latency.

Abstract: Data is received which is transmitted through a serial bus in a predetermined transmission band. The serial bus is preferably in conformity with the IEEE 1394 standards. One of recording modes for different recording rates is selected in accordance with the transmission band of the received data. The data is recorded in the selected recording mode. Data is reproduced which has been recorded in a recording mode for a predetermined recording rate. A transmission band is allocated, based on the recording mode, for transmitting the data through a serial bus.

Abstract: A method and apparatus allowing two independent arbiters which do not directly talk to one another to function on a common system bus, allowing efficient operation of a master controller, and virtually endless capability to add peripherals to the common system bus without problems or major modifications commonly associated with additional arbitration overhead. A master controller sets time slot parameters for an external, subordinate arbiter as often as desired. Based on the time slot parameter information, the subordinate arbiter functions on an electrically separated portion of the common system bus during all times but for a time slot associated with communication of the super arbiter over the entire common system bus. During this time, a tri-state buffer element allows communication between portions of the common system bus.

Abstract: Several peripheral entities are provided, with each peripheral entity being clocked by its own internal clock signal and being able to access a single-access memory. A priority entity is defined from among the peripheral entities, and the other peripheral entities are defined as auxiliary entities. A repetitive time frame is formulated, regulated by the internal clock signal of the priority entity, and subdivided into several groups of time windows that are allocated to the peripheral entities. One of the peripheral entities is a microprocessor that is disabled for a fixed duration after each memory access request.

Abstract: A method and apparatus allowing two independent arbiters which do not directly talk to one another to function on a common system bus, allowing efficient operation of a master controller, and virtually endless capability to add peripherals to the common system bus without problems or major modifications commonly associated with additional arbitration overhead. A master controller sets time slot parameters for an external, subordinate arbiter as often as desired. Based on the time slot parameter information, the subordinate arbiter functions on an electrically separated portion of the common system bus during all times but for a time slot associated with communication of the super arbiter over the entire common system bus. During this time, a tri-state buffer element allows communication between portions of the common system bus.

Abstract: A memory subsystem includes a buffer, a storage device, a buffer access determining mechanism, a request communicator, and a disk input/output subsystem. The buffer comprises a buffer channel having a limited data transfer rate. The storage device comprises a read/write mechanism and non-volatile storage media. The determining mechanism determines when a given client is to be given access to the buffer channel. It comprises a latency monitor for monitoring a latency parameter indicative of the buffer channel access latency for the given client and a buffer access controller for controlling when the given client is given access to the buffer channel in accordance with the monitored latency parameter. The request communicator couples requestors to the buffer access determining mechanism. The requesters request the buffer access determining mechanism to give clients access to the buffer channel.

Abstract: To transfer information between modules which are connected to a common bus, the module that wants to send information sends a request signal via a common bus request line. The module (bus master) which controls the bus activities, receives this signal, sends a command via the bus to all bus users, and thus starts a cycle of clock pulses. A particular clock pulse within a cycle is assigned to each bus user, during which it can send or receive one signal each along one or several predefined bus lines (FIG. 1).

Abstract: A method of transferring data in a network computing environment having a controlling program and a main storage in processing communication with an interface element including one or more adapters. A queuing mechanism is first established in the main storage for asynchronous transmittal of data between the program and said interface element. At least one queue-set is dedicated to input data and another queue-set to output data in the queuing mechanism. Queuing priorities both for said input and output queue-sets are then determined according to importance of data to be processed or transferred or other internal dependencies and a queue-description record is established by passing a QDIO queue command. From this the priority and number of the output queue are provided by order in which the order specified in the queue descriptor record relative to any other output queues described in that record.

Abstract: A method and an apparatus for timely and accurate processing of data in a network computing environment controlled by a running program and having a queuing mechanism established in a main storage. The main storage is in processing communication with an interface element having one or more adapters. At least one set of queues in the queuing mechanism is designated for input and another set for output. A signal adapter instruction can be issued to provide initiative to check content of any or all queues in the mechanism. With the help of the signal adapter an initiate-output can be specified when appropriate and the associated adapter can then asynchronously process the input or the output queues. A synchronize option is also available to signal the associated data queues to update all entries in order to render them current as observed by both the adapter and the controlling running program.

Abstract: A computer program device and product is provided for timely processing of data. The computer program device comprises a program storage device readable by a digital processing apparatus and a program means including instructions executable by the digital processing apparatus by designating at least one set of queues in the queuing mechanism as input queues and another as output queues; issuing a signal adapter instruction to provide initiative to check content of any or all queues in the queuing mechanism; specifying initiate-output or initiate-input appropriately by means of said signal adapter instruction to cause associated adapter to asynchronously process said output or input queues; and causing synchronization by means of said signal adapter instruction by signaling the associated data queues to update all entries in order to render them current.

Abstract: In the novel device and the novel method the data to be transmitted is transmitted in units together with information that is required or useful for the transmission and/or the use of the data. At least some of the units comprise at least one region which defines a time slot within which freely selectable devices can output onto the bus data representing freely selectable information at freely selectable points in time.

Abstract: A processing system comprises: a shared system resource; a plurality of control devices, each assignable with a task having a predetermined maximum time to complete, the control devices time sharing the system resource in the process of performing their assigned tasks in accordance with a predetermined sequence; and an arbiter circuit for regulating access of said control devices to the system resource. Each control device includes a throttle circuit coupled to the arbiter circuit and individually programmable to control in cooperation with the arbiter circuit utilization of the system resource by the corresponding control device so that each control device may perform its task within the predetermined maximum completion time thereof.

Abstract: Improved techniques for controlling buses of a computer system are disclosed such that peripheral devices (and/or their associated buses) can be connected or disconnected to the computer system while the computer system is active. The peripheral devices are connected to the computer system by being inserted into a slot or other receptacle of the computer system. The peripheral devices are disconnected from the computer system by being removed from a slot or other receptacle of the computer system. The slots or receptacles typically includes connectors designed to receive peripheral devices, such as PC CARD slots, expansion bays, and the like. Given that the peripheral devices can be inserted or removed while the computer system is active is active, the computer system according to the invention permits “hot-plugging” of peripheral devices. The invention is particularly well suited for controlling PCI buses for peripheral devices connecting to a computer system by way of peripheral ports.

Abstract: Multimedia applications including a video and an audio are transmitted at respective adapted transfer rates in a server connected with a networks. The server operates on an operating system which permits a multithreading by allocating time slices to thread. For each application, data on a required transfer rate indicative of a permitted lowest transfer rate for the application is prepared. Threads are generated for respective applications. An initial number of slices are allocated to each thread to let said threads transmit said respective applications. A transfer rate of each thread is measured at a time interval. A number of slices to be allocated to each thread is calculated such that the measured transfer rate of each thread (i.e., each application) becomes equal to the required transfer rate of the application transmitted by the thread.

Abstract: A communication system includes a communication control section which may receive bus use requests of both of a DV camera/recorder (50) which becomes an output machine on a serial bus (60D) and a DV deck (40) which becomes an input machine on the serial bus (60D), may check whether or not the serial bus (60D) which were requested to be used is in use, may open the serial bus (60D) to the DV camera/recorder (50) and the DV deck (40) which issued the use requests, may protect a connection between the DV camera/recorder (50) and the DV deck (40), may open a serial bus (60A) to an IRD receiver (10) and a mini disc (20) which issued use requests and which may protect a connection between the IRD receiver (10) and the mini disc (20).

Abstract: A register associated with the architected logic queue of a memory-coherent device within a multiprocessor system contains a flag set whenever an architected operation—one which might affect the storage hierarchy as perceived by other devices within the system—is posted in the snoop queue of a remote snooping device. The flag remains set and is reset only when a synchronization instruction (such as the “sync” instruction supported by the PowerPC™ family of devices) is received from a local processor. The state of the flag thus provides historical information regarding architected operations which may be pending in other devices within the system after being snooped from the system bus. This historical information is utilized to determine whether a synchronization operation should be presented on the system bus, allowing unnecessary synchronization operations to be filtered and additional system bus cycles made available for other purposes.

Abstract: A data recording and reproducing apparatus capable of coping with various applications has been difficult to be realized.

Abstract: In an information processing system, a wait state signal is inserted into a RDY signal, according to which data are transmitted through memory and I/O buses. A CPU controls the number of the wait state signal to adjust the difference of the transfer speeds of the memory and I/O buses. An MCU (Memory Controller Unit) includes configuration and refresh timer registers for specifying the configuration and the refresh cycle of a memory to be accessed.

Abstract: A solution to the problem of undesired serialization of bus controlled instrument measurement delays for multiple instances of programmatically controlled measurement processes is to configure the bus operations and the control programs to allow the issuance of a command within the context of a first collection of such instruments, without having to wait for the corresponding data before issuing commands within the context of a second collection. This is done by instructing the equipment in the collection to signal that they have data instead of the more customary immediately issued "@ address talk", which is then followed by the delay needed by the equipment to make the measurement. Instead, the "have data" signals are associated with the devices that originated them and then the bus instructions that request the data are issued. In conjunction with this, the usual bus I/O commands in the controlling programs may be replaced with calls to a library that operates in just this fashion.

Abstract: The invention relates to a method and system by means of which a large number of peripheral modules (TRn) can request service from a controller, e.g. in form of an interrupt request. Congestion of service requests is prevented in advance by assigning a predetermined time slot to each peripheral module (TRn) during which it is allowed to ask for service from the controller. The time slots are coordinated by a time slot counter which is stepped with a clock signal (CLK). The time slot counters of the different peripheral modules are synchronized with a synchronization signal (SYNC). The peripheral modulees (TRn) may include subperipheral modules, whereby each subperipheral module can request service independently, or a gate N1 coupled to a register SR1 may be employed for detecting that a subperipheral module requires service.