Abstract: A method and apparatus for maximizing the performance of DMA transfers over a PCI.TM. bus are provided which includes a Per-Channel Retry count, Double Buffer Management, Wait Enable functionality, Back Up register functionality, Gather/Scatter mapping, a method for minimization of PIO writes, Read Semaphore functionality, a method for servicing of DMA transfers during FMU latency periods, Valid bit functionality, high and low water thresholds, and re-usable page tables.

Abstract: A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and also includes a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The multimedia bus is preferably time sliced wherein time slices or time slots are allocated in proportion to the required bandwidth. Each multimedia device includes programmable time slotting logic which determines the appropriate time slot. In one embodiment, the time slices are each a constant size and a number of the equal sized time slots are allocated to respective data streams in proportion to the required bandwidth. Alternatively, the time slots are dynamically sized or allocated to data streams in proportion to the required bandwidth.