Abstract: Provided are techniques for interrupt processing. An Input/Output device determines that an event has occurred. The Input/Output device determines a state of an event data structure. The Input/Output device writes an event entry into the event data structure in response to determining that the event has occurred. After writing the event entry, the Input/Output device determines whether to generate an interrupt or not based on the state of the event data structure. Additionally provided are techniques for interrupt processing in which an I/O device driver determines that an interrupt has occurred. The I/O device driver reads an event entry in an event data structure in response to determining that the interrupt has occurred. The I/O device driver updates a state of a structure state indicator to enable/disable interrupts.

Abstract: A dynamic priority scheme is provided that uses information including the status of the target and data availability in deciding which PCI master should be assigned ownership of the bus. The target uses delayed transactions to complete a read access targeted to it. The target also integrates a buffer management scheme, in one embodiment an input/output cache, for buffer management. The present invention optimizes the performance and utilization of the PCI bus.

Abstract: Various methods and apparatuses are described in which an arbitration controller cooperates with arbitration logic. The arbitration controller has a plurality of inputs that receive one or more transactions from a plurality of blocks of functionality. The arbitration controller arbitrates requests for access to a shared resource amongst the plurality of blocks of functionality by implementing an arbitration policy. The arbitration policy groups the transactions from the plurality of blocks of functionality into global groups of transactions for servicing by that shared resource. All of the transactions in a first global group are serviced by that shared resource prior to servicing transactions in a next global group of transactions. The arbitration logic facilitates the arbitration policy. The arbitration logic includes cascaded arbitration units that hierarchically arbitrate for the shared resource.

Abstract: An integrated circuit for a smart card may include a transceiver and a controller for cooperating with the transceiver to receive operating requests from a host device. The controller may perform smart card operations based upon respective operating requests. Moreover, the controller also may cooperate with the transceiver to receive at least one advance request from the host device to indicate that at least one operating request will follow. By way of example, the standby operation may include loading data in at least one buffer, which may be sent to the host device based upon receiving the at least one operating request. Other standby operations may include disabling data transmission to the host device, such as when the communications bus of the host device is preoccupied, and ceasing performing a current smart card operation to allow a higher priority smart card operation to be performed, for example.

Abstract: A method and apparatus for controlling access to a plurality of resources based on multiple received requests is provided. The system includes a priority register configured to receive each individual request, determine a priority for the request, and transmit the request to a priority appropriate path. A first high priority arbiter receives and arbitrates among highest priority requests in a round robin manner to determine a high priority suggested grant vector. At least one lower priority arbiter receiving and arbitrating among lower priority requests in a round robin manner to determine at least one lower priority suggested grant vector. Grant circuitry passes the high priority suggested grant vector unless said grant circuitry receives a low priority indication, whereby the grant circuitry passes a lower priority grant vector.

Abstract: The present invention provides a method of arbitration for resources which allows requestors from multiple frequency domains. Most requestors generate requests at full speed. A small number of low-speed requesters generate requests every two full-speed cycles, and hold their requests for two full-speed cycles. The arbitration method gives priority to the requests from the low-priority requesters and guarantees that two requests made by the half-speed requestors at the beginning of a low-speed cycle will be granted over the course of the low-speed cycle. The requests generated by the low-speed requestors are issued in phases. Issuance of later phases of a request is blocked when the request has been granted in an earlier phase.

Abstract: In a bus arbitration method and bus arbiter which simultaneously considers fairness and priority and enables fairness and priority to be readjusted by a program, that is, by software, arbitration for ownership of a bus connected to a plurality of bus masters comprises grouping the plurality of bus masters into a plurality of groups and arbitrating the frequency of each bus master's ownership of the bus according to the result of the grouping. It is preferable that each of the plurality of groups has a priority different from the priorities of the others, and in arbitrating the frequency of each bus master owning the bus, arbitration of ownership of the bus by bus masters belonging to the same group is performed according to a round-robin method.

Abstract: In a multiprocessor, access to shared resources is provided by a semaphore control mechanism, herein disclosed. The semaphore control mechanism provides for a high degree of programmable firmware reuse requiring relatively few modifications from a uniprocessor. A machine check abort (MCA) handling mechanism is disclosed, which works with the semaphore control mechanism in the multiprocessor to provide improved system availability and reliability. The MCA handling mechanism provides for synchronization of multiple processors and shared resources and for timely execution resumption within the processors that remain on-line.

Abstract: A two-stage arbiter system comprises a first-stage arbiter to grant a request to one of a plurality of requestors in accordance with a first arbitration scheme and a second-stage arbiter to grant one of the remaining requests in accordance with a second arbitration scheme. The first arbitration scheme may be a fast arbitration scheme such as a fixed-priority scheme, and the second arbitration scheme may be a rotating priority-based arbitration scheme or a least-recently-granted arbitration scheme. The first-stage arbiter may operate in a first pipelined stage, and the second-stage arbiter may operate in a second pipelined stage. Two-stage arbitration may help improve access of lower-priority requestors in a pipelined system. In one embodiment, a rotating-priority arbitrator includes a pseudo-random number generator to generate an amount for rotating priorities prior to arbitration. The rotating-priority arbiter may use either a counter or linear-feedback shift register to rotate priorities of requests.

Abstract: A digital system and method of operation is provided in which several processors (740(0)–740(n)) are connected to a shared resource (750). Each processor has an access priority register (1410) that is loaded with an access priority value by software executing on the processor. A memory management unit (MMU) (700) is connected to receive a request address (742) from each respective processor. The MMU has a set of entries that correspond to pages of address space. Each entry provides a set of attributes for the associated page of address space, including an address space priority value 309a. For each request, the MMU accesses an entry corresponding to the request address and provides an address space priority value associated with that requested address space page. Arbitration circuitry (1430) is connected to receive a request signal from each processor along with the access priority value from each access priority register and the address space priority value from each MMU.

Abstract: In a system having a plurality of bus masters, system and method for enhancing data bus utilization are disclosed. This system comprises: a data bus connected to a peripheral apparatus and composed of a plurality of unit data buses each capable of carrying out data transfer independently; a plurality of bus masters each for sending a request signal requesting a use of the data bus in unit data buses, and using the data bus in unit data buses requested when a request by means of the request signal is granted; and a bus controller for giving a grant signal which grants the use of the data bus in unit data buses requested in unit data buses to the bus masters in accordance with an availability of the data bus in unit data buses, thereby split-controlling the data bus in unit data buses for the plurality of bus masters.

Abstract: A method of port numbering in an interconnect device includes loading a port configuration value from a memory device. One or more ports and subports are enabled according to the configuration value. Contiguous logical port numbers are assigned to the one or more ports and subports included in the interconnect device. A mapping request is received; and a mapped response associated with the mapping request is provided to an entity.

Abstract: An improved method and apparatus for resource arbitration. Four priority classes, managed high (MH), managed low (ML), opportunistic high (OH) and opportunistic low (OL), are defined. A priority class is assigned to each resource access request. An access request concentrator (ARC) is created for each resource, through which the resource is accessed. An access request is chosen at each ARC using the priority order MH, ML, OH, and OL, in decreasing order of priority. If OH priority class resource access requests are locked out, the priority order is temporarily changed to OH, OL, MH, and ML, in decreasing order of priority. If OL priority class resource access requests are locked out, the priority order is temporarily changed to MH, OL, OH, and ML, in decreasing order of priority.

Abstract: A clock signal arbitration method includes arbitrating between first and second request signals generated in respective first and second clock domains that are asynchronously timed relative to each other, to obtain first arbitration results. These first arbitration results identify a relative queue priority between the first and second request signals. Additional steps are performed to transfer the first arbitration results into a third clock domain that is asynchronously timed relative to the first and second clock domains. The transfer operation may include arbitrating the first arbitration results in a third clock domain to obtain second arbitration results that confirm or correct the first arbitration results.

Abstract: Systems and methods are disclosed for arbitrating requests from a plurality of clients requesting access to a shared real-time resource. In one embodiment, a plurality of sub-clients are aggregated into an aggregate client. At the aggregate client, access requests from the sub-clients are arbitrated to generate an aggregate request. An aggregate deadline is determined and access requests from the aggregate client and other clients are arbitrated using the aggregate deadline as the deadline of the aggregate client. In one embodiment, a critical instant analysis of the system is performed using the aggregate deadline as the deadline of the aggregate client. In another embodiment, a block-out counter is employed at an aggregate client to regulate the rate at which the aggregate client provides access requests to the shared resource.

Abstract: Methods, apparatus, and systems are presented for arbitrating access to a shared resource involve deciding whether to grant access to the shared resource to at least one of a first plurality of devices in accordance with a first arbitration algorithm and deciding whether to grant access to the shared resource to at least one of a second plurality of devices in accordance with a second arbitration algorithm distinct from the first arbitration algorithm, if access to the shared resource is not granted to at least one of the first plurality of devices. Arbitration algorithms that may be used as the first and/or second arbitration algorithm include fixed-priority algorithms, round-robin algorithms, and most-recently-used algorithms. In accordance with one embodiment, at least one of the first and second arbitration algorithms is implemented in hardware adapted to switch from executing one arbitration algorithm to executing another arbitration algorithm in one clock cycle.

Abstract: An arbitration circuit and a data processing system which ensure fair bus access are provided. An arbitration circuit (1) has a priority check block (21) and a round robin block (22). The priority check block (21) checks pieces of priority information provided from processors, specifies a processor that is presenting priority information with the highest priority, i.e. a processor with the highest priority level, and outputs the result of the check (CHK) to the round robin block (22). The round robin block (22), holding the results of the previous arbitration process, generates and outputs a processor selecting signal (SE) on the basis of the priority check result (CHK) and a round robin order generated from the previous results.

Abstract: Disclosed are systems and methods for providing access to bus-mastered system resources comprising disposing a bus multiplexer between a first bus and a bus access arbiter, wherein the first bus is coupled to at least one system resource for which bus access is arbitrated by the bus access arbiter, and controlling the bus multiplexer to couple a second bus to the first bus thereby providing a link between the first bus and the second bus bypassing the bus access arbiter.

Abstract: A plurality of arbitration devices is hierarchically coupled and has a plurality of child devices and at least one parent device. Each of the plurality of arbitration devices is operable to store a previous arbitration winner. In addition, the plurality of arbitration devices is operable to generate a request-out signal based on a plurality of request-in signals, and is operable to generate a select-out signal from a select-in signal, a plurality of request-in signals and from the previous arbitration winner. The request-out signals of the plurality of child devices are coupled to request-in signals of their respective parent devices and select-in signals of the child devices are received from select-out signals of the respective parent devices. Access is granted by a select-out signal from a device of the plurality of arbitration devices that resides at the lowest level of the system.

Abstract: An apparatus, system and method for controlling access to facilities based on usage class of a requestor are provided. With the apparatus, system and method, a two level protection mechanism is provided for protecting host channel adapter (HCA) facilities from unauthorized access. With the present invention, a first level of access is provided through virtual address translation and a mechanism for determining if the requestor of access may access a system memory address space page associated with a real address to which the virtual address maps. A second level of access is provided through the allocation of usage classes and determining a required usage class for accessing an HCA facility.

Abstract: A binary-tree-based arbitration system and methodology with attributes that approximate a Generalized Processor Sharing (GPS) scheme for rendering fairer service grants in an environment having a plurality of competing entities. Arbitration based on probabilistic control of arbiter nodes' behavior is set forth for alleviating the inherent unfairness of a binary tree arbiter (BTA). In one implementation, BTA flag direction probabilities are computed based on composite weighted functions that assign relative weights or priorities to such factors as queue sizes, queue ages, and service class parameters. Within this general framework, techniques for desynchronizing a binary tree's root node, shuffling techniques for mapping incoming service requests to the BTA's inputs, and multi-level embedded trees are described.

Abstract: A system for selecting bus mastership in a multi-master system includes master devices and at least one slave device. The master devices generate control signals relating to bus mastership in the multi-master system. The slave device(s) receive the control signals from the master devices, determine whether a conflict exists based on the control signals, generate one or more alternate control signals for selecting bus mastership when a conflict is determined to exist, and select bus mastership using the one or more alternate control signals.

Abstract: A method for bus arbitration comprising assigning priorities changeable with time to requesters of a data bus, and for simultaneous bus requests by more than one requestor, granting usage of the bus to the requester with the highest priority at the time of the bus requests.

Abstract: Round robin arbitration system includes a first round robin arbitration module and a second round robin arbitration module. The first round robin arbitration module has a first bit width. It is configured to partition a plurality of requests into a plurality of blocks of requests, to select a block having one or more active requests using round robin arbitration, and to generate a first index corresponding to the selected block. The second round robin arbitration module has a second bit width. It is configured to store each request of the selected block, to select each active request of the selected block using round robin arbitration, to generate a second index corresponding to the selected active request, and to generate a first signal for synchronizing operation of the first and second modules. The round robin arbitration system has a bit width that is a product of the first and second bit widths.

Abstract: A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor. The memory control unit includes a switch network to transfer data between the one or more devices of the processor and the one or more memory ports of the processor. The memory control unit also includes a switch arbitration unit to arbitrate for the switch network, and a port arbitration unit to arbitrate for the one or more memory ports.

Abstract: A data processing device comprises a plurality of processors that are to access a memory system. The memory system comprises at least two memories The data processing device comprises a bus per memory. The buses are interconnected by at least one bridge. A processor is connected to a bus, and the data processing device comprises at least one memory table specifying with which memory an exchange of a data item between a processor and the memory system must be effected.

Abstract: A circuit comprising a plurality of components sharing at least one shared resource, and a lottery manager. The lottery manager is adapted to receive request for ownership for the at least one shared resource from a subset of the plurality of components. Each of the subset of the plurality of components are assigned lottery tickets. The lottery manager is adapted to probabilistically choose one component from the subset of the plurality of components for assigning the at least one shared resource. The probabilistic choosing is weighted based on a number of lottery tickets being assigned to each of the subset of the plurality of components.

Abstract: A computer system including a first repeater and a second repeater that is coupled to the first repeater. The computer system also includes a third repeater that is coupled to the first repeater. The first repeater contains a first arbiter that arbitrates transactions between the first repeater and the second repeater and also arbitrates transactions between the first repeater and the third repeater. The second repeater receives transactions from the first repeater and contains a second arbiter that predicts receipt of transactions from the first repeater to the second repeater.

Abstract: The immediate grant bus arbiter of this invention is a part in the implementation of a multiple transaction bus system. A bus bridge provides a means to connect two separate busses together and secure data integrity. The bus bridge is defined with clear master-slave protocol. The bus bridge normally involves the use of two arbiters. The arbiter on the primary bus needs to operate differently from the arbiter on the secondary bus due to real system time constraints. This invention defines a bus arbiter that allows for a dominant bus master to receive an immediate grant of control on the bus. This immediate grant bus arbiter never relinquishes the bus if another lower priority master makes a bus request. This makes predictable real time data transfer possible.

Abstract: A two-stage arbiter system comprises a first-stage arbiter to grant a request to one of a plurality of requestors in accordance with a first arbitration scheme and a second-stage arbiter to grant one of the remaining requests in accordance with a second arbitration scheme. The first arbitration scheme may be a fast arbitration scheme such as a fixed-priority scheme, and the second arbitration scheme may be a rotating priority-based arbitration scheme or a least-recently-granted arbitration scheme. The first-stage arbiter may operate in a first pipelined stage, and the second-stage arbiter may operate in a second pipelined stage. Two-stage arbitration may help improve access of lower-priority requestors in a pipelined system. In one embodiment, a rotating-priority arbitrator includes a pseudo-random number generator to generate an amount for rotating priorities prior to arbitration. The rotating-priority arbiter may use either a counter or linear-feedback shift register to rotate priorities of requests.

Abstract: A method of synchronizing arbiters. The method is performed by a computer system that has a first repeater, a second repeater that is coupled to the first repeater, and a third repeater that is coupled to the first repeater. The method includes: instructing the second repeater to cease issuing transactions to the first repeater; synchronizing an arbiter within the second repeater with an arbiter within the third repeater; instructing the second repeater to begin issuing transactions to the first repeater; and instructing the third repeater to begin issuing transactions to the first repeater.

Abstract: Methods for dynamically allocating memory in a multiprocessor computer system such as a non-uniform memory access (NUMA) machine having distributed shared memory. The methods include allocating memory by specified node, memory class, or memory pool in response to requests by the system (kernel memory allocation) or a user (application memory allocation). Through these methods memory is allocated more efficiently in a NUMA machine. For example, allocating memory on a specified node in a NUMA machine, such as the same node on which a process requiring the memory is running, reduces memory access time. Allocating memory from a specified memory class allows device drivers with restricted DMA ranges to operate with dynamically allocated memory. Other benefits of these methods include minimizing expensive remote-memory accesses using a distributed reference count mechanism and lock-free cache access.

Abstract: An arbitration method and mechanism assigning priority to one of a combination of requesters. A priority vector for the combination of requesters has a sequential list of requester identifiers. Upon receiving requests from the combination of requesters, the corresponding priority vector is referred to and the next requester identifier on this list is selected. Priority is awarded to the requester corresponding to that requester identifier. A priority vector is preferably provided for each possible combination of multiple requesters. The list of requester identifiers in each priority vector may be advantageously programmable. Preferably, all requester identifiers for a single requester are not provided in a contiguous clump within a given priority vector.

Abstract: In a first embodiment, multi-speed concatenated packet strings are transmitted by a first node on a serial bus. To accommodate multi-speed packets, a speed signal is transmitted immediately prior to the packet. In a second embodiment, ACK-concatenation is used to allow a node to transmit a data packet immediately after transmitting an acknowledge signal on the bus. The data packet need not be related to the ACK packet. In a third embodiment, a node which receives a first data packet followed by a data end signal on a child port, concatenates a second data packet onto the first data packet during retransmission. The second data packet is also transmitted down the bus in the direction of the node which originally transmitted the first data packet.

Abstract: The invention provides unique mechanisms and techniques for a computing device to perform various tasks in a multi-tasking or time sliced environment. A general task scheduling algorithm can select various time slices or priorities for task performance. However, in a dedicated device such as a data communications device, a primary task such as a data transfer task may be so heavily favored by the general task scheduling algorithm, such as in heavy network traffic conditions, that other tasks may be starved of processor time. As such, the system of the invention allows the primary task, to track a first time period Y, and upon expiration of this time period Y, to generate a yield signal to a yielding scheduler. The yielding scheduler can then disable performance of the primary task(s) and track a second time period X during which other tasks may be performed.

Abstract: The invention relates to a bus for a highly scalable multiprocessor system, to a redundant bus system that utilizes this bus, and to a method for transmitting information in this bus system. To guarantee an optimally high throughput of individual accesses onto a shared memory, the bus 3 consists of an address bus 4 and a data bus 5, which are operated logically independent of one another and which are functionally connected only via a common identifier. In this way, the dynamic holding of the address bus 4 and of the data bus 5 as well as the latencies are minimized.

Abstract: In a data/information processing system, a nested privilege protection is employed to protect the system when executing instructions. A first privilege protection having at least two privilege levels is enforced. Additionally, a second privilege protection having at least two sub-privilege levels is further enforced for at least one privilege level of the first privilege protection to further differentiate the privileges otherwise afforded. In one embodiment, core system services, programming language runtime support and application programs are afforded the same privilege level of the first privilege protection, and the different types of programs are afforded different sub-privilege levels of the second privilege protection to differentiate the privileges afforded by the first privilege protection.

Abstract: A computer system including a first repeater; a second repeater coupled to the first repeater; and a third repeater coupled to the first repeater. The second repeater is also coupled to a first client and a second client. The second repeater contains a distributed arbiter that predicts whether the first repeater will send a transaction to the second repeater.

Abstract: An interconnect system includes an arbitration unit for arbitration among a plurality of sources or initiators requesting access to resources or targets. The arbitration unit selectively grants the initiators access to the targets as a function of respective priorities. The system includes a programmable control unit for programmably choosing the priorities in question out of group of at least two different priority schemes including a positional fixed priority, programmed fixed priority, and a variable priority based on a respective threshold latency values associated to the initiators.

Abstract: A method is proposed for the purpose of performing bus arbitration between two control chips in a chipset with preemptive capability. The two control chips can be, for example, a North Bridge chip and a South Bridge chip, of which one is set as bus owner while the other is set as bus receiver at initializtion. During operation, in the event that the current bus receiver intends to carry out a high-priority transaction, it can issue a preemptive request to ask the bus owner to relinquish the control of the bus. In response to this preemptive request, the current bus owner will start a latency timer; and by the time the latency timer reaches its preset time, the current bus owner will unconditionally hand the bus to the current bus receiver, allowing the current bus receiver to become the bus owner, thereby using the bus to carry out the intended high-priority transaction. This preemptive scheme can help enhance the overall system communication perfomance.

Abstract: A multi-processing system (50) utilizes an interconnect fabric (59) for coupling endpoint devices (52, 54, 56, 66, 67). Bus control functions are managed in a method which is bus protocol independent. Each of the endpoint devices and the fabric function by specific rules to transfer data having a priority. Within the interconnect, higher priority data transfers take precedence of servicing, and for equal priority data the data is serviced first-in, first-out. Requests of endpoint devices that require a response can not be sent at the highest priority. Endpoint devices may not allow the acceptance of data to be contingent on outputting data of equal or lesser priority than the priority of the incoming data. Transaction priority, ordering and deadlocks are efficiently handled without the interconnect fabric needing to implement a set of bus protocol rules. Within the endpoint devices, additional rules related to ordering may be implemented.

Abstract: The Sharing arbiter is an arbiter which, under certain conditions, permits two or more Done signals to be received before the Sharing arbiter issues a grant signal and, under certain conditions, is permitted to issue more than one grant signal before receiving a Done signal. A Sharing arbiter can be implemented by adding a queue onto the Done input of a Sequencer arbiter. In a Sharing arbiter with a Sharing-number of N and K request inputs, the Sharing arbiter is permitted to issue M grant signals concurrently if M input requests have been received (where M≦K and M≦N) without enforcing mutual exclusion between the grants if at least M Done signals have also been received. Where less than M Done signals have been received (P Done signals, for example), the Sharing arbiter arbitrates among the M input requests and is permitted to issue P grant signals concurrently.

Abstract: A memory controller (218) is disclosed which includes a write arbiter (130) and a read arbiter (140) for receiving and processing memory requests from a number of requestor modules (190) for accessing a high speed memory device (110). A high speed controller (120) controls data flow to and from the high speed memory device (110) at a frequency that is higher than ail operating of the arbiters (130, 140), allowing pseudo-simultaneous memory transactions. A read data dispatcher (160) is also disclosed for receiving data from the high speed controller (120) in response to read transactions and for passing the data to one of the requestor modules (190). The size and destination information for launched read transactions are kept by a queue 150. When return data is received by the read data dispatcher (160), the read data dispatcher (160) matches the appropriate amount of data with each queue entry and delivers that return data to the appropriate requester module (190).

Abstract: A system includes two or more agents and a distributed arbitration scheme for the bus to which the agents are connected. Thus, an arbiter corresponding to each agent is provided. The arbiters are reset using a first reset signal, while the agents are reset using a separate reset signal or signals. The arbiters are concurrently released from reset when the first reset signal is deasserted, and may have a consistent reset state to provide for synchronization of the arbiters. The agents may be independently released from reset by the separate reset signals. Accordingly, the arbiters may be synchronized and may remain synchronized even if the corresponding agents are released from reset at different times, or are temporarily held in reset for any reason.

Abstract: A binary-tree-based arbitration system and methodology with attributes that approximate a Generalized Processor Sharing (GPS) scheme for rendering fairer service grants in an environment having a plurality of competing entities. Arbitration based on probabilistic control of arbiter nodes' behavior is set forth for alleviating the inherent unfairness of a binary tree arbiter (BTA). In one implementation, BTA flag direction probabilities are computed based on composite weighted functions that assign relative weights or priorities to such factors as queue sizes, queue ages, and service class parameters. Within this general framework, techniques for desynchronizing a binary tree's root node, shuffling techniques for mapping incoming service requests to the BTA's inputs, and multi-level embedded trees are described.

Abstract: Arbitration requests are received that belong to respective bus types. Each of the types is associated with a programmed value representing a potential number of times that requests of that type may win arbitration events that occur in a given time period. For at least some arbitration events that occur in the given time period, the invention updates a counter value for at least some of the types, the counter value for each of the types being set initially to the programmed value, and chooses a winning type in each of the arbitration events based on at least some of the counter values of the types of requests that are contending in the arbitration event.

Abstract: When a high-level bus converter receives a normal request from any one of a plurality of intermediate-level bus converters, the high-level bus converter converts the normal request into a retry response and sends the retry response to the intermediate-level bus converter, if a normal response buffer is busy. When the high-level bus converter receives an urgent request, the high-level bus converter sends a normal response in response to the urgent request to the intermediate-level bus converter. Each of a plurality of low-level bus converters issues a normal request, converts, when a retry response is received, the retry response into an urgent request, and reissues a request as the urgent request. When a plurality of urgent requests compete with each other for being processed, each of the plurality of intermediate-level bus converters arbitrates among the plurality of urgent requests, and directly transfers a winner urgent request to the high-level bus converter.

Abstract: A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor. The memory control unit includes a switch network to transfer data between the one or more devices of the processor and the one or more memory ports of the processor. The memory control unit also includes a switch arbitration unit to arbitrate for the switch network, and a port arbitration unit to arbitrate for the one or more memory ports.

Abstract: In a computing system with non-shareable resources, use-arbitrating processes are executed on behalf of each task seeking or having access to non-shareable resource. The processes compete according to prescribed rules and priority guidelines, the resolution of which determines access to the non-shareable resource. If application of the priority guidelines permits, a use-requesting task can institute takeaway of a resource from a task that is already using the resource.

Abstract: The present invention is directed to a method and apparatus utilizing a two-level, multi-tier system bus. The multi-tier system bus of the present invention allows for the flow of information to be managed among plural processors by connecting processors within modules on a local bus, which is then connected to the system bus by way of a gateway. A system controller and arbitrator is provided for arbitrating access to the system bus by the various modules. The present invention, by way of the system controller initiates and performs control actions and allows the system bus to be freed from transmission delays of prior approaches associated with transmitting data packets.