Abstract: The present invention provides a DMA transfer controller includes: a transfer parameter storing unit for storing a bus occupation time value and transfer parameters of one set or a plurality of sets of DMA transfers for each of a plurality of logical processors; a data transfer performing unit for performing the DMA transfer on the basis of the DMA transfer parameters; a control unit for controlling the receive and transmit of the DMA transfer parameters and the start and the interruption of the DMA transfers; and a time measuring unit for starting to measure bus occupation elapse time when a first DMA transfer is started for each of the logical processors. When the bus occupation elapse time reaches the bus occupation time value, the control unit interrupts the DMA transfer that is currently performed to start the DMA transfers based on the transfer parameters related to the logical processors of a prescribed sequence.

Abstract: A management agent ME1 of a target T1 receives a request of log-in from an initiator of interest and determines whether or not a number of initiators that currently log in the target T1 reaches a predetermined allowable number of simultaneous log-in (steps S210 and S212). In the case of an affirmative answer, the management agent ME1 reads an ordinal number of precedence ‘n’ allocated to a GUID of the initiator of interest from a queue (step S213) and reads a time constant mapped to the input ordinal number of precedence ‘n’ from a time constant table (step S214). The management agent ME1 subsequently sends a status packet, which includes a log-in error status and the time constant, to the initiator of interest (step S216). The initiator of interest receives the status packet, reads the time constant included in the input status packet, and outputs another request of log-in to the target T1 at a timing specified by the time constant.

Abstract: An image processing apparatus includes a data reading and writing unit for reading and writing data with respect to a specific recording medium; a data incompatibility avoiding unit for performing a data incompatibility avoiding process during reading and writing the data associated with cut-off of power; an incompatibility avoiding process starting unit for detecting a cut-off signal of power and controlling the data incompatibility avoiding unit to start the data incompatibility avoiding process; and a power cut-off delaying unit for delaying cut-off of the power for a specific period of time after the cut-off signal is detected when the data incompatibility avoiding unit starts the data incompatibility avoiding process. The data incompatibility avoiding unit performs the data incompatibility avoiding process within the specific period of time.

Abstract: A first storage stores input image data. A second storage stores image data read from the first storage. A control part determines, with respect to a timing at which data transfer of image data into the first storage, a data transfer of the said image data from the first storage to the second storage, based on a rate of data transfer and writing of the image data into the first storage and rate of data transfer and writing of the image data into the second storage from the first storage.

Abstract: Programmatic detection of time-gap defects in computer system hardware where data is corrupted without detection by the computer system. A detection module initiates data transfers between devices in a computer system. An interrupt service routine interrupts the process by inserting a delay into the data transfer. The detection module then checks for time-gap defects by determining if data was corrupted which went undetected by the computer system. The detection module may repeat the data transfer and insert successively longer delays until a time-gap defect is detected or until a maximum delay value is reached. The results of any time-gap defects found may be output to a user.

Abstract: In one embodiment, a direct memory access (DMA) disk controller used in hardware-assisted data transfer operations includes command receiving logic to receive a data transfer command issued by a processor. The data transfer command identifies one or more locations in memory and multiple distinct regions on one or more disks accessible to the DMA disk controller. The DMA disk controller further includes data manipulation logic to transfer data between the memory locations and the distinct regions on the disks according to the data transfer command.

Abstract: A method and system for monitoring frame flow in a Fiber Channel network is provided. The method includes, deleting fill words before any frame data is allowed to be stored in a buffer memory; storing only certain primitive signals and/or frame data in the buffer memory; reading the buffer memory without delay, if a primitive signal is stored in the buffer memory; and delaying reading the buffer memory if frame data is detected. The network includes, a host bus adapter that includes a fiber channel protocol manager that includes a receive logic that deletes fill words before any frame data is allowed to be stored in a buffer memory, wherein the buffer memory stores only certain primitive signals and/or frame data and the buffer memory is read without any delay, if a primitive signal is stored, while a read operation of the buffer memory involving frame data is delayed.

Abstract: According to embodiments of the present invention, a peripheral component interconnect (PCI) standard hot-plug controller (SHPC) includes a command register to store PCI slot operation commands for one or more target PCI slots and a programmable register that may be programmed with one timing parameter value (e.g., Tpccc, Tpece, Tcebe, Tbkrk, etc.) for a signal sequence for execution of one PCI slot operation command and another timing parameter value for a signal sequence for execution of another PCI slot operation command depending on the particular target PCI slot, the particular PCI slot operation command loaded into the command register, and/or the number of times a particular PCI slot operation command has been loaded into the command register, for example.

Abstract: According to one embodiment a system is described. The system includes a direct memory access (DMA) controller and an input/output (I/O) device coupled to the DMA controller. The DMA controller is adaptable to operate in a normal mode and a descriptor mode.

Abstract: A parallel processing system includes a plurality of stages operatively coupled in parallel and operating simultaneously. Each stage including a process unit generating a predetermined function and a buffer coupled via a slow output and a slow input ports to the process unit. The buffer also includes a fast input port and a fast output port. A controller drives the buffer to operate in a Slow Read Phase when data is written from the buffer into the process unit, a Slow Write Phase when data is written into the buffer from the process unit, a Fast Write Phase when data is written at a fast rate into the buffer and a Fast Read Phase when data is read from the buffer.

Abstract: Provided are a method, system, and program for handling Input/Output (I/O) requests. A bus enables communication with an initiator, target device and device controller, wherein the device controller accesses the target device to execute I/O commands directed to the target device. An I/O request command is received to access the target device. The initiator is configured to transmit at least one data request on the bus to one memory address in a predefined address window of the device controller. The device controller is enabled to claim the data request to the memory address in the predefined address window from the initiator on the bus to execute the data request against the target device.

Abstract: A transceiver device comprises a transmitter to transmit signals over a plurality of conductors to a memory device. An interface receives control information from a serial communication path coupled to a controller device. The control information is provided to the memory device as the signals using the transmitter. A register stores a control parameter that specifies a drive strength adjustment to the signals to transmit over the plurality of conductors to the memory device using the transmitter.

Abstract: The parallel or printer port in a personal computer can receive data from the memory under the control of the direct memory access (DMA) controller, releasing processor resources. The processor enables the parallel port, which then indicates to the DMA controller the desire to transfer data. A state machine in the parallel port, along with the associated circuitry, responds to the transfer of the data to the parallel port and then controls the transfer of the data to the attached device, usually a printer. The state machine causes an interrupt to the processor when the transfer is complete or on receipt of errors from the external device. The state machine also communicates with the DMA controller to repeat the transfer process until the transfer is complete or an error occurs. Various DMA channels and parallel port locations can be used. Direct transfers by the processor are blocked during DMA controller handled transfers.

Abstract: Systems for servicing the data and memory requirements of system devices. A DMA engine that includes a data reservoir is provided that manages and arbitrates the data requests from the system devices. An arbitration unit is provided that only allows eligible devices to make a data request in any given cycle to ensure that all devices will be serviced within a programmable time period. The data reservoir contains the data buffers for each channel of each device. A memory interface ensures that sufficient data for each channel is present in the data reservoir by making requests to a system's memory based on an analysis of each channel. Based on this analysis, a request is either made to the system's main memory, or the channel waits until it is evaluated again in the future. Each channel is thereby guaranteed a response time.

Abstract: A transceiver comprises a first interface to receive a first signal, through a first channel, from a memory device. A transmitter transmits a second signal that represents the first signal, through a second channel, to a master device. A plurality of registers stores a plurality of values provided by the master device. The plurality of values includes a first value that specifies a transmit timing adjustment to the second signal to transmit to the master device by the transmitter.

Abstract: In a bi-directional, self-synchronous bus for communication between semiconductor devices, a logic delay is provided as a flag to a state machine control for indicating that the bus is making a transition from a low to a high state. The logic delay causes the bus to adaptively idle until the bus settles, making it amenable for a wide variety of bus sizes and topologies. In this way, oscillation of the bus is avoided without slowing the speed of the state machine clock.

Abstract: The invention relates to an apparatus and a method for accessing memories having a time-variant response over a PCI bus by using two-stage DMA transfers. The invention provides a method for executing a read request over a PCI bus by transferring the requested data from a main memory of a PCI card to a device located on the PCI bus, comprising the steps of obtaining an access request from a read access queue, transferring, by a first DMA transfer, the requested data from the main memory to a buffer memory on the PCI card, and transferring, by a second DMA transfer, the data from the buffer memory to the device.

Abstract: The value relating to the average of the length of processing time required to process a plurality of information sets is reduced. In one embodiment, an information processing device comprises: a receiving component receiving information elements contained in respective information sets having one or more information elements; an information processing component carrying out processing of the information elements thus received; and a determining component determining a processing sequence for the two or more information sets or the plurality of information elements, and determining a processing sequence different from the reception sequence, in which a value relating to the average of the length of processing time for the two or more information sets becomes equal to or less than the value that would be obtained were the plurality of information elements or the two or more information sets to be processed in accordance with their reception sequence.

Abstract: Synchronization is maintained among a plurality of network devices having local clocks that participate in a network. A first packet is broadcast from a first network device to other network devices that participate in the network. The first packet includes a global time reference derived from the local clock of the first network device. The clocks of the network devices that receive the first packet are adjusted to be closer to the local clock of the first network device. A first network local time reference and a second network local time reference may be maintained for a device that participates in a first network and a second network. A free running clock is maintained on the device. The difference between the free running clock and a first network global time reference is determined. A first network offset is calculated to account for the difference between the free running clock and the first network global time reference.

Abstract: A management agent ME1 of a target T1 receives a request of log-in from an initiator of interest and determines whether or not a number of initiators that currently log in the target T1 reaches a predetermined allowable number of simultaneous log-in (steps S210 and S212). In the case of an affirmative answer, the management agent ME1 reads an ordinal number of precedence ‘n’ allocated to a GUID of the initiator of interest from a queue (step S213) and reads a time constant mapped to the input ordinal number of precedence ‘n’ from a time constant table (step S214). The management agent ME1 subsequently sends a status packet, which includes a log-in error status and the time constant, to the initiator of interest (step S216). The initiator of interest receives the status packet, reads the time constant included in the input status packet, and outputs another request of log-in to the target T1 at a timing specified by the time constant.

Abstract: In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.

Abstract: Data received by a Bluetooth wireless unit is buffered on a DRAM. At this time, a CPU (which operates on the basis of a description of HDD startup control program calculates the data transfer rate of the Bluetooth wireless unit and the free area size of a buffer area on the DRAM, and also calculates the remaining time until the buffer data on the DRAM becomes full of data, on the basis of these values. When the calculated remaining time has reached a required startup time of an HDD indicated by remaining time determination data A stored in a flash memory, the CPU starts up the HDD.

Abstract: A computer system architecture and memory controller for close-coupling within a hybrid computing system using an adaptive processor interface port (“APIP”) added to, or in conjunction with, the memory and I/O controller chip of the core logic. Memory accesses to and from this port, as well as the main microprocessor bus, are then arbitrated by the memory control circuitry forming a portion of the controller chip. In this fashion, both the microprocessors and the adaptive processors of the hybrid computing system exhibit equal memory bandwidth and latency. In addition, because it is a separate electrical port from the microprocessor bus, the APIP is not required to comply with, and participate in, all FSB protocol. This results in reduced protocol overhead which results higher yielded payload on the interface.

Abstract: System and method for transferring data to a device using double buffered data transfers. A host computer system couples to a data acquisition device. The device includes a first read buffer and a second read buffer for storing output data received from the host computer. The device reads first data from the computer and stores it in the first read buffer. The first data is transferred out from the first read buffer while the device reads second data from the computer and stores it in the second read buffer. The second data is transferred out from the second read buffer (after the transfer of the first data) while the device reads third data from the host computer and stores the third data in the first read buffer. Thus, the data acquisition device successively reads data into one read buffer concurrently with transferring data out from the other buffer, respectively.

Abstract: The invention is to provide an information processing apparatus capable of easily setting operation parameters in acquiring various status from the plural peripheral apparatus, and a method therefor. In an image for setting the time-out value for a protocol for acquiring the status of the peripheral apparatus on the network, a change by the user on a time-out value for all the status acquisition from the peripheral apparatus is reflected on the time-out values for acquisitions of various statuses.

Abstract: Method for recovering a clock signal from an input data signal in a telecommunications system, that provides for comparing the input data signal with a recovered clock signal in order to control said recovered clock signal generation and provides for generating a plurality of delayed clock signals, obtained by multi-delaying at least a reference signal, said delayed clock signals being phase-shifted with respect to each other. According to the invention, said delayed clock signals show a phase shift with respect to each other, that is nominally constant in time, and, moreover, it is provided for selecting the recovered clock signal among said delayed clock signals.

Abstract: Embodiments of the invention provide a status register for each channel of a DMA controller. The status register may be used to monitor and record events that occur during DMA data transfers, including timeouts and aborts.

Abstract: Complex control procedures employ direct memory access by a first DMA processing unit 54 to send control data to a first controller by means of DMA channels 54-1 to 54-n, and by a second DMA processing unit 56 to send control data to a second controller 36 by means of DMA channels 56-1 to 56-m. The first DMA processing unit 54 also has a branching controller 52 as a DMA channel for transferring timing data to a second timer 40. When a time specified by the received timing data passes, the second timer 40 sends an activation signal to DMA channel 56-1 of the second DMA processing unit 56, and the DMA channels 56-1 to 56-m are thereafter sequentially activated.

Abstract: A multi-processor arrangement having an interprocessor communication path between each of every possible pair of processors, in addition to I/O paths to and from the arrangement, having signal processing functions configurably embedded in series with the communication paths and/or the I/O paths. Each processor is provided with a local memory which can be accessed by the local processor as well as by the other processors via the communications paths. This allows for efficient data movement from one processor's local memory to another processor's local memory, such as commonly done during signal processing corner turning operations. Configurable signal processing logic may be configured to host one or more signal processing functions which allow data to be autonomously accessed from the processor local memories, processed, and re-deposited in a local memory.

Abstract: A control chip having a multiple-layer defer queue therein and a method of operating the control chip. The control chip is coupled to a CPU bus and a PCI bus. The control chip comprises of a PC request queue, a multiple-layer defer queue, a PCI access queue and a PCI controller. The multiple-layer defer queue facilitates the processing of a multiple of concurrent CPU requests that belong to a first request type. The multiple-layer defer queue supports retry and defer transactions, thereby reducing data transmission between the CPU and the control chip.

Abstract: A real-time data acquisition and storage network for real-time acquisition and storage of analog and digital data from one or multiple network-connected data sources to one or multiple network-connected storage devices during a data recording session, and precise reconstruction of the acquired data from one or multiple of the network-connected storage devices during a playback session. The data source are connected to the network through one or multiple real-time data acquisition network (“R-T DAN”) modules which form one or multiple network-connected data acquisition nodes on the network. Each storage device forms a network-connected storage node on the network so that data acquired at any data acquisition node may be applied to the network and stored at any storage node during a data recording session. The stored data may be retrieved from the storage nodes through the network and routed to the data acquisition nodes for reconstruction of the data during a playback session.

Abstract: The ManArray processor is a scalable indirect VLIW array processor that defines two preferred architectures for indirect VLIW memories. One approach treats the VIM as one composite block of memory using one common address interface to access any VLIW stored in the VIM. The second approach treats the VIM as made up of multiple smaller VIMs each individually associated with the functional units and each individually addressable for loading and reading during XV execution. The VIM memories, contained in each processing element (PE), are accessible by the same type of LV and XV Short Instruction Words (SIWs) as in a single processor instantiation of the indirect VLIW architecture. In the ManArray architecture, the control processor, also called a sequence processor (SP), fetches the instructions from the SIW memory and dispatches them to itself and the PEs. By using the LV instruction, VLIWs can be loaded into VIMs in the SP and the PEs.

Abstract: One or more queues store data information such as packets or data flows for later transmission to downstream communication devices. A real-time clock tracks current time and an advancement of a moving time reference, which is displaced with respect to the current time of the clock by an offset value. Thus, as current time advances, the moving time reference also advances in time. Upon servicing a queue, a time stamp associated with the serviced queue is also advanced in time. To monitor a rate of outputting data from the one or more queues, a processor device at least occasionally adjusts the offset value so that the moving time reference and values of the time stamps advance in relation to each other. Consequently, by tracking a relative time difference between current time of the real-time clock and a relative advancement of time stamps, a rate of outputting data information from the queue is monitored over time.

Abstract: A direct memory access controller includes: one request signal input terminal for inputting a request signal while at least one of a plurality of request devices is outputting the request signal; one acknowledge signal output terminal for outputting an acknowledge signal to the plurality of request devices; and a control circuit. The control circuit outputs the acknowledge signal from the acknowledge signal output terminal and thereafter controls a data transfer based on the request signal from one of the plurality of request devices in response to a timing when the request signal inputted from the request signal input terminal changes in level.

Abstract: A method and system for accessing a shared memory in a deterministic schedule. In one embodiment, a system comprises a plurality of processing elements and a system I/O controller where each processing element and system I/O controller comprises a DMA controller. The system further comprises a shared memory coupled to each of the plurality of processing elements where the shared memory comprises a master controller. The master controller may then issue tokens to DMA controllers to grant the right for the associated processing elements and system I/O controller to access the shared memory at deterministic points in time. Each token issued by the master controller grants access to the shared memory for a particular duration of time at a unique deterministic point in time. A processing element or system I/O controller may access the shared memory upon the associated DMA controller relinquishing to the master controller the token that grants the right to access the shared memory at that particular time.

Abstract: Systems and methods for servicing the data and memory requirements of system devices. A DMA engine that includes a data reservoir for reducing or eliminating device buffers is provided that manages and arbitrates the data requests from the system devices. An arbitration unit is provided that only allows eligible devices to make a data request in any given cycle to ensure that all devices will be serviced within a programmable time period. The data reservoir contains the data buffers for each channel of each device. A memory interface ensures that sufficient data for each channel is present in the data reservoir by making requests to a system's memory based on an analysis of each channel. Analysis factors include how much data is remaining in the data reservoir, how long will that data last, and how long until the channel will be analyzed again. Based on this analysis, a request is either made to the system's main memory, or the channel waits until it is evaluated again in the future.

Abstract: A DMA controller has both a receiving portion and a sending portion and may be used in a modem or other data transmission context. The DMA controller is intended to provide to or receive from data samples on a bus that may or may not be available. For the case when the bus is available, samples of data are either sent to or received from proper memory locations. When the bus is not available, the number of the samples that are missed due to the bus not being available is stored. This count is then used to ensure that the samples that are provided or received when the bus becomes available are stored in or read from the proper location to provide the samples at the proper time. The locations in which the samples were lost are provided with predetermined values.

Abstract: A direct memory access control system supplies the respective status signals indicating timings of the read data effective state or writable state between the input/output interface and memory interface, both interfaces maintain the read data effective state and writable state of the input/output memory and synchronous memory under control until the later timing comes up. Consequently, it is possible to match the read data effective timing and writable timing of the synchronous memory and input/output memory, thus making possible flyby transfer of data between both memories.

Abstract: The parallel or printer port in a personal computer can receive data from the memory under the control of the direct memory access (DMA) controller, releasing processor resources. The processor enables the parallel port, which then indicates to the DMA controller the desire to transfer data. A state machine in the parallel port, along with the associated circuitry, responds to the transfer of the data to the parallel port and then controls the transfer of the data to the attached device, usually a printer. The state machine causes an interrupt to the processor when the transfer is complete or on receipt of errors from the external device. The state machine also communicates with the DMA controller to repeat the transfer process until the transfer is complete or an error occurs. Various DMA channels and parallel port locations can be used. Direct transfers by the processor are blocked during DMA controller handled transfers.

Abstract: A method for avoiding data collision in a half-duplex mode using a DMA logic for multi-point linked processors is disclosed. According to the disclosed method, a transmitting processor holds a request-to-send (RTS) signal in an active state for a prescribed period of time so that a transmitting DMA logic of a receiving processor can be initiated after the operation of a receiving DMA logic of the receiving processor is terminated. Since the Tx DMA logic of the receiving processor starts data transmission after the Rx DMA logic of the receiving processor completes receiving of data, data collisions occurring in the receiving processor due to the concurrent operation of the Tx DMA logic and the Rx DMA logic can be prevented.

Abstract: A system is configured to prioritize streaming disk I/O over non-streaming disk I/O by providing high priority queuing to streaming disk I/O and/or to throttle non-streaming disk I/O when the total disk I/O (streaming+non-streaming) exceeds a threshold amount for a given time quantum. When disk throttling is utilized, streaming disk I/O is processed in a first time quantum. Non-streaming disk I/O is processed, as much as possible, in the remainder of the first time quantum. Other non-streaming disk I/O remaining to be processed is deferred to a subsequent time quantum.

Abstract: A digital system having a split transaction memory access. The digital system can access data from a system memory through a read buffer (FIFO) located between the processor of the digital system and the system bus. The read buffer is implemented with two FIFOs, a first incoming data FIFO for reading data, and a second outgoing address FIFO for transmitting read requests. The processor of the digital system can access the data FIFO and read data while the data transfer is still in progress. This decreases the processing latency, which allows the processor to be free to perform additional tasks.

Abstract: The present invention is directed to a system and method for eliminating race conditions in RAID controllers while utilizing a high bandwidth internal architecture for data flow. A remote memory controller of the present invention may ensure that an acknowledge signal is sent only after a memory operation has been actually completed. This may provide for remote direct memory access without coherency problems and data corruption problems while a high bandwidth data flow internal architecture is being utilized.

Abstract: A DMA controller has a cycle register in which the number of data transfer cycles to be performed in response to a single DMA transfer request is set, a cycle counter for counting the number of data transfer cycles actually performed, and a transfer counter for holding a value that is updated every time the number of data transfer cycles as held in the cycle register are completed. From the start to the end of the data transfer cycles, the number held in the cycle register is kept unchanged, and the data transfer cycles are performed until the value held in the transfer counter becomes equal to a predetermined value. In this configuration, even in a case where a predetermined number of DMA transfer cycles are performed in response to a single DMA transfer request and a plurality of DMA transfer requests are made in succession, the CPU has to set in the DMA controller only once the addresses of the source and destination locations and the values to be held in the cycle register and the transfer counter.

Abstract: An apparatus and method for transferring high speed asynchronous data using a DMA controller. By using a conventional Universal Serial Asynchronous Receiver Transmitter (USART) with a small buffer, high speed asynchronous data can be manipulated by the DMA controller by use by other applications, such as wireless communication applications. The wireless communication applications includes Global System for Mobile communications (GSM), Code Division Multiple Access (CDMA), or Personal Digital Cellular (PDC). These wireless communication applications utilize high asynchronous data rates that would require more expensive USART with additional buffer capacity. In the receive mode, the high speed asynchronous data shifted into a DMA FIFO buffer from the USART. The data is then flushed into a host memory, such as a protocol stack by the DMA controller once the FIFO is full or if a timer expires. The data in the protocol stack is then manipulated by the wireless communication application.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. The memory can output data storage registers on the data communication connections during a predetermined number of consecutive clock cycles by adjusting a burst length of register data. The memory can also provide the register data in accordance to a defined clock latency value. The register data can include status data, operating setting data, manufacture identification, and memory device identification.

Abstract: The ManArray processor is a scalable indirect VLIW array processor that defines two preferred architectures for indirect VLIW memories. One approach treats the VIM as one composite block of memory using one common address interface to access any VLIW stored in the VIM. The second approach treats the VIM as made up of multiple smaller VIMs each individually associated with the functional units and each individually addressable for loading and reading during XV execution. The VIM memories, contained in each processing element (PE), are accessible by the same type of LV and XV Short Instruction Words (SIWs) as in a single processor instantiation of the indirect VLIW architecture. In the ManArray architecture, the control processor, also called a sequence processor (SP), fetches the instructions from the SIW memory and dispatches them to itself and the PEs. By using the LV instruction, VLIWs can be loaded into VIMs in the SP and the PEs.

Abstract: A combination of techniques to prevent deadlocks and livelocks in a computer system having a dispatcher and multiple downstream command queues. In one embodiment, a broadcast transaction that requires simultaneously available space in all the affected downstream command queues becomes a delayed transaction, so that the command queues are reserved and other transactions are retried until the broadcast transaction is completed. In another embodiment, a bail-out timer is used to defer a transaction if the transaction does not complete within a predetermined time. In yet another embodiment, a locked transaction that potentially addresses memory space controlled by a programmable attribute map is handled as a delayed transaction if there is less than a predetermined amount of downstream buffer space available for the transaction.

Abstract: Programmatic detection of time-gap defects in computer system hardware where data is corrupted without detection by the computer system. A detection module initiates data transfers between devices in a computer system. An interrupt service routine interrupts the process by inserting a delay into the data transfer. The detection module then checks for time-gap defects by determining if data was corrupted which went undetected by the computer system. The detection module may repeat the data transfer and insert successively longer delays until a time-gap defect is detected or until a maximum delay value is reached. The results of any time-gap defects found may be output to a user.

Abstract: Apparatus and methods, and computer program products are disclosed that accepts time-stamped information and feeds that information to a buffered system that consumes the information. The invention accepts an initial interval of the time-stamped information and when a pre-fill limit is reached, starts consumption of the data. The pre-fill limit is determined by monitoring the time stamp on the data that is ready to be consumed and the time stamp of data that has just been accepted. The difference between these time stamps provides an interval that represents the amount of time related to the data associated with the time-stamped information. Once the interval exceeds a pre-fill limit, the invention allows the buffered time-stamped information to be consumed. As the time-stamped information is consumed, the invention monitors the interval (other embodiments use the time stamp of data that is in the process of being consumed, or data that has just been consumed).