Abstract: An agent may be coupled to receive a clock signal associated with the bus, and may be configured to drive a signal responsive to a first edge (rising or falling) of the clock signal and to sample signals responsive to the second edge. The sampled signals may be evaluated to allow for the driving of a signal on the next occurring first edge of the clock signal. By using the first edge to drive signals and the second edge to sample signals, the amount of time dedicated for signal propagation may be one half clock cycle. Bandwidth and/or latency may be positively influenced. In some embodiments, protocols which may require multiple clock cycles on other buses may be completed in fewer clock cycles. For example, certain protocols which may require two clock cycles may be completed in one clock cycle. In one specific implementation, for example, arbitration may be completed in one clock cycle. Request signals may be driven responsive to the first edge of the clock signal and sampled responsive to the second edge.

Abstract: Briefly, in accordance with an embodiment of the invention, a method and apparatus to transfer information is provided, wherein the method includes monitoring activity on a bus during a transfer of information from a device using the bus and generating a direct memory access (DMA) request based on the bus activity.

Abstract: Apparatus and method for providing DMA transfers between an adapter card with or with out DMA capabilities and a system CPU with DMA capabilities. An adapter DMA controller circuit resides between the system CPU and the adapter card. This adapter DMA controller allows the system to run in immediate mode which allows the system CPU to talk to the adapter card as if the adapter DMA controller was not there. The system can also run in DMA mode. In this mode the system CPU sets up the system DMA controller and the adapter DMA controller. The adapter DMA controller takes over sending or receiving data to the adapter card and then requesting a DMA transfer with the system DMA controller. The transfer of data between the adapter DMA controller and the adapter does not use any system CPU resources such as the data and address busses. The system CPU is free to use the system resources to continue operation.

Abstract: A two-dimensional direct memory access system that maximizes processing resources in image processing systems. The present invention includes a two-dimensional direct memory access machine. Also, it employs a ping-pong style memory buffer to assist in the transfer and management of data. In certain applications of the invention, the type of data used by the invention is image data. The two-dimensional direct memory access machine transfers a specific cross sectional area of the image data to a processor. The efficient method of providing the processor only with the specific cross sectional area of the image data that is to be processed at a given time provides decreased processing time and a better utilization of processing resources within the two-dimensional direct memory access system.

Abstract: An external direct memory access unit includes an event recognizer recognizing plural event types, a priority encoder selecting for service one recognized external event, a parameter memory storing service request parameters corresponding to each event type and an external direct memory access controller recalling service request parameters from the parameter memory corresponding to recognized events and submitting them to a centralized transaction processor. The service request parameters include a priority for centralized transaction processor independent of the event recognition priority. The service request parameters may be stored in the form of a linked list. The service requests are preferably direct memory accesses which may include writes to the parameter memory for self modification. The centralized transaction processor may signal an event to event recognizer upon completion of a requested data transfer.

Abstract: A modular electronic device has a cabinet frame, a plurality of push-in modules with module frames retained in the cabinet frame side-by-side, and printed circuit boards mounted in the module frames, and electronic components carried by said printed circuit boards. Each of these modules has autonomous data transmitting connections for communicating directly with each of the other ones of the modules.

Abstract: A transceiver system is described. A secondary memory module is coupled to a primary channel for receiving data and signals from a controller. The secondary memory module comprises a memory and a secondary channel for transmitting the data and control signals to the memory. The secondary memory module further comprises a transceiver coupled to the primary channel and the secondary channel. The transceiver is designed to electrically isolate the secondary channel from the primary channel. The transceiver is a low latency repeater to permit the data and the control signals from the controller to reach the memory, such that a latency of a data request from the controller is independent of a distance of the transceiver from the controller.

Abstract: A digital system has a host processor 200 with a bus controller 210 and peripherals 220(0)-220(31) interconnected by an interconnect bus 230. 32 peripherals are share a common strobe line (nSTROBE[0]) on an embodiment of the interconnect bus in a first subdomain. Additional sub-domains, such as sub-domain 260, can be likewise connected to interconnect bus 230. Additional strobe lines nSTROBE(n) are used to select a particular sub-domain in response to an address presented to bus controller 210 by CPU 200. An interconnect bus transaction is synchronized in background so that a current cycle is not delayed. A first write cycle 1500 is completed as a no-wait state transaction, while immediately following second write cycle 1510 is delayed while synchronization circuit 1400 completes the synchronization of the first write cycle. nSTROBE pulse 1520 indicates first write transaction 1500 while nREADY pulse 1530 indicates the completion of a no-wait state first write transaction 1500.

Abstract: A direct memory access function for servicing real-time events, ensures that any parameter reloads occur during times when the direct memory access channel is idle and guarantees completion before the channel begins active operation again. The direct memory access channel whose parameters are to be updated is disabled during the update cycle. This ensures that no requests are processed until the new parameters have been written to the direct memory access channel parameters. A second direct memory access channel may be used to reload the data transfer parameters permitting a self-modifying direct memory access function.

Abstract: A data processing system, and a method of operating a data processing system. The data processing system comprises a clock generator for generating a system clock signal, and a memory unit having a plurality of memory modules for storing data. The data processing system further comprises a memory controller coupled to the clock generator for receiving the system clock signal therefrom, and coupled to the memory modules for outputting memory address and control signals to said modules. The memory controller is programmable to have different clock-to-output delays, on signals from the memory controller end, based on the memory installed in the system.

Abstract: An external direct memory access unit includes an event recognizer storing plural event types in an event register, a priority encoder selecting for service one recognized external event, a parameter memory storing service request parameters corresponding to each event type and an external direct memory access controller recalling service request parameters from the parameter memory corresponding to recognized events and submitting them to a centralized direct memory access unit. The external direct memory access controller may update source or destination address for a next occurrence of an event type by adding an offset or updating an address pointer to a linked list. The centralized direct memory access unit queues data transfer parameters on a priority channel basis and stalls the external direct memory access controller for a particular priority level it the corresponding queue is full.

Abstract: An audio record/playback system is configured using a RAM containing PC buffers and a sound input/output board which is equipped with another RAM containing P buffers and R buffers as well as a digital audio circuit. At a playback mode, waveform sample data consisting of waveform samples are subjected to burst transfer using a PCI bus from the PC buffer to the P buffer in a first half duration of each sampling period with respect to one channel. In a second half duration, one of the waveform samples is transferred from the P buffer to the digital audio circuit, wherein it is subjected to digital audio processing. Thus, the waveform sample data are played back in response to prescribed timings synchronized with sampling periods. At a record mode, waveform sample data corresponding to sounds to be picked up are supplied to the digital audio circuit, from which they are transferred to the R buffer. Then, the waveform sample data are transferred to the PC buffer.

Abstract: According to the present invention, a method for very fast calculation of the earliest command issue time for a new command issued by a memory controller is disclosed. The memory controller includes N page status registers each of which includes four page timers such that each of the page timers store a period of time between a last issued command to the particular page and a predicted next access to the memory, wherein the next access to the same page can be “close”, “open”, “write” or “read”. An incoming new command is received and it is then determined how long a particularly page access has to wait before the issue. An appropriate contents of a command timing lookup table is selected by the new command. A new time value is written into appropriate page timers that has to be inserted between the new command and a possible next access to the same page.

Abstract: The present invention relates to a process and a device for modifying code sequences written into a first memory (2) of a medium. A central processing unit (1) executes code sequences and the first memory contains a main program comprising at least one code sequence executable by the central processing unit (1). The first memory also comprises a second, programmable nonvolatile memory (3), and a third working memory (4). A branch table TAB_DER contained in the second programmable memory contains at least one field containing reference data for a new code sequence stored in one of the memories. Branching instructions allow a deferred branch from the executed code sequence to the new code sequence written into one of the three memories. Instructions in the new code sequence allow the return to a point of the code sequence executed before the branch.

Abstract: A bus control device having a plurality of devices such as a processor or a DMAC which can be a bus master accessing a system bus. When the processor transfers data to a memory or a processing circuit, a system bus controller for the processor and a system bus controller for the memory or a system bus controller for the processing circuit access the system bus within an accessible minimum time with each of input/output signals. When the DMAC transfers data to the memory or the processing circuit, a system bus controller for the DMAC and the system bus controller for the memory or the system bus controller for the processing circuit access the system bus within the accessible minimum time with each of the input/output signals.

Abstract: A source module, a destination module, or both modules, that are used in a data transfer, signal over an internal communication bus to a bus master when the addressed storage location in the data transfer comprises a single point address type memory, the addressed module drives an active signal on an address increment disable line in the control bus. In response to the active signal on the address increment disable line, the bus master inhibits changing the address for the duration of the data transfer. The module also drives an active signal on an expansion address off boundary line in the control bus when an internal expansion address of the module is not aligned with a natural boundary of a data bus of the internal communication bus to allow the bus master to adjust the width of the data transfer.

Abstract: An apparatus and method are implemented to track and manage system cycles stolen from a data processor by other processors in a multiprocessor data processor system. The apparatus and method maximize data throughput and minimize unused cycle resources within the multiprocessor data processing system.

Abstract: A data transfer control apparatus is disclosed for controlling conflict of data transfer on a data bus connected to a microprocessor through a bridge circuit. The bridge circuit includes a monitoring unit. When an execution instruction for MPC transfer is issued during DMA transfer, the monitoring unit measures a time period over which the data bus is to be occupied with the MPC transfer. When the PCI bus is to be occupied with the MPC transfer for a predetermined time period, the monitoring unit does not suspend the DMA transfer but performs the MPC transfer after the completion of the DMA transfer.

Abstract: A direct memory access control system supplies the respective status signals indicating timings of the read data effective state or writable state between the input/output interface and memory interface, both interfaces maintain the read data effective state and writable state of the input/output memory and synchronous memory under control until the later timing comes up. Consequently, it is possible to match the read data effective timing and writable timing of the synchronous memory and input/output memory, thus making possible flyby transfer of data between both memories.

Abstract: A digital system has a host processor 200 with a bus controller 210 and peripherals 220(0)-220(31) interconnected by an interconnect bus 230. 32 peripherals are share a common strobe line (nSTROBE [0]) on an embodiment of the interconnect bus in a first subdomain. Additional sub-domains, such as sub-domain 260, can be likewise connected to interconnect bus 230. Additional strobe lines nSTROBE(n) are used to select a particular sub-domain in response to an address presented to bus controller 210 by CPU 200. A FIFO is provided on a peripheral device to reduce data transfer access time. When the FIFO is almost empty, a FIFO management state machine requests a DMA transfer by asserting the nDMA_REQ signal on the interconnect bus, thus transitioning from idle state 2300 to transfer state 2310 along arc 2301. The DMA controller transfers several data words until the FIFO becomes full, as indicated by word_cpt=FIFO_size.

Abstract: A two-dimensional direct memory access system that maximizes processing resources in image processing systems. The present invention includes a two-dimensional direct memory access machine. Also, it employs a ping-pong style memory buffer to assist in the transfer and management of data. In certain applications of the invention, the type of data used by the invention is image data. The two-dimensional direct memory access machine transfers a specific cross sectional area of the image data to a processor. The efficient method of providing the processor only with the specific cross sectional area of the image data that is to be processed at a given time provides decreased processing time and a better utilization of processing resources within the two-dimensional direct memory access system.

Abstract: The parallel or printer port in a personal computer can receive data from the memory under the control of the direct memory access (DMA) controller, releasing processor resources. The processor enables the parallel port, which then indicates to the DMA controller the desire to transfer data. A state machine in the parallel port, along with the associated circuitry, responds to the transfer of the data to the parallel port and then controls the transfer of the data to the attached device, usually a printer. The state machine causes an interrupt to the processor when the transfer is complete or on receipt of errors from the external device. The state machine also communicates with the DMA controller to repeat the transfer process until the transfer is complete or an error occurs. Various DMA channels and parallel port locations can be used. Direct transfers by the processor are blocked during DMA controller handled transfers.

Abstract: A peripheral device and peripheral device control method assure the immediacy of status information while opening the greatest possible bandwidth when communicating status information using a USB interface enabling simultaneous access to a plurality of peripheral devices. A first transfer function enables sending status information to a peripheral device such as a printer using the USB bulk transfer type, and a second transfer function enables sending status information using the USB interrupt transfer type. Status information sent in response to a host request where the host can control the timing of status information transfers is sent by bulk transfer using the first transfer function, thereby assuring bandwidth for bulk transfers. Autonomous status information communicated at a timing unknown to the host is communicated by the second transfer function using the short transfer period interrupt transfer type, thereby assuring the immediate communication of the status information.

Abstract: A system for time-ordered execution of load instructions. More specifically, the system enables just-in-time delivery of data requested by a load instruction. The system consists of a processor, an L1 data cache with corresponding L1 cache controller, and an instruction processor. The instruction processor manipulates an architected time dependency bit field of a load instruction to create a Distance of Dependency (DoD) bit field. The DoD bit field holds a relative dependency value which is utilized to order the load instruction in a Relative Time-Ordered Queue (RTOQ) of the L1 cache controller. The load instruction is sent from RTOQ to the L1 data cache at a particular time so that the data requested is loaded from the L1 data cache at the time specified by the DoD bit field. In the preferred embodiment, an acknowledgement is sent to the processing unit when the time specified is available in the RTOQ.

Abstract: The present invention relates generally to the field of disc controllers, and more specifically to an efficient buffer manager for a disc controller. A state machine in the buffer manager is provided which is responsive to a clock controlled by a single frequency base clock signal and a speed selection signal which indicates the speed of the buffer memory and which is designed to provide a base clock signal for the state machine having a fixed base period and an extended second portion of the cycle period which is extended to reflect the time of the RAMs cycle, plus the necessary time to allow for circuit delays and the like. Thus, different speed RAMs can be used in association with the buffer manager designed in this manner, while always controlling access for reading and writing to the RAM during a single complete cycle of the buffer manager. This allows for direct gating of all control signals to the buffer RAM, simplifying the design of the buffer memory controller and its associated logic.

Abstract: The present invention provides a data processing apparatus and method for controlling timing of transfer requests. The data processing apparatus comprises a bus for interconnecting a number of logic units, data being transferable between the logic units via the bus. A first logic unit is arranged to issue onto a bus a transfer request and a type signal indicating the type of the transfer request, and a second logic unit is arranged to receive the transfer request from the bus and to perform an operation in response to the transfer request. In accordance with the present invention, the first logic unit is arranged to encode within the type signal a timing indication used to control the timing of the receipt of the transfer request by the second logic unit. By this approach, the performance of the data processing apparatus can be increased, since the performance of transfer requests can be governed directly by the actual performance of the logic unit issuing the transfer request.

Abstract: A synchronous dynamic random access memory (“SDRAM”) operates with matching read and write latencies. To prevent data collision at the memory array, the SDRAM includes interim address and interim data registers that temporarily store write addresses and input data until an available interval is detected where no read data or read addresses occupy the memory array. During the available interval, data is transferred from the interim data register to a location in the memory array identified by the address in the interim array register. In one embodiment, the SDRAM also includes address and compare logic to prevent reading incorrect data from an address to which the proper data has not yet been written. In another embodiment, a system controller monitors commands and addresses and inserts no operation commands to prevent such collision of data and addresses.

Abstract: The present invention is directed to an improved direct memory access (DMA) controller for executing commands having an improved instruction set. In accordance with one aspect of the present invention, a DMA controller is provided having an enhance command set. Specifically, a DMA controller is provided having the ability to perform a memory fill command. Thus, in accordance with one aspect of the invention, a method is provided for controlling a DMA controller to execute a memory fill command, wherein the method obtains a starting address, a segment length identifier, and a data value. Preferably, this information is obtained by reading successive bytes from external memory. The method then writes the data value to a plurality of consecutive locations in the memory, beginning at the starting address, wherein the number of consecutive locations written to is equal to the segment length identifier.

Abstract: The parallel or printer port in a personal computer can receive data from the memory under the control of the direct memory access (DMA) controller, releasing processor resources. The processor enables the parallel port, which then indicates to the DMA controller the desire to transfer data. A state machine in the parallel port, along with associated circuitry, responds to the transfer of the data to the parallel port and then controls the transfer of the data to the attached device, usually a printer. The state machine causes an interrupt to the processor when the transfer is complete or on receipt of errors from the external device. The state machine also communicates with the DMA controller to repeat the transfer process until the transfer is complete or an error occurs. Various DMA channels and parallel port locations can be used. Direct transfers by the processor are blocked during DMA controller handled transfers.

Abstract: Provided is a method for preventing memory overrun in a data transmission system. The data transmission system includes a CPU, an HDLC controller having a receive buffer, and a memory shared between the CPU and the HDLC controller. The method includes initializing the HDLC controller by writing to the shared memory. The CPU terminates data reception at the HDLC controller by sending a data reception termination instruction to the controller. The CPU receives an acknowledgement instruction from the HDLC controller responsive to sending the data reception termination instruction. The CPU creates an empty buffer in the shared memory responsive to receiving the acknowledgement instruction from the controller. Thereafter, the CPU makes receive descriptors included in the shared memory point to the empty buffer. The HDLC controller subsequently transfers the data contained in its receive buffer to the empty buffer in shared memory.

Abstract: A system and method of detecting events such as DMA requests, computation operations, configuration set-up operations, occurring in a processing system which are performed by functional system blocks within the system by using logic flags stored in registers within each of the functional system blocks. The registers are coupled to the CPU on dedicated signal lines. Each time a functional block completes an operation or function it updates its corresponding logic flag. The CPU monitors the state of the flags to determine whether certain events have taken place in the system in order to sequentially coordinate functions and operations within the system without the use of interrupt signals on the system bus.

Abstract: A method and system for storing an information signal for subsequent recording are disclosed. An incoming information signal is received, and a starting point in the information signal is identified. At least a portion of the information signal is stored in a memory as it is received, including the identified starting point. A command to record the information signal is received subsequent to the starting point of the information signal, and the information signal is recorded from the memory beginning with the starting point such that the information signal is recorded in its entirety. If the information signal is not recorded, the information signal will continue to be saved until the capacity of the memory is reached at which point the information signal may be recorded over the previously saved information signal. An end point of an information signal may be identified as the starting point of a new information signal desired to be recorded.

Abstract: A DMA controller has a cycle register in which the number of data transfer cycles to be performed in response to a single DMA transfer request is set, a cycle counter for counting the number of data transfer cycles actually performed, and a transfer counter for holding a value that is updated every time the number of data transfer cycles as held in the cycle register are completed. From the start to the end of the data transfer cycles, the number held in the cycle register is kept unchanged, and the data transfer cycles are performed until the value held in the transfer counter becomes equal to a predetermined value. In this configuration, even in a case where a predetermined number of DMA transfer cycles are performed in response to a single DMA transfer request and a plurality of DMA transfer requests are made in succession, the CPU has to set in the DMA controller only once the addresses of the source and destination locations and the values to be held in the cycle register and the transfer counter.

Abstract: A memory component on a single integrated circuit includes a RAM, one or more configuration registers, and an associated controller. The behavior of the memory component, including selection from a number of different operating modes, is controllable via configuration register mode bits. The various modes include several transfer-length modes, where each mode corresponds to data transfers of a predetermined length. Based on the mode selection specified by the mode bits, the controller determines the length of the data transfers.

Abstract: An audio record/playback system is configured using a RAM containing PC buffers and a sound input/output board which is equipped with another RAM containing P buffers and R buffers as well as a digital audio circuit. At a playback mode, waveform sample data consisting of waveform samples are subjected to burst transfer using a PCI bus from the PC buffer to the P buffer in a first half duration of each sampling period with respect to one channel. In a second half duration, one of the waveform samples is transferred from the P buffer to the digital audio circuit, wherein it is subjected to digital audio processing. Thus, the waveform sample data are played back in response to prescribed timings synchronized with sampling periods. At a record mode, waveform sample data corresponding to sounds to be picked up are supplied to the digital audio circuit, from which they are transferred to the R buffer. Then, the waveform sample data are transferred to the PC buffer.

Abstract: It is determined that, when starting of direct memory access is newly requested, whether or not the direct memory access can be started, using a rate of using the bus at the present time by data transfer performed by all the direct memory access controllers which have already started direct memory access until then and all the processors, a data transfer rate needed by the newly requested direct memory access, a size of data which is transferred in one direct memory access operation or a size of data which a memory can accept, a latency for accessing the memory, and a latency for bus-right arbitration. The newly requested direct memory access is started when it is determined that the direct memory access can be started. Starting of the newly requested direct memory access is kept waiting when it is determined that the direct memory access cannot be started.

Abstract: A communication system includes a communication control section which may receive bus use requests of both of a DV camera/recorder (50) which becomes an output machine on a serial bus (60D) and a DV deck (40) which becomes an input machine on the serial bus (60D), may check whether or not the serial bus (60D) which were requested to be used is in use, may open the serial bus (60D) to the DV camera/recorder (50) and the DV deck (40) which issued the use requests, may protect a connection between the DV camera/recorder (50) and the DV deck (40), may open a serial bus (60A) to an IRD receiver (10) and a mini disc (20) which issued use requests and which may protect a connection between the IRD receiver (10) and the mini disc (20).

Abstract: A system for delaying the release of a memory space holding a data block in a disk drive controller until an acknowledge signal is received. The present invention is implemented in a disk drive controller having a memory buffer. The disk drive controller receives a request for data from a host device. The disk drive controller then reads the data block from the disk and stores the data block in the memory buffer. The data block is then transmitted to the host device. The host device then either transmits an acknowledge signal or a busy signal. The disk drive controller does not release the data block unless an acknowledge signal has been received.

Abstract: A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a response request 103 for said access requests to said CPU in synchronism with its internal operation. The CPU performs the access requests for the memory, and fetches data from the outside or outputs the data to the outside in response to and in synchronism with the response request 103 from the accessed memory and according to the kinds of said access requests.

Abstract: An improved bus bridge in a computer system for connecting a first data bus and a second data bus, said bus bridge having means for connecting said first and second buses, means for receiving an address representing a transaction on said first bus, means for decoding said address, means for claiming the transaction on said first bus corresponding to said address, and means for passing said transaction to said second bus, wherein the improvement comprises: (a) means for determining if said address decodes into one of a plurality of address ranges programmed in said bridge device; (b) means for determining a timing speed for the transaction corresponding to said address in accordance with the address range for said address; and (d) means for asserting a signal for claiming the transaction at said determined timing speed.

Abstract: An ATA-compatible drive interface with error correction and detection capabilities is disclosed. Being fully ATA backward compatible, this interface functions with the same physical cable and connectors as current ATA systems, employs bus drivers that are the same as or backward compatible with those provided by earlier versions of the ATA standard and uses signals with cable signal transitions no faster than those presently seen by current ATA devices. The error detection feature indicates when a data block is erroneously transferred between the device and host; the error correction feature identifies the words transmitted in error and corrects those words on the receiving side of the interface. So that ATA backward compatibility is maintained, the data integrity checking feature does not require additional words in a data transfer, and the data correction feature does not require new data transfer protocols or additional data transfer overhead.

Abstract: It is an object to provide a printer apparatus, a control method of such an apparatus, and a printer system, in which a proper control can be performed in consideration of a change in network load. When a load of a transmission path is measured and a data reception from a host is interrupted, a waiting time of the data is extended in accordance with the measured load, thereby realizing the object. The set operating conditions are transmitted to the host and are also automatically set into the other printers connected to the network to which the printer is connected via the host, thereby realizing the object.

Abstract: A synchronous DMA burst transfer method is provided for transferring data between a host device and a peripheral drive device connected by an ATA bus. The method provides synchronous data transfer capability in an asynchronous system by having one device in charge of both a strobe signal and a data signal. When a host read or write command is delivered to the peripheral drive device, the peripheral device decides when to start the synchronous DMA burst. For a read command, the peripheral device requests the synchronous DMA burst then drives a data word onto the ATA bus after the host acknowledges that it is ready to begin the burst. After allowing time for the data signal to settle, the peripheral device toggles a strobe signal from a high state to a low state. The host sees the edge of the strobe signal at which time the host latches the data word on the bus. Additional data words can be driven on the bus and the strobe signal can be retoggled to latch the additional data words into the host.

Abstract: The present invention relates generally to the field of disc controllers, and more specifically to an efficient buffer manager for a disc controller. A state machine in the buffer manager is provided which is responsive to a clock controlled by a single frequency base clock signal and a speed selection signal which indicates the speed of the buffer memory and which is designed to provide a base clock signal for the state machine having a fixed base period and an extended second portion of the cycle period which is extended to reflect the time of the RAMs cycle, plus the necessary time to allow for circuit delays and the like. Thus, different speed RAMs can be used in association with the buffer manager designed in this manner, while always controlling access for reading and writing to the RAM during a single complete cycle of the buffer manager. This allows for direct gating of all control signals to the buffer RAM, simplifying the design of the buffer memory controller and its associated logic.

Abstract: A source module, a destination module, or both modules, that are used in a data transfer, signal over an internal communication bus to a bus master when additional time is needed to participate in the data transfer. If either the source module, destination module or both modules require more time, the bus master, in response to an active stretch bus access signal or signals for the module or modules, automatically extends the bus access cycle until all modules requiring additional time signal over the internal communication bus that they are ready to proceed with the data transfer. Consequently, the source module, destination module, or both modules can re-time a bus access cycle to accommodate the characteristics of that particular module. When the addressed storage location in the data transfer comprises a single point address type memory, the addressed module drives an active signal on an address increment disable line in the control bus.

Abstract: A microprocessor 1 is described which includes a direct memory access (DMA) circuitry 143. DMA 143 is interconnected with a program memory 23 and a data memory 22 and is operational to transfer data to or from these memories. DMA 143 is interconnected with a peripheral bus 110 and thereby to various peripherals internal to microprocessor 1. DMA 143 is also interconnected with an external memory interface 103 and thereby to various external memory circuits and peripherals external to microprocessor 1. An auxiliary channel control circuitry 160 provides DMA transfers by interacting with a peripheral such as host port 150 which has its own address generation circuitry. DMA 143 provides frame synchronization for triggering a frame transfer, or group of transfers. DMA 143 is auto-initialized through registers. DMA action complete pins DMAC0-3 indicate DMA status to external devices.

Abstract: A method for transferring DMA data between the video port and the host interface in a multimedia processor is disclosed. The method includes determining whether one frame data should be transferred between the host interface and the video port; preloading some DMA instructions in the frame buffer and setting the DMA register to be fitted for the DMA operation; and fetching the preloaded instructions from the frame buffer subsequently by the DMA controller to perform video data transfer at a predetermined data bandwidth. According to this invention, the time consumption of a microprocessor for programming the DMA controller is reduced, thereby enhancing the data transfer rate between the host interface and video port of the multimedia computer system.

Abstract: The parallel or printer port in a personal computer can receive data from the memory under the control of the direct memory access (DMA) controller, releasing processor resources. The processor enables the parallel port, which then indicates to the DMA controller the desire to transfer data. A state machine in the parallel port, along with associated circuitry, responds to the transfer of the data to the parallel port and then controls the transfer of the data to the attached device, usually a printer. The state machine causes an interrupt to the processor when the transfer is complete or on receipt of errors from the external device. The state machine also communicates with the DMA controller to repeat the transfer process until the transfer is complete or an error occurs. Various DMA channels and parallel port locations can be used. Direct transfers by the processor are blocked during DMA controller handled transfers.

Abstract: A printer system includes a printer controller and a printer connected to each other by a cable according to IEEE Standard 1394. The printer controller and the printer each accepts data transmitted thereto when device identification data assigned thereto agrees with transmission destination identifying data accompanying the transmitted data. The printer controller and the printer are assigned identical device identification data. The printer controller and printer decide a first transmission-permitted time period in which the printer controller transmits data to the printer and a second transmission-permitted time period in which the printer transmits data to the printer controller. The first and second transmission-permitted time periods are separated from each other. The printer controller transmits image data accompanied by the transmission destination identifying data to the printer in packet units in the first transmission-permitted time period.

Abstract: The present invention provides an improved disc drive. In one embodiment of the present invention a disc drive capable of spinning a disc, which contains more than one type of data is disclosed. A first type of data is associated with a first speed, and a second type of data is associated with a second speed that is faster than the first speed. The disc drive includes a drive mechanism, which may spin the compact disc at the first and second speeds and retrieve data from the compact disc at either speed. The disc drive also includes an elastic buffer, which is in communication with the drive mechanism. The buffer receives data from the drive mechanism at a variable input data rate and outputs data at a variable output data rate. Whereby when the drive mechanism spins the compact disc at the second speed the buffer may receive the first type of data without causing the drive mechanism to slow down to the first speed, and the buffer may output the first type of data at the variable output data rate.