Abstract: A multi-core processor system includes a given configured to queue an interrupt process of a software interrupt request to the given core, and execute queued processes in the order of queuing at the given core; execute preferentially an interrupt process of a hardware interrupt request to the given core over a process under execution at the given core; determine whether the software interrupt request is a specific software interrupt request; and perform control to preferentially execute the interrupt process without queuing, upon determining that the software interrupt request is the specific software interrupt request.

Abstract: A method includes recording a user-level interrupt as undeliverable in a mailbox at least partially based on an interrupt domain identifier and an interrupt recipient identifier included in a user-level interrupt message associated with the user-level interrupt. The recording is at least partially based on an indication that the user-level interrupt is undeliverable to a recipient application thread executing on a processor core of a plurality of processor cores in a multi-core system.

Abstract: A method for interrupt processing includes setting a buffer for buffering data packets received by a front-end or back-end of the virtual machine and setting a timer for timing data buffering time; determining, after receiving the data packets from the front-end or the back-end, whether the received data packets are interacting data packets and determining whether to enable or postpone the timer, and buffering the received data packets by the buffer and enabling the timer in the case that the data packets are not the interacting data packets; and sending the buffered data packets through a virtual machine manager to the back-end or the front-end of the virtual machine for processing in the case that the buffer reaches a maximum capacity limit or the timer reaches a predetermined time.

Abstract: Approaches for communicating data from a source device to a target device. In one approach, a communicated data value is segmented into a plurality of data chunks at the source device. A sequence of interrupt transactions is transmitted from the source device to a system bus. The transmitting of each interrupt transaction in the sequence includes transmitting a target identifier on an address bus of the system bus, and the target identifier of each interrupt transaction in the sequence includes a respective one of the data chunks. The sequence of interrupt transactions from the system bus is received at the target device. The communicated data value is reassembled at the target device from the data chunks in the target identifier of the interrupt transactions in the sequence.

Abstract: A technique for interrupt moderation allows coalescing interrupts from a device into groups to be processed as a batch by a host processor. Receive and send completions may be processed differently. When the host is interrupted for receive completions, it may check for send completions, reducing the need for interrupts related to send completions. Timers and a counter allow coalescing interrupts into a single interrupt that can be used to signal the host to process multiple completions. The technique is suitable for both dedicated interrupt line and message-signaled interrupts.

Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.

Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.

Abstract: Various technologies and techniques are disclosed that provide fast context switching. One embodiment provides a method for a context switch comprising preloading a host virtual machine context in a first portion of a processor, operating a guest virtual machine in a second portion of the processor, writing parameters of the host virtual machine context to a memory location shared by the host virtual machine and the guest virtual machine, and operating the host virtual machine in the processor. In this manner, a fast context switch may be accomplished by preloading the new context in a virtual processor, thus reducing the delay to switch to the new context.

Abstract: The present application relates to a method and an apparatus for adjusting a period of clock interruption. The method comprises: determining a number of processes in a run-queue of a processor; and determining the period of clock interruption for use in a run state of the processor such that the period of clock interruption for use when the number of the processes is greater than a reference threshold is less than the period of clock interruption for use when the number of the processes is not greater than the reference threshold. The apparatus comprises a first determination block and a second determination block. With the method and apparatus according to the embodiment of the application, it is possible to dynamically adjust the period of clock interruption such that the period of clock interruption for use in the run state of the processor can be changed according to needs with flexibility.

Abstract: Efficient techniques are described for identifying active interrupt requests to improve performance and reduce power requirements in a processor system. A method to identify active sampled interrupt requests begins with scanning groups of the sampled interrupt requests one group at a time to identify an active interrupt request in any scanned group. A group of interrupt requests is an M/R priority of N sampled interrupt requests, M is the number of priority levels, and R is a resource sharing factor. A group selection circuit is updated to a new group in response to having identified an active interrupt request to improve the latency in processing high priority interrupt requests. Also, groups having active interrupt requests may be identified by early detection or look ahead circuitry. The scanning of groups of interrupt requests may be stopped until the next interrupt request sample point has been reached to reduce power utilization.

Abstract: A technique for interrupt moderation allows coalescing interrupts from a device into groups to be processed as a batch by a host processor. Receive and send completions may be processed differently. When the host is interrupted for receive completions, it may check for send completions, reducing the need for interrupts related to send completions. Timers and a counter allow coalescing interrupts into a single interrupt that can be used to signal the host to process multiple completions. The technique is suitable for both dedicated interrupt line and message-signaled interrupts.

Abstract: Systems and methods are provided that forward or route data streams using a plurality of processors, while maintaining the correct sequence of data packets within the data stream. Each interface may be associated with a respective one processor such that data packets received by an interface are handled by its respective one processor. Once a data packet is received by an interface, the processor associated with the interface may determine whether the received data packet is intended for another interface associated with another respective one processor. If the processor determines that the data packet is intended for another interface, the data packet may be forwarded to the processor associated with the other interface.

Abstract: An apparatus adapts a pre-designed circuit module not supporting a power management protocol to a power management protocol. The apparatus disconnects a bus interface, disables interrupt and stops a clock to the pre-designed circuit module on a external idle request signal.

Abstract: In an embodiment, a system comprises a memory system configured to store a data structure. The data structure stores at least an interrupt request state for each destination in each of a plurality of guests executable on the system. The interrupt request state identifies which interrupts have been requested at the corresponding interrupt controller in the corresponding guest of the plurality of guests. A guest interrupt manager is coupled to receive an interrupt message targeted at a first destination in a first guest of the plurality of guests, and the guest interrupt manager is configured to update the interrupt request state in the data structure that corresponds to the first destination and the first guest.

Abstract: A network device may include a line interface to receive and transmit data units, a memory including instructions associated with a user space and a kernel space that are executable by a processor, the user space including a first-in-first-out (FIFO) region for storing the data units and corresponding metadata, where the kernel space writes the data unit and the corresponding metadata to the FIFO region, the metadata including a next pointer that identifies a memory address for storing the next data unit in the FIFO region, a user space process determines whether to transmit or drop the data unit, the user space process being a single process, and the user space transmits the data unit from the FIFO region without involving the kernel space when the user space process issues a command.

Abstract: A system, method and article of manufacture for an accelerated processing device (APD) to request a central processing unit (CPU) to process a task, comprising enqueuing a plurality of tasks on a queue using the APD, generating a user-level interrupt and transmitting to the CPU the plurality of tasks in the queue using an interrupt handler associated with a CPU thread.

Abstract: Provided is an apparatus of processing an interrupt, the apparatus including: an interrupt queue storing the input device interrupt when a target virtual machine to process an input device interrupt generated by a user input device is not scheduled; and an interrupt inspector judging whether a processing time of the input device interrupt stored in the interrupt queue reaches a threshold and when the processing time of the input device interrupt reaches the threshold, granting a priority higher than an initial value to the virtual machine to process the corresponding interrupt.

Abstract: An interrupt detection apparatus includes a detection address region storing unit configured to store an address region, as a detection address region, to be detected in accordance with a first interrupt message having address information, an issuance interrupt information storing unit configured to store address information of a second interrupt message as issuance interrupt information, an interrupt message detection unit configured to determine that the first interrupt message corresponds to the detection address region, and an interrupt issuing unit configured to issue the second interrupt message having the issuance interrupt information when it is determined that the first interrupt message corresponds to the detection address region.

Abstract: A computer-implemented system and method for a lock-less, zero data copy messaging mechanism in a multi-core processor for use on a modem in a telecommunications network are described herein. The method includes, for each of a plurality of processing cores, acquiring a kernel to user-space (K-U) mapped buffer and corresponding buffer descriptor, inserting a data packet into the buffer; and inserting the buffer descriptor into a circular buffer. The method further includes creating a frame descriptor containing the K-U mapped buffer pointer, inserting the frame descriptor onto a frame queue specified by a dynamic PCD rule mapping IP addresses to frame queues, and creating a buffer descriptor from the frame descriptor.

Abstract: Disclosed is a system with multiple virtual machines passing I/O requests via a shared memory space. A flag in shared memory is set to a first state in response to a first hypervisor I/O interrupt to indicate that an I/O processing routine is active (running). I/O requests are retrieved from an I/O queue in the shared memory by the I/O processing routine. Based on an indicator that there are no I/O requests remaining in said I/O queue, the shared flag is set to a second state to indicate that the I/O processing routine is deactivated (sleeping). In response to said shared flag being in the second state, when new I/O requests are going to be made, a second hypervisor I/O interrupt is generated. In response to said shared flag being in said first state, I/O requests are inserted into the I/O queue without generating a second hypervisor I/O interrupt.

Abstract: Counter registers are shared among multiple threads executing on multiple processor cores. An event within the processor core is selected. A multiplexer in front of each of a number of counters is configured to route the event to a counter. A number of counters are assigned for the event to each of a plurality of threads running for a plurality of applications on a plurality of processor cores, wherein each of the counters includes a thread identifier in the interrupt thread identification field and a processor identifier in the processor identification field. The number of counters is configured to have a number of interrupt thread identification fields and a number of processor identification fields to identify a thread that will receive a number of interrupts.

Abstract: A system and method for writing, by a sender, a message into blocks of a memory space, the memory space being shared by the sender of the message and a receiver of the message, and sending, by the sender, an interrupt corresponding to the message.

Abstract: In accordance with certain embodiments of the present disclosure, an information handling system is provided. The information handling system may include a plurality of processors, each processor comprising multiple cores, a memory system coupled to the plurality of processors, and a controller coupled to the plurality of processors. The controller may be configured to: receive a local system management interrupt (SMI) signal regarding an error associated with at least one of the multiple cores, determine that the received local SMI signal triggers a global SMI based on a global SMI trigger rule, cause the plurality of processors to enter a global system management mode (SMM), and log the error in a shared resource shared by the plurality of processors during the global SMM.

Abstract: A source identification facility is provided that enables identification of the one or more types of adapters requesting an interrupt in order to facilitate processing of the interrupt. The adapter types are accessible to the operating system and are used to tailor processing by the operating system of the interrupt.

Abstract: Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption signals to a processor that a reply to a request is waiting on the queue. In order for the queue to take advantage of the interruption capability, it is enabled for interruptions.

Abstract: A method of determining request transmission priority subject to request content and transmitting request subject to such request transmission priority in application of Fieldbus communication framework in which the communication device determines whether the received requests have the priority subject to the respective content, and also determines whether there is any logical operation condition established, and then the communication device transmits the received external requests to the connected slave device as an ordinary request or priority request, preventing the slave device from receiving an important external request sent by the main control end or manager at a late time.

Abstract: In an embodiment, a method is provided. The method of this embodiment provides determining a flow context associated with a receive packet; and if the flow context complies with a dynamic interrupt moderation policy having one or more rules, generating an interrupt to process the receive packet substantially independently of an interrupt generated in accordance with an interrupt coalescing scheme (“coalesced interrupt”). Other embodiments are disclosed and/or claimed.

Abstract: A system (150) and method are disclosed that provide for the transfer of at least one packet (194) comprising data between a user space (152) and a kernel space (154) associated with a server (156) that is positioned in a distributed network arrangement (192) with a plurality of clients (158, 160, 162, 164). A distribution program (168) associated with the user space (152) is operable to accumulate the at least one packet (194). An application program interface (174) associated with the user space (152) transfers the at least one packet (194) to the kernel space (154) with a number of software interrupts (204). A driver (176) associated with the kernel space (154) is operable to distribute the at least one packet (194) to a subset of the plurality of clients (158, 160, 162, 164) in response to receiving the number of software interrupts (204). The number of software interrupts (204) is less than one software interrupt per packet per client.

Abstract: An embodiment of the present invention provides a network interface card (NIC), comprising an intelligent wake mechanism and a device driver associated with the intelligent wake mechanism and configured to agree with embedded software on a set of wake codes and wake behaviors associated with the wake codes such that when the NIC encounters a wake event, the NIC first adds the wake code to a command queue, then it drives a PME pin to high to wake a device connected to the NIC.

Abstract: Described embodiments provide a media controller for servicing contexts corresponding to data transfer requests from host devices. The media controller includes a context generator for generating contexts corresponding to the data transfer requests and a buffer for storing one or more context pointers, each pointer corresponding to a context and an action by a system module associated with the context. A context processor is configured to complete a context when the action by a media controller module associated with the context is complete, remove each pointer from the buffer associated with the completed context, and determine whether an interrupt corresponds to the completed context and removed pointer. If no interrupt corresponds to the completed context, the completed context is cleared. If an interrupt corresponds to the completed context, the interrupt is provided to a master processor and a completed context recycler for recycling the completed context pointer to the context generator.

Abstract: A device, method and software for handling multiple interrupts in a peripheral device are disclosed. The disclosed method includes, upon a hardware event in the peripheral device recording the hardware event and determining an acceptable period before which an interrupt should be generated to service the event. A timer at the peripheral device is adjusted as needed to maintain a value within the acceptable period. Upon expiry of the timer a single interrupt is generated to a processor interconnected to the peripheral device. In response to the single interrupt, software code is executed on the processor to service un-serviced hardware events for which an indicator has been recorded.

Abstract: A sponge process, for example within a driver in a guest operating system, is associated in a virtual computer system with each virtual processor in one or more virtual machines. When timer interrupts become backlogged, for example because a virtual machine is temporarily descheduled to allow other virtual machines to run, and upon occurrence of a trigger event, a conventional interrupt is disengaged and catch-up interrupts are instead directed into an appropriate one of the sponge processes. The backlogged timer interrupts are thus delivered without unfairly attributing descheduled time to whatever processes happened to be running while the catch-up interrupts are delivered, and without violating typical guest operating system timing assumptions.

Abstract: A technique for interrupt moderation allows coalescing interrupts from a device into groups to be processed as a batch by a host processor. Receive and send completions may be processed differently. When the host is interrupted for receive completions, it may check for send completions, reducing the need for interrupts related to send completions. Timers and a counter allow coalescing interrupts into a single interrupt that can be used to signal the host to process multiple completions. The technique is suitable for both dedicated interrupt line and message-signaled interrupts.

Abstract: Preventing time out of an IO transaction during CPU re-initialization by controlling the IO transaction so that the time when the IO transaction is continuously stopped during the CPU re-initialization process is within a predetermined time that prevents complete time out of an interrupt of an IO transaction. In a case where the IO transaction would be continuously stopped for greater than the predetermined time during a CPU re-initialization the IO transaction is stopped and restarted within the predetermined time. The status of the interrupt during such stopping and starting is stored so as not to loose the interrupt status during the interval between such stopping and starting.

Abstract: A system including an event monitor for monitoring at least one transmission link. Each event monitor receives transmission link addresses from an address sequencer and transmits related event data to a centralized storage register. The address sequencer also transmits the addresses to the storage register. The event monitor compares new event data for each address with old event data stored by the event monitor. If a difference is detected, the event monitor sends a strobe signal to the storage register, which stores the event data reflecting the difference and the related address data. The strobe signal is also sent to a signaling device, which sends an interrupt signal to cause a microprocessor to read the event and address data from the storage register. Optionally, the signaling device does not send an interrupt signal until a threshold number of strobe signals have been received.

Abstract: A method of determining request transmission priority subject to request source and transmitting request subject to such request transmission priority in application of Fieldbus communication framework in which the communication device determines whether the received requests have the priority subject to the respective source and also determines whether there is any logical operation condition established, and then the communication device transmits the received external requests to the connected slave device as an ordinary request or priority request, preventing the slave device from receiving an important external request sent by the main control end or manager at a late time.

Abstract: A cache managing unit creates a list of elements corresponding to each data block arranged based on a priority of writing data blocks to a magnetic disk apparatus, and when a group of elements corresponding to data blocks to be written to the same magnetic disk apparatus exists, provides a link connecting elements at both ends of the group. A write control unit searches, upon selecting a data block for writing, elements belonging to the list in descending order of priority, and if a link is set at an element corresponding to a data block to be written to a magnetic disk that cannot perform a writing, follows the link to search a subsequent element.

Abstract: A memory module including a plurality of memory banks, a memory control unit, and a built-in self-test (BIST) control unit is provided. The memory banks store data. The memory control unit accesses the data in accordance with a system command. The BIST control unit generates a BIST command to the memory control unit when a BIST function is enabled in the memory module. While the system command accessing the data in a specific memory bank exists, the memory command control unit has the priority to execute the system command instead of the BIST command testing the specific memory bank. Memory reliability of a system including the memory module is enhanced without reducing the system effectiveness.

Abstract: Managing Message Signaled Interrupts (MSIs). For example, a method of managing MSI requests in a computing system may include receiving a plurality of MSI requests from one or more components of the computing system; directing data of the plurality of MSI requests to be stored sequentially, according to a First In First Out (FIFO) order, in successive entries of a FIFO structure defined in a main memory of the computing system; and directing a processor of the computing system to retrieve data of one or more of the plurality of MSI requests from the FIFO structure to be processed according to the FIFO order. Other embodiments are described and claimed.

Abstract: An information processing system is provided which includes a plurality of system resources, and an event queue having a maximum number of entries. An event recording mechanism of the information processing system is operable to make entries regarding events in the event queue, wherein the entries are limited to a predetermined number of active entries in the event queue per each type of event per each of the system resources. In a particular embodiment, the number of entries per each type of event for each of the system resources is limited to one.

Abstract: A packet relaying apparatus includes queues holding packet information, and queue control units controlling dequeueing. The dequeueing means transmission of packet information from a queue of a previous stage to a queue of a next stage. The packet relaying apparatus further includes a packet information control unit that, on receiving packet information to be dequeued at the time of dequeueing, returns discard information and data volume corresponding to the received packet information, a first bandwidth adjusting unit that, on determining that the received packet has been discarded, discards the packet information, maintains a usable bandwidth, and transfers the discard information and the data volume to the previous stage, and a second bandwidth adjusting unit that, on receiving the discard information and the data volume from the next stage, adds the data volume to the usable bandwidth and transfers the discard information and the data volume to a previous stage.

Abstract: A method for allowing simultaneous parameter-driven and deterministic simulation during verification of a hardware design, comprising: enabling a plurality of random parameter-driven commands from a random command generator to execute in a simulation environment during verification of the hardware design through a command managing device; and enabling a plurality of deterministic commands from a manually-driven testcase port to execute in the simulation environment simultaneously with the plurality of random parameter-driven commands during verification of the hardware design through the command managing device, the plurality of deterministic commands and the plurality of random parameter-driven commands each verify the functionality of the hardware design.

Abstract: In one embodiment, a method includes receiving an incoming posted transaction in a processor complex from a peripheral device, determining if the transaction is an interrupt transaction, and if so routing it to a first queue, and otherwise routing it to a second queue. Other embodiments are described and claimed.

Abstract: Interrupt frequency control by estimating processor load in the peripheral adapter provides adaptive interrupt latency to improve performance in a processing system. A mathematical function of the depth of one or more queues of the adapter is compared to its historical value in order to provide an estimate of processor load. The estimated processor load is then used to set a parameter that controls the frequency of an interrupt generator, which may be controlled by setting an interrupt queue depth threshold, packet frequency threshold or interrupt hold-off time value. The mathematical function may be the ratio of the transmit queue depth to the receive queue depth and the historical value may be predetermined, user-settable, obtained during a calibration interval or obtained by taking a long-term average of the mathematical function of the queue depths.

Abstract: A method and apparatus is described herein for executing firmware tasks during OS runtime. A thread slices execution time among entries in a control structure, such as process control block (PCB), maintained by an OS kernel. An entry in the control structure includes a reference to a firmware task, such as a system management operation, a BIOS task, and/or and EFI task. Based on that entry, the thread allocates an amount of execution time either directly to the firmware task or to a kernel mode driver to perform the firmware task.

Abstract: In process control based on partition setting which is a process corresponding to a plurality of operating systems (OSs), a configuration is implemented in which an interrupt request can be processed efficiently. In process control for switching processes which are based on the plurality of OSs, it is configured to set an interrupt processing partition as an interrupt processing execution period corresponding to an interrupt processing request so as to coincide with a pre-set partition switching timing. Further, a processing schedule is set, taking a maximum allowable delay time, a minimum allowable delay time into account. As a result of the present configuration, an increment in the number of partition switching processes can be kept to 1, and thus efficient data processing becomes possible.

Abstract: A host device may include a driver that is arranged and configured to communicate commands to a data storage device and multiple pairs of queues, where each of the pairs of queues may include a command queue that is populated with commands for retrieval by the data storage device and a response queue that is populated with responses by the data storage device for retrieval by the host device, where each response queue is associated with an interrupt and an interrupt handler.

Abstract: A method for making it possible for a virtualization software (VMM) to generally identify a PCI function of an interrupt requester presupposing the existing I/O devices based on the PCI express is provided. An interrupt relay circuit is provided between an I/O device based on the PCI express and a PCI express bridge. The interrupt relay circuit receives and relays an interrupt transaction issued by the I/O device, and records whether there is an interrupt request in an interrupt indicator in association with an interrupt identifier. A VMM 114 uniquely identifies an I/O device of interrupt requester by referring to the interrupt indicator 134.

Abstract: A system and method for writing, by a sender, a message into blocks of a memory space, the memory space being shared by the sender of the message and a receiver of the message, and sending, by the sender, an interrupt corresponding to the message.

Abstract: A distributed control system and methods of operating such a control system are disclosed. In one embodiment, the distributed control system is operated in a manner in which interrupts are at least temporarily inhibited from being processed to avoid excessive delays in the processing of non-interrupt tasks. In another embodiment, the distributed control system is operated in a manner in which tasks are queued based upon relative timing constraints that they have been assigned. In a further embodiment, application programs that are executed on the distributed control system are operated in accordance with high-level and/or low-level requirements allocated to resources of the distributed control system.