Abstract: An address crossbar switch temporarily buffers received requests while monitoring the requests, and counts requests of a predetermined type (for example, long-packet address requests). When a counter value exceeds a predetermined threshold value (for example, when a long-packet counter value exceeds 100), the address crossbar switch suspends broadcasting the address requests for a predetermined time period. After the predetermined time period has elapsed, the address crossbar switch restarts broadcasting the address requests in the order in which they were received.

Abstract: A computer device, an input/output (“I/O”) communication subsystem, a chipset and a method are disclosed for implementing interrupt message packets to facilitate peer-to-peer communications between a device controller and a coprocessor. Advantageously, the various embodiments of the invention obviate a requirement for specialized circuitry on a motherboard to establish peer-to-peer communications. In one embodiment, an I/O communication subsystem includes a bus interface for coupling the I/O communication subsystem to a general-purpose bus. It also includes a device controller being configured to generate an interrupt as an interrupt message packet for a coprocessor, which, in turn, interrupts processing functions that otherwise are performed by the host processor. The device controller can reside either internal or external to the I/O communication subsystem.

Abstract: An information processing system is provided which includes a plurality of system resources, and an event queue having a maximum number of entries. An event recording mechanism of the information processing system is operable to make entries regarding events in the event queue, wherein the entries are limited to a predetermined number of active entries in the event queue per each type of event per each of the system resources. In a particular embodiment, the number of entries per each type of event for each of the system resources is limited to one.

Abstract: An auxiliary interrupt control circuit is for use in a computer system including at least one peripheral for generating interrupt requests, an interrupt pending register for storing the interrupt requests, a microprocessor for processing interrupts, and an interrupt control circuit associated with the microprocessor. The auxiliary control circuit may include an auxiliary register coupled to the priority interrupt register for storing a copy of the interrupt requests. It may further include an encoder coupled to the auxiliary register and the microprocessor for generating a bit string identifying an active bit stored in the auxiliary register corresponding to a highest priority interrupt request to be processed, and for providing the bit string to the microprocessor.

Abstract: Provided are techniques for interrupt processing. An Input/Output device determines that an event has occurred. The Input/Output device determines a state of an event data structure. The Input/Output device writes an event entry into the event data structure in response to determining that the event has occurred. After writing the event entry, the Input/Output device determines whether to generate an interrupt or not based on the state of the event data structure. Additionally provided are techniques for interrupt processing in which an I/O device driver determines that an interrupt has occurred. The I/O device driver reads an event entry in an event data structure in response to determining that the interrupt has occurred. The I/O device driver updates a state of a structure state indicator to enable/disable interrupts.

Abstract: An information processing system is provided which includes an interrupt table including a plurality of entries relating to interrupts requested by entries in a plurality of event queues. The entries of the interrupt table reference identifiers, and the identifiers are assigned to events from a pool of identifiers in accordance with an order in which the events occur.

Abstract: In a computer system or information handling system, a virtual system event provides for the communication of the notification of a system events from the hardware of the computer system to the power and configuration management system of the computer system.

Abstract: An idle mode system has a clock gating circuit, a bus interface unit, memory interfaces and an interrupt and idle control unit. The clock gating circuit receives a first clock and designated idle-acknowledge signals. The clock gating circuit produces a second clock signal based on the first clock signal when fewer than all designated idle-acknowledge signals are received. The clock gating circuit produces no second clock signal when all designated idle-acknowledge signals are received. The bus interface unit receives bus access requests and receives the first and second clock signals. When a bus access request is made, the bus interface unit de-asserts its idle-acknowledge signal and passes the bus access request. The memory interfaces operate on the second clock. One interface receives the bus access request from the bus interface unit, withdraws its idle-acknowledge signal, processes the bus access request, and re-asserts its idle-acknowledge signal upon completion.

Abstract: A method, apparatus, and computer instructions for providing pre and post handlers to log trace records before entering or after exiting the interrupt handler. A trace record includes a ‘from’ address where the interrupt occurs or where the branch instruction is executed or a ‘to’ address for the branch to case and counts of selected performance monitoring events. A timestamp may be associated with each event. In one embodiment, the pre and post handler is used with trap on branch to log trace records prior to and immediate after taking a branch. In another embodiment, a pre handler is enabled to log trace records that occur prior to executing interrupt service routines. A post handler is enabled to log trace records that occur after the interrupt service routines is executed and prior to returning to normal execution. Resulting low-level performance trace data may be collected by the user at a later time for more structured performance analysis.

Abstract: An interrupt handling technique is provided that may allow for sharing level sensitive interrupts in systems where interrupts are message based, i.e., edge triggered. An interrupt input unit is provided for receiving level sensitive interrupt requests and generating request occurrence signals therefrom. An edge detection unit generates start signals for edge triggered interrupt messages on the basis of the request occurrence signals. An interrupt termination detection unit receives termination signals each indicating that an interrupt routine relating to a previous edge triggered interrupt message has terminated. The interrupt input unit is controlled to output a request occurrence signal in response to a received termination signal if a previously received level sensitive interrupt request is still active. That is, a second edge triggered interrupt message may be generated.

Abstract: A queue monitoring system and method determines when one or more transmit queues have reached a state that requires action by the host processing device, without the need for periodic polling of transmit status or excessive interrupt servicing. The queue monitoring implements an interrupt mechanism that generates an interrupt if one or more of the transmit queues has gone from a non-empty state to an empty state, and remained in the empty state for a (programmable) period of time. The combination of queue status checking (when adding new transmit data) with the queue monitoring interrupt mechanism removes the need for periodic polling of queue status and handling of interrupts generation on the completed transmission of data from one or more transmit buffer.

Abstract: A video apparatus has a digital decoder having a first memory on an internal bus and linked to an OSD circuit and to a second memory via a main bus. The video apparatus comprises means for realizing a DMA transfer between the first memory and the second memory. A process for controlling such a video apparatus is also described.

Abstract: A computer-implemented method for handling pending interrupt vectors of a pending interrupt list is disclosed. The method includes batch-reading the set of pending interrupt vectors into a working list of working interrupt vectors. The method also includes performing interrupt handling of the working interrupt vectors using an interrupt handling arrangement until the working list is empty. The interrupt handling process permits a first incoming interrupt vector that is received by the pending interrupt list after the batch reading to temporarily interrupt the performing interrupt handling of the working interrupt vectors and to be handled on a priority basis by the interrupt handling arrangement if a priority level of the first incoming interrupt vector is higher than a priority level of a first working interrupt vector being currently handled by the interrupt handling arrangement.

Abstract: A system including an event monitor monitoring at least one transmission link. Each event monitor receives transmission link addresses from an address sequencer and transmits related event data to a centralized storage register. The address sequencer also transmits the addresses to the storage register. The event monitor compares new event data for each address with old event data stored by the event monitor. If a difference is detected, the event monitor sends a strobe signal to the storage register, which stores the event data reflecting the difference and the related address data. The strobe signal is also sent to a signaling device, which sends an interrupt signal to cause a microprocessor to read the event and address data from the storage register. Optionally, the signaling device does not send an interrupt signal until a threshold number of strobe signals have been received.

Abstract: A processor includes a set of general purpose registers that are used when executing generic tasks and a set of exception registers that is dedicated for servicing specific exceptions. When a task is interrupted with an asserted “fast” exception, the processor automatically diverts the exception to the dedicated exception registers using a dedicated vector. The dedicated vector and exception registers may be reserved for high priority, i.e., critical, exceptions. Because the exception registers are automatically activated for fast exceptions, there is no need to determine the priority of the exception. Further, high priority interrupts and high priority operating system calls (traps) may have different dedicated vectors and the set of exception registers may have a portion allocated for servicing interrupts and another portion allocated for servicing operating system calls. With the use of a dedicated vector or dedicated vectors, there is no need for software to decode the fast exception.

Abstract: An API including an interrupt handler registration function and one or more interrupt dispatchers, is provided to an optical networking apparatus to facilitate registration of interrupt handlers to handle interrupts triggered by the function blocks of multi-protocol optical networking modules (MPONM). Each registered interrupt handler may handle interrupts triggered by one or more function blocks of any of the MPONM, and/or for one or more cause. In one embodiment, the one or more interrupt dispatchers are equipped to determine the triggering function block and the cause, and determine the interrupt handlers, if any, are to be notified. Each of the interrupt handlers to be notified is notified accordingly, including the triggering function block and the cause.

Abstract: The present inventions provide a controlling device for reducing external interrupts for a processor and the method thereof in a real time system. The controlling device decides whether it should trigger a real interrupt to the processor or combining as many interrupts as possible in one interrupt. The controlling device comprises a buffer, an interrupt controller, and an interrupt recording table. The interrupt controller receives interrupts, then saving information of interrupts to the buffer and reading out limitations of the interrupts, the limitations including interrupt deadlines and processing time of each interrupt. The interrupt recording table stores the limitations of each interrupt. The interrupt controller comprises a timer for counting timing references of the interrupt signals. After receiving an interrupt, the interrupt controller compares the limitations and selectively sends an interrupt signal, a real hardware interrupt, to the processor.

Abstract: A method for generating interrupt commands for a microprocessor system includes storing interrupts in a pending interrupts register, and storing priority values associated with the stored interrupts in a plurality of priority registers coupled to the pending interrupts register. A plurality of counters coupled in cascade to the plurality of priority registers are loaded with the stored priority values. The loaded priority values are incremented at predetermined intervals, and are compared for identifying the interrupt having a highest priority. The method further includes identifying a respective interrupt service routine to be executed based upon the interrupt having the highest priority.

Abstract: A method and system for completing pending I/O device reads by periodically stalling the issuance of I/O device accesses by a program in a multiple-processor computer system.

Abstract: A method and system for forwarding interrupt requests from a source device to a destination device. A controller bridge receives data, from a source device, for a destination device and stores the incoming data in a data queue. An interrupt request is received from the source device for the destination device and forwarded to the destination device in response to completing a transfer of the data from the source device to the destination device. If data received from the source device for the destination device are pending in the data queue, the interrupt request is rejected and the source may resubmit the interrupt request at a later time. If additional data are received from the source device for the destination device, the data may be rejected in response to an interrupt pending in the interrupt queue from the source device for the destination device.

Abstract: A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

Abstract: Method and apparatus for supporting interrupt devices configured for a specific architecture (e.g., APIC-based software and hardware) on a different platform (e.g., a PowerPC platform).

Abstract: A host channel adapter configured for outputting packets, according to a service protocol requiring acknowledgement messages within a prescribed time interval following transmission, utilizes a retransmission table for storing entries identifying the packets awaiting respective acknowledgment messages during the respective prescribed time intervals. A retransmission manager is configured for updating the retransmission table after each access cycle, defined as a prescribed number of clock cycles. The retransmission manager also identifies a number of transmitted packets within the corresponding access cycle within a selected initial entry for the access cycle. An acknowledgment manager in the receive portion of the host channel adapter resets to zero an acknowledgment waiting bit in a selected entry in response to an acknowledgment message identifying the corresponding packet.

Abstract: A data processing system nested interrupt controller 24 responsive to priority level values 28, 30 associated with respective interrupt handling programs to control the execution of those interrupt handling programs. The priority level values have a first portion 28 which controls whether or not a pending interrupt handling program will pre-empt an already active interrupt handling program and a second portion 30 which controls which of a plurality of pending interrupt handling programs will be executed next when they share the same value for the first portion of their priority level value.

Abstract: The present invention relates to a bus system comprising a first and second station (10, 14) coupled via a bus (12) for transferring data and control signals, the bus (12) operating according to a protocol in which the first station (10) repeatedly sends requests (200, 210, 220, 230) for data to the second station, the second station (14) responding to each request (200, 210, 220, 230) by sending a message with a data item or sending a negative acknowledge signal (24), wherein the second station (14) comprises: an interruptable processor (15) for generating data items; a first in first out buffer (160) coupled between the processor (15) and the bus (12), for buffering data items for successive messages in a first in first out order, the processor (15) being programmed to start writing the data items to the buffer (160) in response to an interrupt (204, 234); a bus interface (162) arranged to handle the protocol, sending data items from the buffer (160) in the messages, the bus interface (162) sending an in

Abstract: Systems, methods, and software for reducing system management interrupt (SMI) latency while operating in system management mode. The present invention implements a technique for exiting system management mode while waiting for polled hardware events, handling any pending lower-priority interrupts and then resuming polling. The present invention does this by multi-threading SMI source handlers, using an idle thread, and using protocols for software-generated system management interrupts that insure that lower priority interrupts are serviced.

Abstract: An apparatus is described which is distinguished by the fact that the apparatus does not output an interrupt request until after a plurality of interrupt requests have been received. The apparatus outputs a plurality of interrupt requests in response to an interrupt request being received, and/or the apparatus waits to output an interrupt request until it can be assumed that the operation to be initiated by a previously output interrupt request has been executed. As a result, it can be used extremely flexibly.

Abstract: A method and apparatus for generating, initializing, and scheduling of two interrupt queue heads to represent a single endpoint are described. In an embodiment, a method includes generating primary and secondary interrupt queue heads to represent a single interrupt endpoint. The method further includes initializing the primary and secondary interrupt queue heads. The method also includes scheduling the primary and secondary queue heads in immediately subsequent frames.

Abstract: Coded requests are received from Memory Port Interfaces (608 and 612) and stored into Outgoing Queue (604). Coded requests are also received from Transaction Pipeline (610), some of which may be linked requests. In response to each linked request stored in Outgoing Queue (604), multiple bus requests are generated by Outgoing Queue (604) and assembled by Assembler (602) and placed onto Bus Interface (620).

Abstract: In a transfer controller with hub and ports architecture one of the data ports is an active data port. This active data port can supply its own source information, destination information and data quantity in a data transfer request. This data transfer request is serviced in a manner similar to other data transfer requests. The active data port may specify itself as the data destination in an active read. Alternatively, the active data port may specify itself as the data source in an active data write.

Abstract: In one aspect, a method is disclosed. The method includes trapping initializing data of a first interrupt type to a first interrupt controller, re-routing the initializing data of the first interrupt type to a second interrupt controller, and configuring the second interrupt controller to manage interrupt of the first interrupt type.

Abstract: A queue-based spin lock with timeout allows a thread to obtain contention-free mutual exclusion in fair, FIFO order, or to abandon its attempt and time out. A thread may handshake with other threads to reclaim its queue node immediately (in the absence of preemption), or mark its queue node to allow reclamation by a successor thread.

Abstract: A system and method of enhanced backplane messaging among a plurality of computer boards communicating over a common bus uses a set of pre-allocated buffers on each computer board to receive messages from other computer boards. Each sending computer board is represented on each remote computer board by a descriptor ring with pointers to pre-allocated buffers on that remote computer board. When a sending computer board has a message to deliver to a remote computer board, the sending computer board uses its DMA controller to transfer the message into the pre-allocated buffers on the remote computer board. The sending computer board also sends a mailbox interrupt to the remote computer board. The remote computer board interrupt handler moves the messages from the descriptor rings to the receiving application(s) via pointer manipulation. Chained DMA transfers are used to eliminate any data transfers by the processor itself across the bus.

Abstract: One embodiment of the present invention provides a system that facilitates delaying interfering memory accesses from other threads during transactional execution. During transactional execution of a block of instructions, the system receives a request from another thread (or processor) to perform a memory access involving a cache line. If performing the memory access on the cache line will interfere with the transactional execution and if it is possible to delay the memory access, the system delays the memory access and stores copy-back information for the cache line to enable the cache line to be copied back to the requesting thread. At a later time, when the memory access will no longer interfere with the transactional execution, the system performs the memory access and copies the cache line back to the requesting thread.

Abstract: An anti-starvation interrupt protocol for use in avoiding livelock in a multiprocessor computer system is provided. At least one processor is configured to include first and second control status registers (CSRs). The first CSR buffers information, such as interrupts, received by the processor, while the second CSR keeps track of the priority level of the interrupts. When an interrupt controller receives an interrupt, it issues a write transaction to the first CSR at the processor. If the first CSR has room to accept the write transaction, the processor returns an acknowledgement, whereas if the first CSR is already full, the processor returns a no acknowledgment. In response to a no acknowledgment, the interrupt controller increments an interrupt starvation counter, and checks to see whether the counter exceeds a threshold. If not, the interrupt controller waits a preset time and reposts the write transaction.

Abstract: An output cycle of a pulse string generated from a pulse generating section (2) is divided by a pulse dividing section (3) and a signal having a cycle which is plural times as great as the cycle of an output pulse is output from the pulse dividing section (3). This signal is input as an interruption request signal to a CPU (1). Consequently, the CPU (1) can execute an interruption processing in a cycle which is plural times as great as the cycle of the output pulse. By the interruption processing, the number of pulses to be output is controlled.

Abstract: The present invention relates generally to interrupt processing. One embodiment relates to a method for executing an interrupt in a data processing system including fetching a conditional store instruction that is conditional upon a reservation, receiving notice that an interrupt is pending, invalidating a reservation in response to receiving the notice, and processing the interrupt. Invalidating the reservation allows the conditional store instruction to finish in a predetermined amount of time and properly update an architectural state of the processor. Therefore, interrupt latencies (the amount of time between receiving and processing an interrupt) corresponding to the conditional store instruction can be bounded. The method may be used in a single processor or multi-processor data processing system, wherein each processor includes a reservation register.

Abstract: A method and system for a processor to efficiently accesses a remote First-in First-out (FIFO) buffer that is used to record event information. The access involves an interrupt mechanism when the FIFO transitions from the empty state, a mechanism for reading a FIFO entry including FIFO state information, and a mechanism for reading large areas of the FIFO while maintaining the pointers and interrupt protocols.

Abstract: A data transfer control circuit includes several data receiver-transmitters, each having an interrupt identification register. Interrupt signals from the data receiver-transmitters are combined into a single interrupt signal by an interrupt controller. One of the data receiver-transmitters has an interrupt status register with bits indicating the logic levels of the interrupt signals from each of the data receiver-transmitters. A host device that receives the interrupt signal from the interrupt controller can read the interrupt status register to determine which data receiver-transmitter caused the interrupt, then read the interrupt identification register of that data receiver-transmitter to identify the interrupt source, without having to search through the interrupt identification registers of other data receiver-transmitters.

Abstract: An information handling system is provided which includes a dynamic interrupt router for balancing interrupt assignments among a plurality of devices requesting interrupt assignments. The system balances interrupt assignments among both fixed devices mounted on the processor board and interrupt assignments to devices situated in expansion slots. When the system is populated with a large number of devices relative to the number of available interrupts, improved interrupt sharing is desirably achieved by causing a device which generates a large number of interrupt requests to share a common interrupt with a device which generates a lower number of interrupts.

Abstract: Starting and establishing a dialog between an interruption handler and an operating system for handling of hardware interruptions by the operating system is disclosed. A recommendation for handling such an interruption, and information regarding the interruption, are stored by the interruption handler in a storage accessible by the operating system. The interruption handler calls the operating system at a predetermined interruption handling point thereof, for the operating system to handle the interruption. The handler then determines whether the operating system handled the interruption according to the recommendation.

Abstract: A flexible interrupt controller (28) that includes an interrupt force register (120) is presented. Hardware interrupts (102) that are presently asserted by their respective hardware sources are stored in an interrupt source register (110) included in the interrupt controller (28). An independent interrupt force register (120) stores currently pending software interrupts (104) which may be asserted through the execution of software routines by the central processing unit (CPU) (12) within the data processing system (10). In one embodiment, each bit location in the interrupt source register (110) has a corresponding bit location in the interrupt force register (120), and each bit in the interrupt force register (120) is logically OR-ed with the corresponding bit in the interrupt source register (110).

Abstract: Methods and apparatus for enabling timeouts with arbitrary resolutions to be implemented are disclosed. According to one aspect of the present invention, a method for enabling a device driver to communicate with a processor in a computing system includes exchanging information between the device driver and a clock system, and exchanging information between the clock system and a cyclic system. Information is also exchanged between the cyclic system and the processor. Although the clock system indirectly exchanges information with the processor, the clock system does not directly exchange information with the processor. In one embodiment, the clock system includes a callout system and a system clock, and exchanging information between the device driver and the clock system includes exchanging information between the system clock and the callout system, and exchanging information between the callout system and the device driver.

Abstract: A microprocessor system having an interrupt controller is provided for use in a mobile communications device. Peripheral processing units generate interrupt requests for sending to the microprocessor. The microprocessor has components for responding to interrupt requests by interrupting current processing and performing an interrupt service routine associated with the interrupt request. The interrupt controller receives interrupt requests directed to the microprocessor from the peripheral processing units and for prioritizes the interrupt requests on behalf of the microprocessor. By providing an interrupt controller for prioritizing interrupt requests on behalf of the microprocessor, the microprocessor therefore need not devote significant internal resources to prioritizing the interrupt request signals.

Abstract: Mechanisms and techniques operate in a computerized device to execute critical code without interference from interruptions. Critical code is registered for invocation of a critical execution manager in the event of an interruption to the critical code. The critical code is then executed until an interruption to the critical code occurs. After handling the interruption, a critical execution manager is invoked and the critical execution manager detects if an interference signal indicates a reset value. If the interference signal indicates the reset value, the critical execution manager performs a reset operation on the critical code to reset a current state of the critical code to allow execution of the critical code while avoiding interference from handling the interruption and returns to execution of the critical code using the current state of the critical code.

Abstract: A method for achieving low overhead for operating system (“OS”) interrupts is described. In a preferred embodiment, when an interrupt occurs, a lightweight interrupt handler is used to acknowledge that the interrupt occurred, prevent the CPU and the OS from fully servicing the interrupt until a designated future time, set a CPU flag indicating that the interrupt has been received, and return from the lightweight interrupt handler. In this manner, the interrupt is partially acknowledged by the CPU and the OS, but the driver that caused the interrupt is still awaiting service. To achieve low latency, a heavyweight (“non-deferrable”) time-based interrupt that flushes all deferred interrupts is scheduled to occur within a specified time. At a later time, when drivers would normally be polled for work, the CPU flag is checked to see if there is interrupt work.

Abstract: This invention has as its object to achieve high-speed data transfer using an asynchronous transfer interface. An encoding program encodes source data not to include byte data of a predetermined value. An arithmetic operation program EX-ORs the predetermined value, encoded data of interest, and immediately preceding output data so that neighboring data do not have identical values in units of bytes, and outputs the result as output data. A communication program sends the output data to a printer (7). In the printer (7), a clock is generated based on a change in received data, and received data is latched and decoded in synchronism with the clock.

Abstract: A system and method for logging events processed by an operating system is provided. The events logged can include interrupt and non-interrupt events, and can include user-defined events. Information concerning the interrupt events is initially written, during event handling time, into a first buffer while information concerning non-interrupt events is initially written, during event handling time, into a second buffer. Information from the two buffers is then written to a third buffer not during event handling time. Separating the interrupt event buffer from the non-interrupt event buffer rather than having one buffer, and writing relatively small amounts of data during event handling time to memory, rather than transporting data to slower non-memory mapped devices allows the event logger to be less intrusive and facilitates greater accuracy in event logging.

Abstract: A peripheral device is connected to an information processing device, and in the event that an interruption job is input from the information processing device while the peripheral device is processing a job by executing one of multiple device control programs holding the functions of multiple devices engines of the peripheral device and managing jobs with the device engines, another device control program different from the device control program being executed is selected and the interruption job is executed. Accordingly, a user-friendly multifunctional peripheral device can be provided.

Abstract: An apparatus and method for reducing operating system interrupts by queuing incoming network traffic units received by a network interface, where said units are received without interrupting a host environment on receiving queued units. However, if a predetermined number of received units have a same origin, then the host environment is interrupted as subsequent network traffic units are received by the network interface, until a predetermined number of network traffic units are subsequently received from a different origin. Notwithstanding queuing incoming network traffic units, the host environment is interrupted on expiration of a timeout period, or if a predetermined number of units have been queued.