Abstract: Embodiments of an interrupt mailbox in host memory are described herein. In an implementation, a device connected to a host writes interrupt data corresponding to an interrupt generated by the device to host memory. Then, the host, when processing the interrupt, accesses the interrupt data from the host memory.

Abstract: System and methods for preventing an operating-system scheduler in a computer system from crashing as a result of an uncleared periodic interrupt are disclosed. A periodic interrupt is generated using a real-time clock (RTC) residing on a chipset. A flag indicating a periodic interrupt is entered into a status register associated with the RTC in firmware residing on the CMOS chip, if the status register indicates no periodic interrupt has been pending. An interrupt handler associated with the RTC attempts to handle the periodic interrupt, if pending. If the periodic interrupt is pending after a preset interval of time elapses, a basic-input-output system (BIOS) residing on a memory unit coupled to the chipset generates a system-management interrupt (SMI). If the periodic interrupt is pending after the preset interval of time elapses, a firmware SMI handler residing on the memory unit clears the pending periodic interrupts from the status register.

Abstract: An interrupt control circuit includes: a section that generates an interrupt signal for requesting an interrupt in response to occurrence of a plurality of interrupt causes; a section that generates an interrupt vector signal for indicating a storing destination of an interrupt processing program corresponding any of the plurality of interrupt causes; a section that outputs the interrupt signal and the interrupt vector signal to an interrupt process executing circuit; and a section that controls the interrupt signal and an output value of the interrupt vector signal in sync with an interrupt acceptance signal input from the interrupt process executing circuit, the interrupt acceptance signal representing a condition in which an interrupt process is acceptable.

Abstract: A method includes determining a plurality of memory addresses, each memory address being different from one another. The method further includes generating a plurality of system management interrupt interprocessor interrupts, each system management interrupt interprocessor interrupt having a corresponding processor in a plurality of processors in a system and each system management interrupt interprocessor interrupt including one of the plurality of memory addresses. The method further includes directing each system management interrupt interprocessor interrupt to the corresponding processor. An associated machine readable medium is also disclosed.

Abstract: Disclosed is a communication mechanism among hardware, firmware and system software in order to redirect interrupts or other hardware events to only one thread execution context of an error domain for a multi-threaded processing system. Other embodiments are also described and claimed.

Abstract: A first processor in a multiprocessor system for processing interrupts by a plurality of processors accepts an interrupt and executes first interrupt processing in accordance with the accepted interrupt. In the first interrupt processing, second interrupt processing corresponding to the accepted interrupt is assigned to a second processor.

Abstract: A system and method is disclosed for managing system management interrupts in a multiprocessor system. The system described herein includes multiple processors, each of which may be directly coupled to memory. A primary processor will recognize the initiation of a system management interrupt. The primary processor will write a reason code to a storage location and set a watchdog timer, the expiration of which causes all of the processors of the system to enter a system management mode. After all of the processors have entered system management mode, it is determined if the reason code of the storage location corresponds to certain software-based system management interrupts. If so, the system management interrupt is handled by the local processors. Following the handling of the system management interrupt by the local processor, a signal is sent to each of the other processors to cause the processors to exit system management mode.

Abstract: A method, information processing system, and computer readable medium, mitigate processor assignments. A first processor in a plurality of processors is assigned to a first communication port in a plurality of communication ports. An interrupt associated with the first communication port is generated. An assignment of a processor other than the first processor to handle the interrupt is inhibited.

Abstract: Interrupts are directed to currently idle processors. Which of a number of processors of a computing system that are currently idle is determined. An interrupt is received and directed to one of the currently idle processors for processing. Determining which processors are currently idle can be accomplished by monitoring each processor to determine whether it has entered an idle state. When a processor has entered an idle state, it is thus determined that the processor is currently idle. Where just one processor is currently idle, an interrupt is directed to this processor. Where more than one processor is currently idle, one of these processors is selected to which to deliver an interrupt, such as in a round-robin manner. Where no processor is currently idle, then one of the processors is selected to which to deliver an interrupt.

Abstract: Handling interrupts within an information handling system including entering into an interrupt management mode in response to receiving an interrupt, identifying at least one source of the received interrupt in accordance with an ordered list of a plurality of possible interrupt sources, dispatching an appropriate interrupt handler to resolve the identified at least one source of the received interrupt, noting a frequency of occurrence of each indentified at least one source generating a received interrupt over time, and recording the ordered list of possible interrupt sources in response to the noted frequency, wherein the possible interrupt sources with higher frequencies are placed in the beginning of the ordered list.

Abstract: A method and apparatus for enabling usage of an accelerator device in a processor socket is herein described. A set of inter-processor messages is utilized to initialize a configuration/memory space of the accelerator device. As an example, a first set of inter-processor interrupts (IPIs) is sent to indicate a base address of a memory space and a second set of IPIs is sent to indicate a size of the memory space. Furthermore, similar methods and apparatus' are herein described for dynamic reconfiguration of an accelerator device in a processor socket.

Abstract: Hot plug modules comprising processors, memory, and/or I/O hubs may be added to and removed from a running computing device without rebooting the running computing device. The hot plug modules and computing device comprise hot plug interfaces that support hot plug addition and hot plug removal of the hot plug modules.

Abstract: A single USB interrupt endpoint is usable by two different active logical devices in a USB device. If a first logical device is to interrupt a USB host, then the first logical device writes a notification into the endpoint. The notification carries a number that identifies a first device object. If, however, a second logical device is to interrupt the host, then the second logical device writes a notification into the endpoint, but the notification carries a number that identifies a second device object. The USB host reads the notification. In one example, if the number and a Device ID indicate that the notification is for the first object, then the first object processes the notification. If the number and Device ID indicate that the notification is for the second object, then the first object notifies the second object so that the second object processes the notification.

Abstract: In some embodiments, an apparatus includes logical interrupt identification number creation logic to receive physical processor identification numbers and create logical processor identification numbers through using the physical processor identification numbers. Each of the logical processor identification numbers corresponds to one of the physical processor identification numbers, and the logical processor identification numbers each include a processor cluster identification number and an intra-cluster identification number. The processor cluster identification numbers are each formed to include a group of bits from the corresponding physical processor identification number shifted in position, and the intra-cluster identification numbers are each formed in response to values of others of the bits of the corresponding physical processor identification number. Other embodiments are described.

Abstract: A peripheral circuit control register has a plurality of bits corresponding respectively to peripheral resources. A decoder activates an access signal to the peripheral resource at an access destination when the bit corresponding to the peripheral resource at the access destination in the peripheral circuit control register is under a set state in response to occurrence of access to any of the peripheral resources by a CPU. A functional specification of an evaluation chip can be made equivalent to those of product chips and development of a wrong user program can be prevented by setting in advance the bits of the peripheral circuit control register corresponding to the peripheral resources mounted to the product chip to the set state.

Abstract: A system and method of obtaining error data within an information handling system is disclosed. According to one aspect, an interrupt handling system can include a first system management interrupt handler operable to initiate access to a first interrupt event message. The interrupt handling system can also include a first resource operable to generate the first interrupt event message. In one form, the first interrupt event message can identify a first interrupt event occurrence detectable by the first system management interrupt handler. The interrupt handling system can further include a memory including a first allocated memory location configured to store the first interrupt event message using the first system management interrupt handler. In one form, the first system management interrupt handler can be responsive to a second system management interrupt handler request to read the first interrupt event message.

Abstract: A method and apparatus for distributing multiple interrupts among multiple processors is disclosed. According to one embodiment, an interrupt daemon monitors the interrupt load among the processors that results from an initial mapping of the interrupts to the processors. The interrupt daemon determines whether there is a sufficient imbalance of the interrupts among the processors. If so, the interrupt daemon triggers a reassignment routine that generates a new mapping of the interrupts among the processors, and if not, the interrupt daemon goes to sleep for a specified time period. If the new mapping produces a sufficient improvement in the distribution of interrupts among the processors, based on the same criteria used to detect the imbalance, the new mapping is used by the central hub for subsequent distribution of interrupts to the processors. However, if the new mapping does not provide a sufficient improvement, the original mapping continues to be used.

Abstract: Methods for processing more securely. Embodiments provide effective and efficient mechanisms for reducing APIC interference with accesses to SMRAM, where enhanced SMM code implementing these mechanisms effectively reduces APIC attacks and increases the security of proprietary, confidential or otherwise secure data stored in SMRAM.

Abstract: An information handling system recovers from memory errors associated with a memory unit that supports operation of an SMI handler by using another memory unit to support operation of the SMI handler. For example, if an SMI handler detects an error associated with a DIMM that supports operation of the SMI handler, then an SMI handler location module moves the SMI handler to another DIMM. For instance, a jump command is activated to jump to a pre-existing copy of the SMI handler stored at another DIMM. As another example, a relocation of the SMI handler to another DIMM is performed by changing address information used by the chipset and CPUs to run the SMI handler.

Abstract: Handling interrupts within an information handling system includes entering into an interrupt management mode in response to receiving an interrupt, identifying at least one source of the received interrupt in accordance with an ordered list of a plurality of possible interrupt sources, dispatching an appropriate interrupt handler to resolve the identified at least one source of the received interrupt, noting a frequency of occurrence of each identified at least one source generating a received interrupt over time, and reordering the ordered list of possible interrupt sources in response to the noted frequency, wherein the possible interrupt sources with higher frequencies are placed in the beginning of the ordered list.

Abstract: A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with an interrupt mapper for informing a plurality of processors about system-related functions for a plurality of channels. Using status registers containing interrupt status information for the plurality of channels, interrupt sources are specifically assigned to individual processors in the multiprocessor device so that the assigned processor can efficiently determine the source and priority of an interrupt by reading the register information.

Abstract: A method and system for handling a management interrupt, such as a system management interrupt (SMI) and/or a platform management interrupt (PMI), includes sequestering one or more processor cores for handling the management interrupt. Generated management interrupts are directed to the sequestered processor core and not to other processor cores allocated to a main partition. The sequestered processor core(s) handles the management interrupt without disrupting the current operation of the remaining processor cores.

Abstract: A method for directly sharing a network stack offload I/O adapter that directly supports resource virtualization and does not require a LPAR manager or other intermediary to be invoked on every I/O transaction is provided. The present invention also provides a method, computer program product, and distributed data processing system for directly creating and initializing one or more virtual resources that reside within a physical adapter, such as a PCI, PCI-X, or PCI-E adapter, and that are associated with a virtual host. Specifically, the present invention is directed to a mechanism for sharing conventional PCI (Peripheral Component Interconnect) I/O adapters, PCI-X I/O adapters, PCI-Express I/O adapters, and, in general, any I/O adapter that uses a memory mapped I/O interface for host to adapter communications.

Abstract: A fault-tolerant mass storage system includes two RAID controllers that communicate via a PCI-Express link. Each controller has a bus bridge coupled to the link, a cache memory that caches user data for storage on disk drives controlled by the controllers, and a CPU. The CPU fetches and executes program instructions from a CPU memory coupled to it. The CPU programs the bus bridge with window information defining a window of locations within the CPU memory, which is less than an entirety of the CPU memory. The bus bridge receives data on the link from the other controller and if the header of a packet containing the data indicates it is destined for the CPU memory, the bus bridge translates the address of the data so as to write the data safely to the CPU memory, but only within the window and nowhere else within the CPU memory.

Abstract: A device driver includes a kernel stub and a user-mode module. The device driver may access device registers while operating in user-mode to promote system stability while providing a low-latency software response from the system upon interrupts. Upon receipt of an interrupt, the kernel stub may run an interrupt service routine and write information to shared memory. Control is passed to the user-mode module by a reflector. The user-mode module may then read the information from the shared memory to continue servicing the interrupt.

Abstract: According to one embodiment, a method is disclosed. The method includes selecting a first of a plurality of programmable interrupt enable registers, a controller determining for the first register whether there interrupts at a queue manager to be processed by a processor, the processor reading an interrupt status register within the queue manager, the processor processing packets corresponding to addresses stored in each of a plurality of queues within the queue manager, selecting a second of a plurality of programmable interrupt enable registers and the controller determining for the second register whether there interrupts at the queue manager to be processed by the processor.

Abstract: Assigning interrupts for I/O devices among the nodes of NUMA systems is disclosed. At least one of the following is performed. First, interrupts for the devices are assigned among the nodes based on at least one of: the nodes to which the devices are connected, the nodes at which interrupt service routines for the devices reside, and the processors of the nodes. Second, for each node, the interrupts for the devices that are performance critical and that have been assigned to the node are assigned to the processors of the node in a round-robin manner. Third, assignments of the interrupts among the nodes of the system are dynamically modified based on actual performance characteristics of the assignments. Fourth, for each node, assignments of the interrupts that are performance critical and that have been assigned to the node are dynamically modified based on actual performance characteristics of the assignments.

Abstract: An interrupt control system is provided where a signal-line-based interrupt system can be incorporated into interrupt control using MSIs (Message Signal Interrupts). The interrupt control system includes a first PCI interface, a second PCI interface, a PCI bridge serving as a bridge between the first PCI interface and the second PCI interface, and a control circuit for controlling an interrupt signal. The PCI bridge recognizes a message signal interrupt issued from the first PCI interface to the second PCI interface and transfers the message signal interrupt to the control circuit, and the control circuit is provided with an interrupt conversion unit for converting the message signal interrupt into an interrupt signal and outputting it via a signal line.

Abstract: A system and a method for asynchronously signaling interrupts from a plurality of devices in a computing system, while optimizing the latencies in handling the interrupts. In a particular embodiment, an interrupt is signaled via a plurality of daisy chained devices by handing over the interrupt request from one device to another while retaining information regarding any interrupts handed over (also referred to as passed). In this way, the interrupt source can be readily identified (using a binary search, for example) thereby reducing interrupt latency and memory resources required to retain interrupt history.

Abstract: A method and system for handling interrupts within a computer system during hardware resource migration are disclosed. In at least some embodiments, the method includes (a) programming an address conversion component so that incoming interrupt signals are directed to a control component rather than to a source processing resource, and (b) accumulating the incoming interrupt signals at the control component. Additionally the method also includes, subsequent to the migration of the partition from the source processing resource to a destination processing resource, (c) sending the accumulated incoming interrupt signals to the destination processing resource, and (d) reprogramming the address conversion component so that further incoming interrupt signals are directed to the destination processing resource.

Abstract: A falling protective device for protecting a hard disk of a falling portable computer against damages includes a falling sensor arranged in the portable computer for generating and sending an interrupt signal to a keyboard controller in response to a detected falling state of the computer. An SMI signal line is extended between and connected to the keyboard controller and a system BIOS of the computer. On receipt of the interrupt signal generated by the falling sensor, the keyboard controller sends an SMI signal via the SMI signal line to the system BIOS, which in turn sends a park control signal to park the hard disk or a power-off control signal to terminate the supply of working power to the hard disk. The system BIOS sends a polling signal via a polling signal line to the keyboard controller, so as to poll about a state signal of a default status bit in a default signal port of the keyboard controller.

Abstract: A method for communicating with a processor event facility is provided. The method makes use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

Abstract: In accordance with embodiments, there are provided mechanisms and methods for suspending work by a resource adapter. These mechanisms and methods for suspending work by a resource adapter can enable embodiments to provide the capability to start and stop work performed by a resource adapter to connector architectures. The ability of embodiments to provide the capability to start and stop work performed by a resource adapter can enable users of Connector Architectures to quiesce an adapter's inbound/outbound or work sections. Such capability can enable an adapter embodiment to complete in-flight transactions but not accept new inbound transactions until a request to resume operation is received. Resource adapters may be quiesced during a versioning or change out process or other maintenance processes for example.

Abstract: A system and method of obtaining error data within an information handling system is disclosed. According to one aspect, an interrupt handling system can include a first system management interrupt handler operable to initiate access to a first interrupt event message. The interrupt handling system can also include a first resource operable to generate the first interrupt event message. In one form, the first interrupt event message can identify a first interrupt event occurrence detectable by the first system management interrupt handler. The interrupt handling system can further include a memory including a first allocated memory location configured to store the first interrupt event message using the first system management interrupt handler. In one form, the first system management interrupt handler can be responsive to a second system management interrupt handler request to read the first interrupt event message.

Abstract: Systems, methodologies, media, and other embodiments associated with a system configured with a trap mode register, multiple interrupt vector address registers, and multiple interrupt vector tables are described. One exemplary system embodiment includes a logic for initializing the trap mode register, for initializing interrupt vector address registers, and for initializing interrupt vector tables. When a trap occurs in a computer configured with the exemplary system, the trap mode register may select, based, for example, on the trap type or a trap data, an associated interrupt vector address register to provide an address of an interrupt vector table through which a trap handler can be invoked.

Abstract: An information processing apparatus includes: a CPU; a controller including a signal transmission unit configured to supply an SMI (system management interrupt) signal to the CPU; a multifunctional device having a plurality of functions each potentially causing an SMI; and a plurality of signal lines provided between the controller and the multifunctional device. Each of the signal lines corresponds to one of the plurality of functions and is configured to send a notification of occurrence of an SMI event from the multifunctional device to the controller.

Abstract: A method for processing an interrupt signal within a microprocessor based system is described. The method includes storing a received interrupt signal within an interrupt cause register of an interrupt controller, outputting an interrupt command from the interrupt controller to an interrupt collector, asserting an interrupt signal to the microprocessor from the interrupt collector, and shifting the cause value field into a cause array. The interrupt command include an identifier field, a cause register ID field, and a cause value field, and content of the cause value field is based on a content of the interrupt cause register. The interrupt signal is asserted based on receipt of the identifier field and cause register ID field by the interrupt collector, and the shifting of the cause value field into a cause array within the interrupt collector occurs while the microprocessor services the receipt of the identifier field and cause register ID field from the interrupt collector.

Abstract: Machine-readable media, methods, and apparatus are described to issue message signaled interrupts. In some disclosed embodiments, a device generates message signaled interrupts in a manner that enables a device driver written with level-sensitive semantics to properly service the device despite the edge-triggered characteristics message signaled interrupts.

Abstract: An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding registers. An interrupt vector register has bit positions corresponding to different classes of interrupts. A read queue has inputs coupled to the plurality of interrupt holding registers and to the interrupt vector register. Detection logic is coupled between an arbiter, fed by the write and read queues, and a processor for: (a) indicating when an interrupt has passed from the write arbiter to the processor; (b) detecting the interrupt class of such passed interrupt; (c) enabling the one of the bit positions corresponding to the detected interrupt class in the interrupt vector register to store a state indicating the servicing requirement for such detected class of interrupt; and (d) wherein the data stored in the interrupt vector register is passed to the processor through the read queue and the arbiter selector.

Abstract: Various operations are disclosed for improving the operational efficiency of address mapping caches, such as translation lookaside buffers, in a multiprocessor environment. When an address mapping translation is invalidated, unnecessary address mapping cache flushes are avoided by signaling only those processors operating in a virtual machine monitor mode to flush their address mapping caches. Address mapping cache flushes for processors operating in guest modes are postponed until the processor enters a virtual machine monitor mode. Optionally, a counter is maintained for each processor and incremented each time the processor enters virtual machine monitor mode. When an address mapping cache is invalidated, a snapshot of the counter values is stored. When an new address translation for an invalidated address translation is requested, the snapshot is compared with the current value of a counter to determine whether the address mapping cache associated with the counter has been flushed since the invalidation.

Abstract: A method according to one embodiment may include partitioning a multi-core processor into a first partition and a second partition, the first partition including a first processor core and a first interrupt controller configured to store a first partition identifier, the second partition including a second processor core and a second interrupt controller configured to store a second partition identifier. The method may also include receiving, by the first interrupt controller and the second interrupt controller, at least one interrupt that includes a partition identifier. The method may also include comparing, by the first interrupt controller, the partition identifier included with the interrupt to the first partition identifier stored in the first interrupt controller.

Abstract: In one embodiment, an input/output memory management unit (IOMMU) comprises a control register and control logic coupled to the control register. The control register is configured to store a base address of a device table, wherein a given input/output (I/O) device has an associated device identifier that selects a first entry in the device table. The first entry comprises a pointer to an interrupt remapping table. The control logic is configured to remap an interrupt specified by an interrupt request received by the IOMMU from the given I/O device if the interrupt remapping table includes an entry for the interrupt.

Abstract: Interrupt process generated in a processor for arithmetic operation is offloaded onto a system control processor, thereby reducing disturbance to the processor for arithmetic operation. A heterogeneous multiprocessor system includes: means which accepts an interrupt in each CPU; means which inquires the accepted interrupt of an interrupt destination management table to select an interrupt destination CPU; means which queues the accepted interrupt; means which generates an inter-CPU interrupt to the selected interrupt destination CPU; each means which receives the inter-CPU interrupt in the interrupt source CPU, performs interrupt process of the interrupt source CPU, and generates the inter-CPU interrupt to the interrupt source CPU in the interrupt destination CPU; means which performs an interrupt end process; and means which performs interrupt process in its own CPU when the interrupt destination CPU selected as a result of the inquiry to the interrupt destination management table is its own CPU.

Abstract: An interrupt control system is disclosed. The interrupt control system can include control logic that provides at least one interrupt request signal to a processor in response to at least one event signal. The control logic provides at least one computer executable instruction to a processor in response to detecting an instruction request from the processor corresponding to an interrupt response.

Abstract: The present invention relates to a system and methodology to facilitate negotiation, assignment, and management of interrupt resources in a flexible and dynamic manner. An interrupt arbitration system is provided to process at least one request associated with an interrupt resource, wherein the request includes at least two dimensions related to an interrupt and an interrupt service component. An arbiter processes the request and returns a subset of interrupt resource ranges in view of available system resources. This multi-dimensional mapping of resources enables coordination across resource pools, processors, buses, and/or other components while mitigating possible run-time problems attributed to one-dimensional systems that may find that suitable resources are unavailable.

Abstract: An API including an interrupt handler registration function and one or more interrupt dispatchers, is provided to an optical networking apparatus to facilitate registration of interrupt handlers to handle interrupts triggered by the function blocks of multi-protocol optical networking modules (MPONM). Each registered interrupt handler may handle interrupts triggered by one or more function blocks of any of the MPONM, and/or for one or more cause. In one embodiment, the one or more interrupt dispatchers are equipped to determine the triggering function block and the cause, and determine the interrupt handlers, if any, are to be notified. Each of the interrupt handlers to be notified is notified accordingly, including the triggering function block and the cause.

Abstract: An interrupt control system is provided where a signal-line-based interrupt system can be incorporated into interrupt control using MSIs (Message Signal Interrupts). The interrupt control system includes a first PCI interface 40, a second PCI interface 43, a PCI bridge 44 serving as a bridge between the first PCI interface and the second PCI interface, and a control circuit 54 for controlling an interrupt signal. The PCI bridge recognizes a message signal interrupt issued from the first PCI interface to the second PCI interface and transfers the message signal interrupt to the control circuit, and the control circuit is provided with an interrupt conversion unit for converting the message signal interrupt into an interrupt signal and outputting it via a signal line.

Abstract: A method for determining blocking signals is used to judge whether to block a return signal transmitted to a CPU or not when a system management interrupt (SMI) signal is transmitted to the CPU, wherein the return signal is a signal transmitted by a system chip in response to a triggering command transmitted to the system chip by the CPU. The blocking method includes detecting whether the CPU has transmitted the triggering command to the system chip, and detecting whether the system management interrupt signal is transmitted to the CPU. When the CPU has transmitted the triggering command to the system chip, and subsequently the system management interrupt signal has been transmitted to the CPU, it is judged that the system management interrupt signal is used to extract the values in registers of a computer system. Thereby the return signal transmitted to the CPU is blocked.

Abstract: A driver program for a multiprocessor subsystem includes an interrupt servicing routine (ISR) and a deferred procedure call (DPC). The ISR, invoked in response to an interrupt, determines whether any of the co-processors in the multiprocessor subsystem generated an interrupt. If one of the co-processors generated an interrupt, the ISR schedules the DPC for execution and disables sending of further interrupts from all of the co-processors. The DPC services pending interrupts from any of co-processors, then re-enables sending of interrupts from the co-processors.

Abstract: An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding registers. An interrupt vector register has bit positions corresponding to different classes of interrupts. A read queue has inputs coupled to the plurality of interrupt holding registers and to the interrupt vector register. Detection logic is coupled between an arbiter, fed by the write and read queues, and a processor for: (a) indicating when an interrupt has passed from the write arbiter to the processor; (b) detecting the interrupt class of such passed interrupt; (c) enabling the one of the bit positions corresponding to the detected interrupt class in the interrupt vector register to store a state indicating the servicing requirement for such detected class of interrupt; and (d) wherein the data stored in the interrupt vector register is passed to the processor through the read queue and the arbiter selector.