Abstract: An interrupt controller and interrupt controlling method are provided for prioritizing interrupt requests generated by a plurality of interrupt sources. The interrupt controller comprises an interrupt source interface operable to receive interrupt requests generated by a first plurality of interrupt sources, and a daisy chain interface operable to receive a daisy chain interrupt request output by a further interrupt controller based on a second plurality of interrupt requests generated by a second plurality of interrupt sources. The daisy chain interface includes a priority input operable to receive a daisy chain priority signal indicating a priority associated with the daisy chain interrupt request. Prioritization logic is operable to receive the daisy chain priority signal and to apply predetermined prioritisation criteria to determine the highest priority interrupt request selected from the daisy chain interrupt request and the interrupt request generated by the first plurality of interrupt sources.

Abstract: An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding registers. An interrupt vector register has bit positions corresponding to different classes of interrupts. A read queue has inputs coupled to the plurality of interrupt holding registers and to the interrupt vector register. Detection logic is coupled between an arbiter, fed by the write and read queues, and a processor for: (a) indicating when an interrupt has passed from the write arbiter to the processor; (b) detecting the interrupt class of such passed interrupt; (c) enabling the one of the bit positions corresponding to the detected interrupt class in the interrupt vector register to store a state indicating the servicing requirement for such detected class of interrupt; and (d) wherein the data stored in the interrupt vector register is passed to the processor through the read queue and the arbiter selector.

Abstract: Method, system, apparatus and computer program product for interrupt scheduling in processing communication. In one embodiment the method includes: a sending computer program and a receiving computer program, coupling at least one registered signal identifier and a corresponding registered signal function with said receiving computer program; sending a communication including a request signal identifier by said sending computer program to said receiving computer program; receiving said communication sent at (B) by said receiving computer program; and performing said corresponding registered signal function without context switching of said receiving computer program if said request signal identifier received is coupled with said registered signal identifier. A system, router, computer program and computer program product are also disclosed.

Abstract: A fault-tolerant RAID system is disclosed. The system includes redundant RAID controllers coupled by a PCI-Express link. When a PCI-Express controller of one of the RAID controllers receives a PCI-Express memory write request transaction layer packet (TLP), it interprets a predetermined bit in the header as an interrupt request flag, rather than as its standard function specified by the PCI-Express specification. If the flag is set, the PCI-Express controller interrupts the processor after storing the message in the payload at the specified memory location. In one embodiment, an unused upper address bit in the header is used as the interrupt request flag. Additionally, unused predetermined bits in the TLP header are used as a message tag to indicate one of a plurality of message buffers on the receiving RAID controller into which the message has been written. The PCI-Express controller sets a corresponding bit in a register to indicate which message buffer was written.

Abstract: A computer device, an input/output (“I/O”) communication subsystem, a chipset and a method are disclosed for implementing interrupt message packets to facilitate peer-to-peer communications between a device controller and a coprocessor. Advantageously, the various embodiments of the invention obviate a requirement for specialized circuitry on a motherboard to establish peer-to-peer communications. In one embodiment, an I/O communication subsystem includes a bus interface for coupling the I/O communication subsystem to a general-purpose bus. It also includes a device controller being configured to generate an interrupt as an interrupt message packet for a coprocessor, which, in turn, interrupts processing functions that otherwise are performed by the host processor. The device controller can reside either internal or external to the I/O communication subsystem.

Abstract: A simulation system that increases a polymer molecule binding prediction speed on a parallel and distributed computer system is provided.

Abstract: An information handling system is disclosed that retires events upon device replacement. The system has several devices of one or more types and each device includes nonvolatile memory. A unique identifier, for devices of that type, is stored in the nonvolatile memory of each device. A first memory segment stores an event log. The event log has entries that identify system events. A second memory segment stores identifiers of devices that correspond to an entry of the event log. At least one of the corresponding devices is removable. The system detects the removal of the devices and, in response, removes any entries in the event log that correspond only to identifiers of one or more devices that have been removed.

Abstract: Provided are techniques for interrupt processing. An Input/Output device determines that an event has occurred. The Input/Output device determines a state of an event data structure. The Input/Output device writes an event entry into the event data structure in response to determining that the event has occurred. After writing the event entry, the Input/Output device determines whether to generate an interrupt or not based on the state of the event data structure. Additionally provided are techniques for interrupt processing in which an I/O device driver determines that an interrupt has occurred. The I/O device driver reads an event entry in an event data structure in response to determining that the interrupt has occurred. The I/O device driver updates a state of a structure state indicator to enable/disable interrupts.

Abstract: A method is disclosed including the steps of submitting a print job to a network printer and identifying a specific printer controller governing the print job. The method further includes loading a set of identifiers respective to a specific printer controller and selecting from the set a respective identifier corresponding to the type of print job employed on the specific printer controller. The selected identifier is used to issue the predetermined type of notification from the controller.

Abstract: An interrupt processing technique is provided where an interrupt message is sent to an interrupt controller of a processor in response to an interrupt request from an individual device. The interrupt message comprises a memory address and interrupt status information. The memory address is specifically allocated to the device that has issued the interrupt request. The interrupt status information indicates an interrupt status of the device. An interrupt table that is stored in the memory is updated by the interrupt controller using the interrupt status information comprised in the interrupt message. The interrupt table holds device specific interrupt statuses. Updating the interrupt table comprises addressing the memory using the memory address in the interrupt message.

Abstract: In a computer system or information handling system, a virtual system event provides for the communication of the notification of a system events from the hardware of the computer system to the power and configuration management system of the computer system.

Abstract: In one embodiment, a method includes recognizing an interrupt pending during an operation of guest software, determining that the interrupt is to cause a transition of control to a virtual machine monitor (VMM), determining whether the interrupt is to be acknowledged prior to the transition of control to the VMM, and if the interrupt is to be acknowledged, acknowledging the interrupt and transitioning control to the VMM.

Abstract: Techniques and mechanisms provide management of interrupt requests in a system, such as a programmable chip system. The system may include multiple master components and slave components. Techniques and mechanisms are described for assigning interrupts to slave components on a per master component basis. When a slave component initiates an interrupt request, a master component associated with the request will handle the interrupt without disrupting operation of other master components in the system.

Abstract: An idle mode system has a clock gating circuit, a bus interface unit, memory interfaces and an interrupt and idle control unit. The clock gating circuit receives a first clock and designated idle-acknowledge signals. The clock gating circuit produces a second clock signal based on the first clock signal when fewer than all designated idle-acknowledge signals are received. The clock gating circuit produces no second clock signal when all designated idle-acknowledge signals are received. The bus interface unit receives bus access requests and receives the first and second clock signals. When a bus access request is made, the bus interface unit de-asserts its idle-acknowledge signal and passes the bus access request. The memory interfaces operate on the second clock. One interface receives the bus access request from the bus interface unit, withdraws its idle-acknowledge signal, processes the bus access request, and re-asserts its idle-acknowledge signal upon completion.

Abstract: An interrupt control apparatus comprising an interrupt vector register for holding address information corresponding to interrupt resources of a first type which are managed by an operating system and interrupt resources of a second type which are not managed by the operating system. Regarding an interrupt generated by an interrupt resource of the first type, the interrupt control apparatus in the present invention launches a common interrupt entry function which is subject to a scheduling process common to the interrupt resources of the first type, based on the address information of the interrupt vector register. At the same time, with regard to an interrupt generated by an interrupt resource of the second type, the interrupt control apparatus in the present invention launches an extended interrupt entry function which is not subject to the aforementioned scheduling process, based on the address information held in the interrupt vector register.

Abstract: Provided are techniques for interrupt processing. An Input/Output device determines that an event has occurred. The Input/Output device determines a processor identifier and determines an event data structure identifier for an event data structure into which data for the event is stored using the processor identifier. The Input/Output device also determines a vector identifier for an interrupt message vector into which an interrupt message for the event is written. Then, interrupt message data is written to the interrupt message vector to generate an interrupt.

Abstract: A control packet management device of a packet forwarding system has a packet queue having a plurality of queues to store a control packet as transmitted, a first processor to transmit said control packet stored in one queue of said plurality of queues to a host a by one-to-one interrupt, a second processor to divide said control packets stored in said one queue into groups of a predetermined size and transmit said control packets to said host in the group unit and by direct memory access (DMA), a third processor to discard a most common type of said control packets stored in said one queue, and a controller to control said first, second and third processors to selectively operate in accordance with an accumulation state of said control packets stored in said plurality of queues.

Abstract: To emulate an interrupt architecture in a data processing system, interrupt emulation code receives from an operating system a first call requesting access to a first resource in a first interrupt architecture. In response to receipt by the interrupt emulation code of the first call, the interrupt emulation code maps the first resource to a second resource in interrupt hardware of the data processing system. The mapping operation includes determining an identifier of the second resource in a different second interrupt architecture. The interrupt emulation code then initiates access to the second resource implemented by the interrupt hardware.

Abstract: An apparatus and method for handling an interrupt are disclosed. In one embodiment, a processor may receive an interrupt request corresponding to a particular interrupt. The particular interrupt may be one of a group of interrupts. Responsive to receiving the interrupt request, the processor may substitute a vector corresponding to the group of interrupts with a vector corresponding to the particular interrupt. Responsive to the substitution, the processor may then jump to a service routine corresponding to the particular interrupt. Execution of the service routine may resolve the condition which initially caused the interrupt request.

Abstract: A wearable computer system includes a processing unit (102) and a number of peripherals. The processing unit and peripherals are coupled in a daisy-chain fashion utilizing a serial bus (120). The processing unit has a single connector for implementing the serial bus, and peripherals each have two connectors for propagating the serial bus. The wearable computer system has only one unused connector at any one time, thereby reducing excess bulk and weight due to excessive unused connectors. When a peripheral interrupts the processing unit, the processing unit relinquishes the serial bus to the interrupting peripheral. Alternatively, peripherals are assigned time slots within which the peripherals can utilize the serial bus.

Abstract: A data transmission device is used to forward data that have been received from a first device, and are intended for a second device, to the second device. The data transmission device described has a whole series of characteristics that allow the data that are to be transmitted to be transmitted very easily very quickly and which confer additional functions on the data transmission device.

Abstract: An API including an interrupt handler registration function and one or more interrupt dispatchers, is provided to an optical networking apparatus to facilitate registration of interrupt handlers to handle interrupts triggered by the function blocks of multi-protocol optical networking modules (MPONM). Each registered interrupt handler may handle interrupts triggered by one or more function blocks of any of the MPONM, and/or for one or more cause. In one embodiment, the one or more interrupt dispatchers are equipped to determine the triggering function block and the cause, and determine the interrupt handlers, if any, are to be notified. Each of the interrupt handlers to be notified is notified accordingly, including the triggering function block and the cause.

Abstract: A method for processing an interrupt message in a system having a plurality of processors arranged into at least two partitions. The interrupt message is decoded to identify an interrupt source. If the interrupt source is not in an interrupt set, the interrupt is dropped. If the interrupt source is in a local partition, the interrupt is delivered. If the interrupt source is in the interrupt set and not in the local partition, the interrupt is processed in accordance with at least one of a target enable register and a vector enable register.

Abstract: A method and system for forwarding interrupt requests from a source device to a destination device. A controller bridge receives data, from a source device, for a destination device and stores the incoming data in a data queue. An interrupt request is received from the source device for the destination device and forwarded to the destination device in response to completing a transfer of the data from the source device to the destination device. If data received from the source device for the destination device are pending in the data queue, the interrupt request is rejected and the source may resubmit the interrupt request at a later time. If additional data are received from the source device for the destination device, the data may be rejected in response to an interrupt pending in the interrupt queue from the source device for the destination device.

Abstract: A bus simulation apparatus for simulating a bus connecting a plurality of devices. Each of a plurality of simulated bus slot application interfaces prepares a receive task in response to a call from a simulated device corresponding to each of the plurality of the devices. The receive task obtains a communication handle for an application name of the simulated device. A communication handle management table relates the communication handle to the application name. A simulated bus manager, in response to a request for data transfer between the simulated devices along with the application name, sends data to the receive task of destination using the communication handle obtained by searching the communication handle management table based on the received application name.

Abstract: A method of processing interrupts is described as well as processing devices. A processing device detects an indicator associated with an interrupt signal from an expansion device and transfers data related to the interrupt signal from the device across the expansion bus to a local memory. The device then process the data related to the interrupt.

Abstract: An interrupt generating register within an interrupt control circuit is mapped in a memory space of the node. By issuing a store command to the memory space, the node transmits the store command to an address of the interrupt generating register via a network. An interrupt control circuit receives the store command, generates an interrupt command, and transmits the generated interrupt command to a CPU module.

Abstract: Systems, methods, and software for reducing system management interrupt (SMI) latency while operating in system management mode. The present invention implements a technique for exiting system management mode while waiting for polled hardware events, handling any pending lower-priority interrupts and then resuming polling. The present invention does this by multi-threading SMI source handlers, using an idle thread, and using protocols for software-generated system management interrupts that insure that lower priority interrupts are serviced.

Abstract: An interconnection controller for use in a computer system having a plurality of processor clusters is described. Each cluster includes a plurality of local nodes and an instance of the interconnection controller. The interconnection controller is operable to transmit locally generated interrupts to others of the clusters, and remotely generated interrupts to the local nodes. The interconnection controller is further operable to aggregate locally generated interrupt responses for transmission to a first remote cluster from which a first interrupt corresponding to the locally generated responses was generated. The interconnection controller is also operable to aggregate remotely generated responses for transmission to a first local node from which a second interrupt corresponding to the remotely generated responses was generated. A computer system employing such an interconnection controller is also described.

Abstract: An information handling system is disclosed that retires events upon device replacement. The system has several devices of one or more types and each device includes nonvolatile memory. A unique identifier, for devices of that type, is stored in the nonvolatile memory of each device. A first memory segment stores an event log. The event log has entries that identify system events. A second memory segment stores identifiers of devices that correspond to an entry of the event log. At least one of the corresponding devices is removable. The system detects the removal of the devices and, in response, removes any entries in the event log that correspond only to identifiers of one or more devices that have been removed.

Abstract: The invention relates to the processing of state information such as interrupt status in a hierarchical network of nodes having a tree configuration. There is a root node at the top of the hierarchy, one or more intermediate nodes, and a plurality of leaf nodes at the bottom of the hierarchy. Each leaf node is linked to the root node by zero, one or more intermediate nodes. Each leaf node maintains information about one or more interrupt states, and each intermediate node maintains information derived from the interrupt states of leaf nodes below it in the hierarchy. This interrupt information is then processed by navigating from the root node to a first leaf node having at least one set interrupt state which is then masked out. The status of any intermediate nodes between this first leaf node and the root node is then updated if appropriate to reflect the fact that the particular interrupt state at the first leaf node is now masked out.

Abstract: In a microcomputer, a testing-purpose interrupt request signal generator generates a testing-purpose interrupt request signal, an interrupt request selecting register stores an interrupt request selection signal for making an interrupt request during testing effective, and at least one delay circuit generates one or more delayed interrupt request selection signals obtained by delaying the interrupt request selection signal by one or more delay times. Each of selection circuits selects either one of the interrupt request signals or the testing-purpose interrupt request signal based on the delayed interrupt request selection signal. The testing-purpose interrupt request signals output from the respective selection circuits at a different timing, can be sequentially input to the interrupt controller.

Abstract: A system and method for generating sequences of triggered events and for generating global interrupts in a clustered computer graphics system. In a sender-receiver dichotomy, one node is deemed the sender and the others act as receivers. The sender determines trigger values for each of the nodes in the system in order to achieve a particular operation sequence. In addition, a synchronization signal generator is provided to synchronize a timing signal between the sender and receiver nodes. Further, the sender designates one or more receiver nodes and causes them to turn on an interrupt enable register. In this way, the receiver nodes are able to be interrupted by the sender.

Abstract: System and method for supporting split transactions on a bus. The method may comprise processing a periodic frame list of external bus data frame by frame, and traversing each frame node by node. When a save place node is encountered in a first frame, the traversing jumps to a destination node pointed to by the save place node in a second frame, and continues the traversing there. When a restore place node is encountered when traversing the nodes in the second frame, the traversing returns to the node after the save place node in the first frame and continues the processing in the first frame. The method may be implemented on a system that comprises a processor, a memory, an internal bus, and an external bus controller. The external bus controller and the external bus data may support one or more versions of the Universal Serial Bus standard.

Abstract: A method, apparatus, and computer instructions for managing interrupts using a set of presentation controllers. A first interrupt server is identified in the set of interrupt servers to handle the interrupt in response to receiving an interrupt signal. The set of interrupt servers constituting a server pool are linked in a circular list using a set of identifiers. The message representing the interrupt is sent to a second interrupt server, such as in a second presentation controller in the set of presentation controllers based on an identifier identifying the second interrupt server in the set of interrupt servers, if the first interrupt server is unable to handle the interrupt. The identifier is found within the first interrupt controller. The interrupt is passed to different interrupt servers potentially associated with different presentation controllers within the circular list.

Abstract: A method and apparatus for delivering APIC interrupts to a processor, and between processors, as FSB transactions. Interrupts and hardware signals, generated by a PCI device, are converted into an upstream memory write interrupt and further converted into an FSB interrupt transaction, received by a processor. Interrupts marked as lowest priority re-directable are redirected based on task priority information. Support for XTPR transactions to update XTPR registers is provided. Preferred ordering of XTPR update transactions and interrupts to be redirected is provided.

Abstract: A method and apparatus for conveying data over a packet-switching network (26). Data are received from a peripheral device (25) for transmission via the network to a memory (22) associated with a central processing unit (CPU) (21), followed by an interrupt signal from the peripheral device associated with the data. One or more data packets containing the data are sent over the network to a host network interface (32) serving the memory and the CPU, followed by an interrupt packet sent over the network to the host network interface. Responsive to the interrupt packet, an interrupt input of the CPU is asserted only after the one or more data packets have arrived at the host network interface.

Abstract: An information capturing technique captures information on a processor cycle that results in a high level interrupt, such as an SMI (System Management Interrupt). A memory controller is connected to at least one processor to control a memory in response to instructions from the at least one processor. An I/O controller is connected to the memory controller to control data flow to at least one device in response to instructions from the at least one processor. Lock down logic stores captured cycle information on a processor cycle that results in interrupt.

Abstract: A processing method, a chip set and a controller for supporting message signaled interrupt. A memory write transaction on a PCI bus is monitored. When the address of the system memory specified in the interrupt message of the write transaction is located at a range of a reserved interrupt address, the interrupting service sequence is performed. The reserved interrupt address is located in an address of a system memory. Thus, the data to be processed and the system-specified message are written in the buffer and arranged in sequence. The problem of “write buffer latency” is resolved, and is irrelevant to the level of the PCI bus. Many system specified messages can be stored in the system memory, so that multiple system message signaled interrupts issue from different peripheral components can be processed in the same interrupt service routine.

Abstract: A heterogeneous computer system, a heterogeneous input/output system and a data back-up method for the systems. An I/O subsystem A for an open system and an I/O subsystem B for a mainframe are connected by a communication unit. In order to back up data from at least a disk connected to the I/O subsystem B in a MT library system and in order to permit the mainframe to access the data in the I/O subsystem B, the I/O subsystem A includes a table for assigning a vacant memory address in a local subsystem to the memory of the I/O subsystem A for an open system. A request of variable-length record format received from the mainframe is converted into a fixed-length record format for the I/O subsystem B. The disk designated according to the table is accessed, and the data thus obtained is sent to the mainframe and backed up in the back-up system.

Abstract: A pre-stored vector interrupt handling system for rapidly processing interrupt requests from input/output (I/O) devices in processor-based systems includes selection logic and an interrupt vector store to quickly deliver a branch instruction from the interrupt vector store directly to the execution unit of a processor. The interrupt vector store is either pre-loaded with a table of the processor's branch instructions during system initialization or implemented in ROM. During normal operation, when an interrupt is received, a master interrupt signal is issued to the processor, which asserts an instruction cycle mode signal to external chip select logic. The chip select logic deselects the program store and selects the interrupt vector store. An interrupt vector from the vector store is loaded onto the data bus and then directly into the execution unit of the processor.

Abstract: A heterogeneous computer system, a heterogeneous input/output system and a data back-up method for the systems. An I/O subsystem A for an open system and an I/O subsystem B for a mainframe are connected by a communication unit. In order to back up data from at least a disk connected to the I/O subsystem B in a MT library system and in order to permit the mainframe to access the data in the I/O subsystem B, the I/O subsystem A includes a table for assigning a vacant memory address in a local subsystem to the memory of the I/O subsystem A for an open system. A request of variable-length record format received from the mainframe is converted into a fixed-length record format for the subsystem B. The disk designated according to the table is accessed, and the data thus obtained is sent to the mainframe and backed up in the back-up system.

Abstract: Starting and establishing a dialog between an interruption handler and an operating system for handling of hardware interruptions by the operating system is disclosed. A recommendation for handling such an interruption, and information regarding the interruption, are stored by the interruption handler in a storage accessible by the operating system. The interruption handler calls the operating system at a predetermined interruption handling point thereof, for the operating system to handle the interruption. The handler then determines whether the operating system handled the interruption according to the recommendation.

Abstract: In operation processing devices based on Java (a registered trademark), each time a functional program is executed, in response to a command to access that function, a work area for the program which is accessed is set up dynamically within the thread work area for the thread then being executed. By applying this processing in the case of an external interrupt as well, this invention eliminates the need to maintain a separate memory area for interrupt program processing. It simplifies the processing involved in sidetracking and restoring data and switching the program to be executed. The work area for a program being run is a dynamically created memory area according to this invention. When an interrupt is generated, the register data indicating the status and register state of the program being run at that time are sidetracked in the work area for that program.

Abstract: A system and method for automatically assigning resources to a slave device inserted into a PCI backplane utilizes pairs of PCI GNT/REQ lines as bus lines of a time division multiplexed multiplexer control bus. The slave device generates a random delay number and utilizes the number to select an unassigned time slot to be assigned to the slave device. Configuration data is transferred to the slave utilizing the already existing PCI GNT/REQ lines so that no additional bus lines and card space are required to automatically assign resources to the slave device.

Abstract: An apparatus for sharing an interrupt between a controller for a parallel storage device interface and a controller for a serial storage device interface includes interrupt conditioning circuitry that masks an interrupt signal coming from the parallel storage device interface if no storage device is coupled to the parallel storage device interface. The masking of the parallel storage device interface interrupt of no storage device is coupled to the parallel storage device interface allows the controller for the serial storage device interface to share the interrupt traditionally assigned to the parallel storage device interface.

Abstract: A peripheral device is connected to an information processing device, and in the event that an interruption job is input from the information processing device while the peripheral device is processing a job by executing one of multiple device control programs holding the functions of multiple devices engines of the peripheral device and managing jobs with the device engines, another device control program different from the device control program being executed is selected and the interruption job is executed. Accordingly, a user-friendly multifunctional peripheral device can be provided.

Abstract: A method and system for allocating distributed resources connected to a computer network to application programs running on computers attached to the communications network. The distributed resource allocator system comprises a number of identical processes running on one or more computers attached to the communications network. Application programs request allocation of resources from a local distributed resource allocator system process running using a resource allocator applications programming interface. Application programs request allocation of resource from a remote distributed resource allocator system process via a resource allocator access protocol. The distributed resource allocator system is fault-tolerant and provides contention control and load balancing. The resource allocator system also manages information about the capacities and capabilities of resources connected to the communications network.

Abstract: An apparatus and method for reducing operating system interrupts by queuing incoming network traffic units received by a network interface, where said units are received without interrupting a host environment on receiving queued units. However, if a predetermined number of received units have a same origin, then the host environment is interrupted as subsequent network traffic units are received by the network interface, until a predetermined number of network traffic units are subsequently received from a different origin. Notwithstanding queuing incoming network traffic units, the host environment is interrupted on expiration of a timeout period, or if a predetermined number of units have been queued.

Abstract: One embodiment of the present invention provides a method for processing a remote interrupt signal or a remote event. Another embodiment of the present invention provides a system for issuing a raw packet over a network in response to a remote interrupt or a remote event. Another embodiment of the present invention provides a network interface system configured to issue interrupt requests over a network.