Abstract: A communication controller for handling high speed multi protocol data streams, wherein a stream is comprised of frames. Communication controller has two processors, second processor initializes first processor and handles high level management and protocol functions, first processor handles the data stream transactions. First processor and second processors are coupled to a two external buses. First processor handles a transactions of a frame by executing a task. First processor performs a task switch when there is a need to fetch information from an external unit, coupled to either first or second external bus, if it did process a whole frame, or if there is a need to fetch a portion of a frame from a communication channel.

Abstract: A computing or processing system including a microprocessor and a memory coupled together by a local bus, and also includes a north bridge providing translation to a PCI or other standard bus. The system also includes a device bus, which may or may not be coupled to the PCI bus by a south bridge. A device bus interface bypasses the north and south bridges, to provide a single-step interface to the device bus. This reduces the latency.

Abstract: A first bus 11 and a second bus 12 are connected through a bus repeater 13 having a buffer memory, and DMA (Direct Memory Access) controllers 22, 27 are respectively connected to the buses 11 and 12. The bus repeater 13 can issue DMA request to the respective DMA controllers 22, 27, and these DMA requests can be masked by respective CPUs 22, 27. The DMA controller 22 carries out DMA transfer of data on the bus 11 between the DMA controller 22 and the buffer memory within the bus repeater 13, and the DMA controller 27 carries out DMA transfer between the buffer memory and the bus 12. The CPU 22 masks DMA request of the bus repeater 13 to directly access the buffer, thereby making it possible to check DMA function. Thus, debugging of the system for carrying out DMA transfer through buffer between different buses is easily carried out.

Abstract: The circuit converts data and has at least one programmable mini-processor, a program and data memory as well as a bus controller. For increasing the data throughput, the electronic circuit is integrated on an application-specific integrated circuit.

Abstract: A computer system includes a processor/PCI bus bridge that couples a processor bus to a relatively high-speed expansion bus, such as a PCI bus and a PCI extension bus. The PCI extension bus is coupled to a 32-bit PCI device, a 64-bit PCI device, and a non-PCI device, such as a device normally connected to a relatively low speed bus. In operation, an arbiter in the bus bridge selectively grants either the 64-bit PCI device or the non-PCI device access to the PCI extension bus. Data transfers between the processor bus and the non-PCI device can occur simultaneously with data transfers between the processor bus and the 32-bit PCI device. Several non-PCI devices may be coupled to the PCI extension bus. Data transfer between the processor bus and the non-PCI devices may be accomplished alternately if the non-PCI devices share the same lines of the PCI extension bus or simultaneously in the non-PCI devices use different lines of the PCI extension bus.

Abstract: A direct input/output port access device according to the invention which can control data accesses directly between an input port and an output port. The direct input/output port access device includes a local data bus which electrically connects the input port and the output port, an input/output port read/write controller and a data bus transceiver. In a direct input/output port access operating mode, the data bus transceiver is controlled by the input/output port read/write controller to electrically separate the local data bus from a system data bus. Simultaneously, the input/output port read/write controller generates can control data accesses directly between the input port and the output port according to read/write request status signals of the output port and the input port. At this time, a microprocessor can process other operations using the system data bus.

Abstract: A method and apparatus for processing data packets through direct memory access (DMA) in transferring data packets between a bus and an apparatus containing DMA engines. The DMA engines process different contexts, also referred to as distinct logical data streams. The phase of a bus along with the status of DMA transactions are monitored. The phase and the status are used to dynamically allocate priorities to the DMA engines to maximize the efficiency in processing data.

Abstract: The present invention provides a data processing apparatus and method for controlling timing of transfer requests. The data processing apparatus comprises a bus for interconnecting a number of logic units, data being transferable between the logic units via the bus. A first logic unit is arranged to issue onto a bus a transfer request and a type signal indicating the type of the transfer request, and a second logic unit is arranged to receive the transfer request from the bus and to perform an operation in response to the transfer request. In accordance with the present invention, the first logic unit is arranged to encode within the type signal a timing indication used to control the timing of the receipt of the transfer request by the second logic unit. By this approach, the performance of the data processing apparatus can be increased, since the performance of transfer requests can be governed directly by the actual performance of the logic unit issuing the transfer request.

Abstract: A method and apparatus are described that permit an application to control data transfer from a memory object of a source device to a sink device. The application can request that an operating system establish a mapping between a fast buffer and a memory object storing the data. The operating system then establishes the mapping between the fast buffer and the memory object thereby permitting the application to direct that the data of the memory object be transferred to the sink device. Thus, the sink device can use direct memory access to the source device to transfer the data from the memory object. Furthermore, if the application modifies a portion of the data of the memory object prior to directing the transfer, only the modified portion of the data is copied to main memory prior to transfer to the sink device.

Abstract: The method of the present invention includes maintaining a first tier 101 and a second tier 102 of devices 30 that have access to a secondary bus 42 that a PCI to PCI bridge 38 services. Each device 30 that has access to secondary PCI bus 42 is categorized into either first tier 101 or a second tier 102. The devices 30 in first tier 101 are provided more frequent opportunities to gain access to secondary PCI bus 42 than devices in low tier 102. Next, a pending transaction is recognized when an initiating device 30 that has been categorized into second tier 102 accesses secondary PCI bus 42 and attempts a transaction that crosses PCI to PCI bridge 38 to primary PCI bus 26. However, PCI to PCI bridge 38 is unable to complete the transaction on primary PCI bus 26. Therefore, PCI to PCI bridge 38 is unable to provide access to any other device 30 on secondary bus 42 until the pending transaction completes.

Abstract: A memory cache device for a CD-ROM for use with a host computer capable of initially filling a clone area of the hard disk with data from the compact disc using a sequential striped fill process for copying a plurality of blocks of data from the compact disc to the hard disk, the process comprising the steps of: accessing a first block of data of a sequence of data blocks from the compact disc and copying the first block onto the hard disk, accessing a second block of data in the sequence of data blocks from the compact disc and not copying the second block to the hard disk, and accessing a third block of data in the sequence of data blocks from the compact disc and copying the third block onto the hard disk, the fill process continuing until the entire capacity of the hard disk devoted to cloning the compact disk is full, while leaving sufficient area for storage of blocks not initially copied in the fill process.

Abstract: A very long instruction word (VLIW) processor exploits program level parallelism as well as instruction level parallelism. Unlike prior VLIW machines which obtain speed advantages using instruction level parallelism, the present processor exploits the parallelism inherent in a VLIW processor by providing new instruction level mechanisms to separate processor execution into parallel threads. This separation allows greater hardware use because more than one program can exploit instruction level parallelism on the system at the same time. A first program and a second program execute concurrently such that the second program executes using resources and cycles that would have been wasted by the first program. This construct is especially useful where the second program is an interrupt service routine because the interrupt service routine can be threaded through the machine with high or low priority while the functional units still process the first program stream.

Abstract: In an FDD control apparatus for controlling a floppy disk drive for driving a floppy disk loaded in the floppy disk drive, an FDD control part including a floppy disk controller (FDC) is disposed in an FDD side in lieu of a host side (a SET side). The host side (SET side) is loaded with a USB connector connected to the FDD control part. The FDD control part includes a flash ROM for storing a program for adjusting a step timing of a stepping motor.

Abstract: A bus bridge for a computer system for bridging first and second buses includes a shift and accumulate unit. The shift and accumulate unit includes a shifter having an input connected to receive bytes from one of the first and second buses and an output providing a selectable shift to the received bytes. The shift and accumulate unit also includes an accumulator having an input connected to receive the output of the shifter and providing accumulation of selectable bits of the shifted bytes, the accumulator having an output for supplying realigned bytes to be passed to the other of the first and second buses. The combination of the shifter and the accumulator permits a desired amount of shift to be combined with the accumulation of selected bits or bytes to realign sets of bytes from one bus and to form sets of bytes for the other bus. Burst transfer is also possible by operating the shift and accumulate unit to operate in successive cycles for successive sets of input bytes from one of the buses.

Abstract: The invention, in one embodiment, is a method for accessing memory. The method includes programming a remote DMA engine from a destination; accessing data in the memory with the DMA engine, the DMA engine operating as programmed by the destination; and transferring the accessed data to the destination.

Abstract: Improved techniques for controlling buses of a computer system are disclosed such that peripheral devices (and/or their associated buses) can be connected or disconnected to the computer system while the computer system is active. The peripheral devices are connected to the computer system by being inserted into a slot or other receptacle of the computer system. The peripheral devices are disconnected from the computer system by being removed from a slot or other receptacle of the computer system. The slots or receptacles typically includes connectors designed to receive peripheral devices, such as PC CARD slots, expansion bays, and the like. Given that the peripheral devices can be inserted or removed while the computer system is active is active, the computer system according to the invention permits “hot-plugging” of peripheral devices. The invention is particularly well suited for controlling PCI buses for peripheral devices connecting to a computer system by way of peripheral ports.

Abstract: A first bus 11 and a second bus 12 are connected through a bus repeater 13 having a buffer memory, and DMA (Direct Memory Access) controllers 22, 27 are respectively connected to the buses 11 and 12. The bus repeater 13 can issue DMA request to the respective DMA controllers 22, 27, and these DMA requests can be masked by respective CPUs 1, 6. The DMA controller 22 carries out DMA transfer of data on the bus 11 between the DMA controller 22 and the buffer memory within the bus repeater 13, and the DMA controller 27 carries out DMA transfer between the buffer memory and the bus 12. The CPU 21 masks DMA request of the bus repeater 13 to directly access the buffer, thereby making it possible to check DMA function. Thus, debugging of the system for carrying out DMA transfer through buffer between different buses is easily carried out.

Abstract: There is provided a data transfer apparatus for transferring data from a main memory coupled to a main bus to a local memory coupled to a local bus. The data transfer apparatus includes: a first-in-first-out buffer having a data region for storing one or more words of CPU access data which is accessed by a CPU coupled to the main bus, and a plurality of words of DMA access data which is accessed by a DMA controller coupled to the main bus; and a controller for controlling the first-in-first-out buffer. When the local bus is available, the controller controls the first-in-first-out buffer so as to consecutively transfer the one or more words of CPU access data stored in the data region to the local memory, and to burst transfer the plurality of words of DMA access data stored in the data region to the local memory.

Abstract: A first bus 11 and a second bus 12 are connected through a bus repeater 13 having a buffer memory, and DMA (Direct Memory Access) controllers 22, 27 are respectively connected to the buses 11 and 12. The bus repeater 13 can issue DMA request to the respective DMA controllers 22, 27, and these DMA requests can be masked by respective CPUs 22, 27. The DMA controller 22 carries out DMA transfer of data on the bus 11 between the DMA controller 22 and the buffer memory within the bus repeater 13, and the DMA controller 27 carries out DMA transfer between the buffer memory and the bus 12. The CPU 22 masks DMA request of the bus repeater 13 to directly access the buffer, thereby making it possible to check DMA function. Thus, debugging of the system for carrying out DMA transfer through buffer between different buses is easily carried out.

Abstract: A data transfer controller (14) decides that both of a host bus (100) and a local bus (101) have been acquired by a bus interface LSI 1b by the fact that a host bus use permission GNTH from a host bus arbiter (2b) and a local bus use permission GNTL from a local bus arbiter (4) are both activated, in which case, the data transfer controller (14) controls a host bus DMA controller (12) and a local bus DMA controller (13) to make selectors SE1 and SE2 establish a connection between the host bus (100) and the local bus (101) through an inner data path (11b) having no buffer. This configuration improves data transfer rate through the host bus (100) and the local bus (101).

Abstract: A bus bridge coupled between two bridges providing bus exception event isolation and address/data translation. In one embodiment the bus bridge includes two direct memory access (DMA) engines and a first-in-first-out (FIFO) buffer interface between the DMA engines to provide the bus exception isolation. The DMA engines and FIFOs also enable a packet based message passing architecture, which eliminates the need for address translation and also handles data reordering.

Abstract: In an information processing apparatus equipped with a CPU, an operating rate of this CPU is increased so as to increase a throughput of this entire information processing apparatus. The information processing apparatus is arranged by first and second internal buses independently provided from each other, an internal memory connected to the first internal bus, and a timer 25 connected to the second internal bus. Furthermore, this information processing apparatus is arranged by an A/D converter, first/second serial interfaces, the CPU, and a DMAC (direct memory access controller). Both the CPU and the DMAC control data input/output operations in the internal memory and the timer while occupying at least one of these fist/second data buses.

Abstract: A computer system includes a host computer and a peripheral memory device such as a CD ROM which are interconnected by a bus including a plurality of pipes defined by packets, time division multiplexing, frequency division multiplexing, or code division multiplexing. A plurality of pipe configuration registers are maintained for controlling bus configuration. A BUS controller for the bus includes a plurality of registers for controlling data transfer including pipe data flow direction, packet size, control information, bandwidth setting, and descriptor pointer. The plurality of pipes can have different bandwidths and latencies to efficiently facilitate the transfer of commands, data, and control information. The peripheral memory device is able to transfer and receive data directly to and from the host computer using a dedicated pipe without the need of a buffer memory at the peripheral device.

Abstract: The present invention provides a cache memory system which allows a user to update cache memory in advance without adding special hardware. The cache memory system comprises cache memory composed of a plurality of banks, a cache controller which issues an update instruction as directed by a command, and a DMA controller which transfers data. The cache controller has a command register in which a cache update instruction from a central processing unit is stored. When a cache miss occurs or when the cache controller detects that data was written into the command register, the cache controller issues a DMA transfer instruction to the DMA controller.

Abstract: A method and apparatus for transferring data in a computer system between a first memory region and second memory region in a single Direct Memory Access (DMA) operation. The first memory region, the second memory region, or both the first and second memory regions can include sub-regions of sequentially-addressable memory locations that are separated, within their respective regions, by a stride. The method and apparatus are particularly well adapted for use in computer graphics systems that include one or more regions of memory, such as frame buffers, that are organized in a rectangular manner as a plurality of contiguous but not sequentially-addressable memory locations within the memory of the graphics system.

Abstract: A data bus is divided into two portions. One portion of the bus transfers data from one side of the bus to the other and the other portion of the bus transfers data in the opposite direction. Bus cycles that originate from one side of the bus only go in one direction (from the originator to the other side). In order to avoid inefficiency because one of the portions of the bus may become unused if a long bus cycle is going in one direction while nothing is being transferred in the opposite direction, one side can take over the whole data bus and transfer data over both sides of the bus.

Abstract: A method for managing data transfers with minimal host processor involvement. Data is transferred between a peripheral device coupled to a host computer and a network device over a high performance bus. In one exemplary embodiment, data is transferred over a bus utilizing the IEEE 1394 communication protocol and a network utilizing the Ethernet communication protocol. The novel data transfer method advantageously minimizes the involvement of the host computer's processor in the management of data transfers, thus maximizing the host processor's availability for performing other computations. Specifically, to transfer data from the peripheral device to the network, the host processor generates a data pointer table and sends it to the network device. A processor in the network device then takes over data transfer management, using information in the data pointer table to locate and transmit the designated block of data from the peripheral device to the network.

Abstract: A system including a host coupled to a memory device and a peripheral controller device. The host is coupled to the peripheral controller device via a bus having a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The peripheral controller device performs direct memory access (DMA) transactions with the memory device via the host and the bus.

Abstract: A method and apparatus which may be used for direct memory access (DMA) acknowledges. A method of acknowledging a request for access to a bus from a bus agent access involves receiving a request for access to the bus and generating a request acknowledge signal. The request acknowledge is generated on a multiplexed bus in response to the request for access to the bus.

Abstract: A method for accessing a shared resource is provided. An assigned usage rate is received from a resource coordinator and a desired usage rate is determined. When it is determined that the desired usage rate is higher than the assigned usage rate, a shared resource may be accessed at an enhanced usage rate if a usage reserve has been accumulated. When a shared resource is accessed at an enhanced usage rate, the usage reserve is decremented by an amount based on a difference between the enhanced usage rate and the assigned rate. When there is no usage reserve accumulated, access to the shared resource is limited to the assigned usage rate. When the desired usage rate is not higher than the assigned usage rate, a shared resource is accessed at the desired usage rate. When the desired usage rate is less then the assigned usage rate, the usage reserve is accumulated up to a reserve maximum. The reserve maximum may be based on configuration data.

Abstract: A computer system implementing a distributed direct memory access architecture is disclosed. The computer system includes a re-map engine that includes control logic and a shadow register for each distributed DMA channel. Each shadow register includes 16 bytes of DMA configuration information that mirrors the current programming of the associated distributed DMA channel. When the CPU needs to program one or more DMA channels, the CPU sends a DMA master programming cycle to the control logic in the re-map engine. The re-map control logic compares the configuration data in the master cycle with the contents of the shadow registers and spawns daughter programming cycles to just those distributed channels for which a mismatch condition exists. If a match exists with respect to a particular channel, indicating that the new programming data is no different than the current programming of the channel, the control logic does not spawn a daughter programming cycle to that channel.

Abstract: A communications unit configured to be implemented in an ASIC environment utilizes only a small amount of chip surface area and requires a minimum number of pins. The unit operates asynchronously with respect to the ASIC internal clock so that communications can occur independent of such internal clock. In one embodiment the communications unit includes a controller coupled to a shift register via a data bus. Pin connections to the controller include a request line REQ, an input/output control line I/O (or INOUT), an acknowledgement line ACK, an external clock line EXTCLK, and a data line DATA. The shift register also is coupled, via a data bus, to a memory module, e.g., a RAM. An ASIC processor is coupled to the controller, shift register and memory module via control lines.

Abstract: A memory disc sharing method in which a plurality of computers share a memory disc through a network, wherein a command in accordance with which the memory disc is accessed is received by a network interface apparatus, and when a requested computer to which a request of the command has been made is any of other computers, the command is transmitted to the any of other computers, and when the requested computer is a computer concerned, the command is stored in a memory disc command queue. The network interface apparatus retrieves the command from the memory disc command queue, and executes the processing of reading out/writing data from/to the memory disc in the computer concerned when a requesting computer from which a request of the command has been made is the computer concerned, and carries out the data transfer between the memory disc in the computer concerned and the requesting computer when the requesting computer is any of other computers.

Abstract: The invention, in one embodiment, is a method for accessing memory. The method includes programming a remote DMA engine from a destination; accessing data in the memory with the DMA engine, the DMA engine operating as programmed by the destination; and transferring the accessed data to the destination.

Abstract: A process and system for transferring data including at least one slave device connected to at least one master device through an arbiter device. The master and slave devices are connected by a single address bus, a write data bus and a read data bus. The arbiter device receives requests for data transfers from the master devices and selectively transmits the requests to the slave devices. The master devices and the slave devices are further connected by a plurality of transfer qualifier signals which may specify predetermined characteristics of the requested data transfers. Control signals are also communicated between the arbiter device and the slave devices to allow appropriate slave devices to latch addresses of requested second transfers during the pendency of current or primary data transfers so as to obviate an address transfer latency typically required for the second transfer.

Abstract: The invention provides a data processing system comprising: a CPU; a system memory; a plurality of network interfaces; a CPU bus connected to the system memory and to each of the network interface for initialization and control of the network interfaces by the CPU; an individual DMA bus connected to each of corresponding network interfaces and to the system memory; each of the network interfaces is connectable to an external network, whereby data can be transferred by the data processing system from one network to another using system memory.

Abstract: A method and implementing system are provided which includes a DMA controller coupled to a slave bus controller through a processor local bus. The slave bus controller is also coupled to a memory unit. The memory unit is connected directly to a peripheral device. The DMA controller is arranged to receive a data transfer request from the peripheral unit and initiate a transfer cycle with the slave bus controller. The slave bus controller is selectively operable to assert a transfer signal to the memory unit which enables data movement directly between memory and the peripheral device in accordance with the request from the peripheral device. Upon completion of the address transfer and prior to the completion of the data transfer, the slave bus controller generates a transfer complete signal back to the peripheral device. This technique allows for a DMA FlyBy transfer to be overlapped with a subsequent processor local bus transfer.

Abstract: A multimedia system including a PCI bus master controller for transferring concurrent and independent video and audio data streams to video and audio devices. The controller includes a video request and DMA channel, a video sub-picture request and DMA channel, an audio request and DMA channel, and a decompressed video DMA and posted request channel for independently and concurrently transferring the data streams from host memory to the devices. The host processor builds lists of request packets in system memory and asynchronously submits the request packets to the controller. The request packets include commands which the request channels execute. The commands may include spinning on status conditions in registers of the multimedia devices, writing to registers of the devices, or performing bus master transfers of multimedia data streams from system memory to the devices. The device register accesses are performed by the controller on local buses thereby reducing PCI bus traffic.

Abstract: A system and method for optimizing the amount of time it takes for a requestor (device) to receive data from a memory storage unit in a multi-requestor bus environment. The present invention provides a unidirectional response signal, referred to as an early warning signal, sent from a memory storage unit to a device, sometime after that device has executed a fetch request for data, to alert the device that the data is forthcoming. This early warning signal allows the device to arbitrate for the data bus so that when the data arrives, the device will have exclusive ownership of the data bus to accept the data immediately. The present invention comprises a main memory, a cache memory, one or more processor modules, one or more I/O modules, and an early warning bus. The cache memory is connected to the main memory via an interface bus. The processor modules are connected to the cache memory via a processor interface bus. The I/O modules are connected to the main memory via an I/O interface bus.

Abstract: A PCMCIA host adapter includes the capability to master a non-DMA system bus and control a DMA data transfer between a DMA capable peripheral and the internal system memory. A peripheral can be coupled to the system through a PCMCIA card plugged into a PCMCIA expansion slot. A DMA controller coupled to the PCMCIA expansion slots through a PCMCIA bus controls a DMA transfer between the internal system memory and the peripheral. A bus master disables the CPU and takes control of the system bus during a DMA data transfer. In an alternative embodiment, the PCMCIA host adapter can be used with either a system having a system bus with DMA capability or with a system having a system bus without DMA capability. In this alternate embodiment if the system bus has DMA capability, the PCMCIA host adapter effectively passes the DMA signals between the peripheral and the system bus.

Abstract: A DMA controller receives size data in association with a DMA request. If first size data is received, a first amount of data (for example, one word) is transferred through the DMA controller for the DMA request. If, on the other hand, second size data is received, then a second amount of data (for example, two words) is transferred through the DMA controller for the DMA request. In the event that a DMA request cannot be serviced when received, the DMA request is stored in the DMA controller for later servicing. Size data for a DMA request is stored so that the size of the data transfer will be known when the stored DMA request is serviced. Using this size data, a single DMA channel can support data transfers of different sizes. In some embodiments, size data is used to increment a DMA current address register by the correct amount after the data associated with the size data is transferred through the DMA controller.

Abstract: The present invention relates to a system and method for supporting DMA I/O devices. A PCI-PCI bridge is provided to support DMA I/O devices on the PCI bus. Through the use of two signal lines and a serial link, DMA transfers may be accomplished over the PCI bus. A PCI-ISA dock bridge is also provided to allow the system to support DMA I/O devices and ISA masters (i.e., any device including DMA I/O devices on the ISA bus that generates ISA cycles) on the ISA bus.

Abstract: To increase access speed, a single-chip computer system having a direct memory access (DMA) mode, includes a central processing unit (CPU) for executing instructions, a first bus connected to the CPU, a memory array connected to the first bus, for storing data, a buffer connected to the first bus, a second bus connected to the buffer, and a communication circuit, connected to the second bus, for receiving and outputting data. The buffer connects the first bus to the second bus when the DMA mode is executed, and disconnects the first bus from the second bus when the DMA mode is not executed.

Abstract: A system and method that allows ISA-compatible DMA devices (60) to communicate over non-ISA buses such as the VL bus (20) and a PCI bus (30). In a computer system (10) with a non-ISA bus, the present invention couples a secondary set of DMA controllers (50) in the same input/output space and a glue logic circuit (70) to the non-ISA bus in the computer system (10) to allow the ISA-compatible DMA device (60) to operate over the non-ISA bus. The secondary set of DMA controllers (50) provides the support for an ISA-compatible DMA device (60) to perform DMA transactions and the glue logic circuit (70) directs the DMA controller accesses to the proper place in the computer system (10).