Abstract: This disclosure provides techniques for managing writes of data useful for storage systems that do not permit overwrite of a logical address. One implementation provides a nonvolatile memory storage drive, such as a flash memory drive, that provides support for zoned drive and/or Open Channel-compliant architectures. Circuitry on the storage drive tracks storage location release metadata for addressable memory space, optionally providing to a host system information upon which maintenance decisions or related scheduling can be based. The storage drive can also provide buffering support for accommodating receipt of out-of-order writes and unentanglement and performance of out of order writes, with buffering resources being configurable according to any one of a number of parameters. The disclosed storage drive facilitates reduced error rates and lower request traffic in a manner consistent with newer memory standards that mandate that writes to logical addresses be sequential.

Abstract: Structures and methods are provided for integrating a resistance random access memory (ReRAM) in a back-end-on-the-line (BEOL) fat wire level. In one embodiment, a ReRAM device area contact structure is provided in the BEOL fat wire level that has at least a lower via portion that contacts a surface of a top electrode of a ReRAM device area ReRAM-containing stack. In other embodiments, a tall ReRAM device area bottom electrode is provided in the BEOL fat wire level and embedded in a dielectric material stack that includes a dielectric capping layer and an interlayer dielectric material layer.

Abstract: A method of operating a terminal device for transmitting a first amount of data, the method comprising receiving an indication of an allocation of communications resources, the allocated communications resources sufficient for transmitting a second amount of data, the second amount of data greater than or equal to the first amount of the data, selecting from a plurality of permitted TBS values a transport block size, TBS, for the transmission of the first amount of data, based on the first amount, determining communications resources for transmitting the first amount of the data based on the selected TBS and the allocated communications resources, and transmitting the first amount of the data using the determined communications resources.

Abstract: A two pin communication interface bus and control circuits are used with circuit boards, integrated circuits, or embedded cores within integrated circuits. One pin carries data bi-directionally and address and instruction information from a controller to a selected port. The other pin carries a clock signal from the controller to a target port or ports in or on the desired circuit or circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is minimal. The bus is used for communication, such as serial communication related to the functional operation of an IC or core design, or serial communication related to test, emulation, debug, and/or trace operations of an IC or core design.

Abstract: An outdoor satellite receiving unit (ODU) receives several independent satellite signals, selects two signals with a switch matrix, downconverts the two signals to a bandstacked signal with a high and a low band signal, and outputs the bandstacked signal on the same cable to receiver units. Several satellite signals can be selected in groups of two or more and output to independent receiver units. Signal selecting is performed at the received radio frequency (RF) and bandstacking is performed with a single downconversion step to an intermediate frequency (IF). Channel stacking on the same cable of more than two channels from several satellites can be achieved by using frequency agile downconverters and bandpass filters prior to combining at the IF output. A slow transitioning switch minimizes signal disturbances when switching and maintains input impedance at a constant value.

Abstract: This disclosure provides techniques for managing writes of data useful for storage systems that do not permit overwrite of a logical address. One implementation provides a nonvolatile memory storage drive, such as a flash memory drive, that provides support for zoned drive and/or Open Channel-compliant architectures. Circuitry on the storage drive tracks storage location release metadata for addressable memory space, optionally providing to a host system information upon which maintenance decisions or related scheduling can be based. The storage drive can also provide buffering support for accommodating receipt of out-of-order writes and unentanglement and performance of out of order writes, with buffering resources being configurable according to any one of a number of parameters. The disclosed storage drive facilitates reduced error rates and lower request traffic in a manner consistent with newer memory standards that mandate that writes to logical addresses be sequential.

Abstract: A semiconductor device includes a terminal group configured to receive a first signal and a second signal from a host, a first chip electrically connected to the terminal group, and a second chip electrically connected to the terminal group. The first chip is configured to, in response to reception of the first signal, transmit a third signal corresponding to the first signal to the second chip. The first chip is configured to, when the first chip has received the second signal before the first signal, refrain from transmitting the third signal to the second chip.

Abstract: A computer-implemented method and distributed system for maintaining consistency of client applications on a plurality of server nodes may comprise providing a first and second versions of a distributed coordination engine (DConE). The first version of the DConE may receive proposals, reach agreements thereon and generate a first ordering of agreements that specifies an order in which the client applications are to execute the agreed-upon proposals and correspondingly update their respective states. A ChangeVersion proposal may then be processed by the first version of the DConE, whereupon the first version of the DConE may stop reaching any further agreements. A second version of the DConE may then take over reaching agreements on the proposals and generate a second ordering of agreements, beginning with the agreed-upon ChangeVersion proposal.

Abstract: Management of immersive reality devices via a reduced competition core network component is disclosed. The reduced competition core network component can preferentially be reserved for immersive reality device data and can therefore exclude some or all other types of data typically associated with conventional wireless network devices, e.g., phone, tablet/laptop computers, IoT devices, etc. This can result in immersive reality data communication that does not have to compete with more generic data types for network or computing resources. Additionally, the reduced competition core network component can be divided into at least one reduced competition user-plane network component and at least one reduced competition control-plane network component. Use of a reduced competition user-plane network component can avoid generating additional carrier network traffic. Further, a reduced competition user-plane network component can facilitate non-carrier entity authentication, security protocols, etc.

Abstract: A method of operating a terminal device for transmitting a first amount of data, the method comprising receiving an indication of an allocation of communications resources, the allocated communications resources sufficient for transmitting a second amount of data, the second amount of data greater than or equal to the first amount of the data, selecting from a plurality of permitted TBS values a transport block size, TBS, for the transmission of the first amount of data, based on the first amount, determining communications resources for transmitting the first amount of the data based on the selected TBS and the allocated communications resources, and transmitting the first amount of the data using the determined communications resources.

Abstract: Systems and methods for implementing a multi-layer neural network using crossbar arrays are disclosed. In some implementations, an apparatus comprises: a plurality of first devices, a plurality of second devices, and a plurality of first flow controllers connecting the plurality of first devices and the plurality of second devices. Each flow controller in the plurality of first flow controllers is independently controlled from other flow controller in the plurality of first flow controllers. In some implementations, the apparatus further comprises: a plurality of third devices; a plurality of second flow controllers connecting the plurality of second devices and the plurality of third devices; and a first common ground line separating the plurality of first flow controllers and the plurality of second flow controllers. Each of the plurality of second flow controllers is independent of each of the plurality of first flow controllers.

Abstract: An emulator system and a method for emulating functionalities of an integrated circuit design are disclosed. In one aspect, the system includes a plurality of verification components each comprising circuitry configured to perform transactions with at least another verification component. The system can include a plurality of proxies, each executing on a processor and corresponding to a respective one of the verification components. The system can include a switch that is communicatively coupled with the proxies, the switch dynamically configurable to, in a first time duration, operate with a first subset of the proxies to enable a first transaction between a functional module of the design and a first verification component. The switch can be dynamically configurable to, in a second time duration, operate with a second subset of the proxies to enable a second transaction between the functional module and a second verification component.

Abstract: Implementations of the present disclosure are directed to systems and methods for mapping point-to-point channels to packet virtual channels. A chip with an point-to-point interface converts point-to-point data to a packet format. The point-to-point channels are mapped to virtual channels of the packet transmission protocol. Information from multiple point-to-point channels may be combined in a single packet. Among the benefits of implementations of the present disclosure is that point-to-point devices may be connected to a packetized network without losing the benefits of separate channels for different types of communication. This allows existing point-to-point devices to communicate using a packetized network without internal modification or performance degradation.

Abstract: Apparatuses and methods for managing a coherent memory are described. These may include one or more algorithmic logic units (ALUs) and an input/output (I/O) interface. The I/O interface may receive one or more commands and retrieve data from or write data to a memory device. Each command may contain a memory address portion associated with a memory device. The apparatus may also include a memory mapping unit and a device controller. The memory mapping unit may map the memory address to a memory portion of the memory device, and the device controller may communicate with the memory device to retrieve data from or write data to the memory device. The apparatus may be implemented as a processing element in a configurable logic block network, which may additionally include a control logic unit that receives programming instructions from an application and generate the one or more commands based on the instructions.

Abstract: Methods, systems, and apparatus, including computer-readable media, are described for interleaving memory requests to accelerate memory accesses at a hardware circuit configured to implement a neural network model. A system generates multiple requests that are processed against a memory of the system. Each request is used to retrieve data from the memory. For each request, the system generates multiple sub-requests based on a respective size of the data to be retrieved using the request. The system generates a sequence of interleaved sub-requests that includes respective sub-requests of a first request interleaved among respective sub-requests of a second request. Based on the sequence of interleaved sub-requests, a module of the system receives respective portions of data accessed from different address locations of the memory. The system processes each of the respective portions of data to generate a neural network inference using the neural network model implemented at the hardware circuit.

Abstract: A video signal transmitter or receiver for handling multiple video signals, including mainboard signal processing circuitry, one master fiber module, and one or more add-on fiber modules. Video data signal for the multiple videos are transmitted over the master and add-on fiber modules, but no video control signal is transmitted over any add-on fiber module. Video control signal for all of the multiple videos are transmitted on a first subset of channels of the master fiber module in a multiplexed manner. The mainboard signal processing circuitry cooperates with the signal processing chip of the master fiber module to process all video control signals, with the master fiber module processing video control signals for at least two videos. Non-video signals are processed by the mainboard circuitry and transmitted on a second subset of channels of the master fiber module (same as or different from the first subset of channels).

Abstract: Disclosed is an approximate physical simulation integrated debugging method based on digital twinning, which includes the following steps of: a production line simulation model building step, a twinning step, a system debugging step, a hardware-in-the-loop debugging step, and a device-in-the-loop debugging step. The approximate physical simulation integrated debugging system based on digital twinning includes a production line simulation model building module, a twinning module, a system debugging module, a hardware-in-the-loop debugging module, and a device-in-the-loop debugging module. According to the approximate physical simulation integrated debugging method and system based on digital twinning, since a local component twin after being successfully debugged is replaced with an entity component, when a problem occurs after replacement, only the local component twin needs to be debugged and optimized again, thus saving time and reducing cost.

Abstract: A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line. The flit is forwarded to the second shared memory controller using a shared memory link according to a routing path.

Abstract: Disclosed embodiments relate to an improved memory system architecture for multi-threaded processors. In one example, a system includes a system comprising a multi-threaded processor core (MTPC), the MTPC comprising: P pipelines, each to concurrently process T threads; a crossbar to communicatively couple the P pipelines; a memory for use by the P pipelines, a scheduler to optimize reduction operations by assigning multiple threads to generate results of commutative arithmetic operations, and then accumulate the generated results, and a memory controller (MC) to connect with external storage and other MTPCs, the MC further comprising at least one optimization selected from: an instruction set architecture including a dual-memory operation; a direct memory access (DMA) engine; a buffer to store multiple pending instruction cache requests; multiple channels across which to stripe memory requests; and a shadow-tag coherency management unit.

Abstract: In non-energy-backed memory with persistent storage, a complex protocol is required to handle persistent writes. To address this issue, it is proposed to provide a simple protocol to handle persistent writes in energy-backed memory with persistent storage.

Abstract: Aligning received BDIs with received data on a cross-chip link including receiving, from the cross-chip link, a control flit comprising incoming data flit information for a plurality of incoming data flits; adding the incoming data flit information to a control structure; receiving, from the cross-chip link, the plurality of incoming data flits; directing each of the plurality of incoming data flits to virtual channel queues based on the incoming data flit information at a first read pointer in the control structure; receiving a bookend flit comprising a plurality of BDIs for the plurality of data flits; and associating each of the BDIs with the plurality of data flits based on the incoming data flit information at a second read pointer in the control structure.

Abstract: Aligning received BDIs with received data on a cross-chip link including receiving, from the cross-chip link, a control flit comprising incoming data flit information for a plurality of incoming data flits; adding the incoming data flit information to a control structure; receiving, from the cross-chip link, the plurality of incoming data flits; directing each of the plurality of incoming data flits to virtual channel queues based on the incoming data flit information at a first read pointer in the control structure; receiving a bookend flit comprising a plurality of BDIs for the plurality of data flits; and associating each of the BDIs with the plurality of data flits based on the incoming data flit information at a second read pointer in the control structure.

Abstract: In one embodiment, a method for 3D digital watermarking for a triangular mesh using one or more key parameters is disclosed including forming a Hamiltonian path of a desired length around a selected vertex in a selected direction of a spiral; marking the selected vertex a dead end if there is a deadlock and continuing the spiral; and applying a watermark by introducing points in a path order on edges of the spiral, wherein information is encoded at a partition of adjacent triangles at one or more of the points.

Abstract: Bridge logic is provided to receive a request from a device, where the request references an address of a secondary address space. The secondary address space corresponds to a subset of addresses in a configuration address space of a system, and the secondary address space corresponds to a first view of the configuration address space. The bridge logic uses a mapping table to translate the address into a corresponding address in the configuration address space, where addresses of the configuration address space correspond to a different second view of the configuration address space.

Abstract: Examples relate to switching devices comprising a switch controller and a plurality of interconnected sub-switches forming an internal network of the switching device. A packet is received at a first sub-switch of the plurality of interconnected sub-switches. The packet is to be routed to a particular external output port of a second sub-switch of the plurality of interconnected sub-switches. Upon reception of the packet, the switch controller reserves a space for the packet in a queue associated to the particular external output port. Then, the switch controller routes the packet on the internal network to the particular external output to occupy the reserved space for the packet.

Abstract: To reduce overhead for cache coherence for shared cache in multi-processor systems, adaptive granularity allows tracking shared data at a coarse granularity and unshared data at fine granularity. Processes for adaptive granularity select how large of an entry is required to track the coherence of a block based on its state. Shared blocks are tracked in coarse-grained region entries that include a sharer tracking bit vector and a bit vector that indicates which blocks are likely to be present in the system, but do not identify the owner of the block. Modified/unshared data is tracked in fine-grained entries that permit ownership tracking and exact location and invalidation of cache. Large caches where the majority of blocks are shared and not modified create less overhead by being tracked in the less costly coarse-grained region entries.

Abstract: Aligning received BDIs with received data on a cross-chip link including receiving, from the cross-chip link, a control flit comprising incoming data flit information for a plurality of incoming data flits; adding the incoming data flit information to a control structure; receiving, from the cross-chip link, the plurality of incoming data flits; directing each of the plurality of incoming data flits to virtual channel queues based on the incoming data flit information at a first read pointer in the control structure; receiving a bookend flit comprising a plurality of BDIs for the plurality of data flits; and associating each of the BDIs with the plurality of data flits based on the incoming data flit information at a second read pointer in the control structure.

Abstract: Elastic cloud storage (ECS) systems typically divide storage nodes into geographic or topological zones and implement various concepts that enable the system to be extremely efficient in terms of capacity management. Architectures detailed herein can improve ECS and other similar systems in terms of inter-zone data transfers and remote data caching without violating core concepts of an ECS system that enable efficient capacity management.

Abstract: Embodiments herein may present an integrated circuit including a switch, where the switch together with other switches forms a network of switches to perform a sequence of operations according to a structure of a collective tree. The switch includes a first number of input ports, a second number of output ports, a configurable crossbar to selectively couple the first number of input ports to the second number of output ports, and a computation engine coupled to the first number of input ports, the second number of output ports, and the crossbar. The computation engine of the switch performs an operation corresponding to an operation represented by a node of the collective tree. The switch further includes one or more registers to selectively configure the first number of input ports and the configurable crossbar. Other embodiments may be described and/or claimed.

Abstract: Aligning received BDIs with received data on a cross-chip link including receiving, from the cross-chip link, a control flit comprising incoming data flit information for a plurality of incoming data flits; adding the incoming data flit information to a control structure; receiving, from the cross-chip link, the plurality of incoming data flits; directing each of the plurality of incoming data flits to virtual channel queues based on the incoming data flit information at a first read pointer in the control structure; receiving a bookend flit comprising a plurality of BDIs for the plurality of data flits; and associating each of the BDIs with the plurality of data flits based on the incoming data flit information at a second read pointer in the control structure.

Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.

Abstract: Systems and methods relate to performing data movement operations using single instruction multiple data (SIMD) instructions. A first SIMD instruction comprises a first input data vector having a number N of two or more data elements in corresponding N SIMD lanes and a control vector having N control elements in the corresponding N SIMD lanes. A first multi-stage cube network is controllable by the first SIMD instruction, and includes movement elements, with one movement element per SIMD lane, per stage. A movement element selects between one of two data elements based on a corresponding control element and moves the data elements across the stages of the first multi-stage cube network by a zero distance or power-of-two distance between adjacent stages to generate a first output data vector. A second multi-stage cube network can be used in conjunction to generate all possible data movement operations of the input data vector.

Abstract: A multivariate signature method for resisting key recovery attack, which establishes a new signature verification condition by adding additional value of signature. The verification condition implies verification of internal information x and y, thereby effectively resisting key recovery attack generated by the existence of equivalence key. Specifically, the method includes the three stages of data preprocessing, signature generation and signature verification. The invention is a signature authentication method based on polynomial equations of a plurality of variables in a finite field, which can effectively resist the key recovery attack, provide the basic technical support for the information security and the establishment of the trust system in the quantum computer era, and provide a secure digital signature option in the quantum era.

Abstract: A method includes retrieving a decode threshold number of encoded data slices, wherein codecs process, in an order, a data segment and the processed data segment is encoded into a set of encoded data slices. The method further includes decoding the decode threshold number of encoded data slices to recover the processed data segment. In a reversed order to the order, applying a first codec on the processed data segment to produce a first partially processed recovered data segment. When the first codec is a verifiable codec, the method further includes separating the first partially processed recovered data segment into an initial integrity value and a processed data segment. The method further includes calculating a new integrity value from the processed data segment. When the new integrity value substantially matches the initial integrity value, the method further includes indicating that the set of encoded data slices is authentic.

Abstract: A crossbar switch comprises two or more data inputs 10, two or more data outputs 100, a buffer 30 between the inputs and the outputs, an arbiter 52 associated with each output and configured to select data from one of the inputs when there is contention at the output, a bypass 32 associated with the buffer so that the buffer can be enabled or disabled, and a buffer controller 60 configured to enable or disable the buffer. The buffer controller further includes an accumulator 70 configured to assess whether a time-based average of the contention rate, or an average injection rate, at the output associated with the buffer, has reached a predetermined threshold. This prevents the buffer being enabled when the contention is only intermittent, which reduces power consumption without significant loss of performance.

Abstract: A memory device and methods for operating the same are provided. The memory device includes an array of memory cells, and a controller configured to receive a data word to be stored at an address in the array and to store, at the address in the array, the data word and a location indicia corresponding to the address. The controller can be further configured to command the array to read the data word from the address, to receive response data from the array, and to verify that a location indicia of the response data corresponds to the address. If the location indicia of the response data does not correspond to the address, the controller can be further configured to indicate an error.

Abstract: A Data Storage Device (DSD) enclosure includes a chassis and at least one backplane mounted in the chassis. According to one aspect, each backplane includes a row of DSD slots and a switch slot located in a middle portion of the row of DSD slots. A plurality of signal traces connect the DSD slots to the switch slot.

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

Abstract: A method, a computing system, and a non-transitory machine readable storage medium containing instructions for managing a stream processing topology are provided. In an example, the method includes receiving a first topology that communicatively couples a plurality of processing elements via a first arrangement of interconnections to perform an operation on a stream of data. A second topology is defined that communicatively couples the plurality of processing elements via a second arrangement of interconnections that is different from the first arrangement. The second topology assigns the plurality of processing elements a first set of operations. The second topology is provided to a stream processing manager and is modified during processing of the stream of data by assigning a second set of operations to the plurality of processing elements that is different from the first set of operations.

Abstract: A method comprising: receiving an I/O request for object data; determining one or more data fragments wherein the object data is stored; determining that one or more of the data fragments are unavailable; determining, from within the one or more unavailable data fragments, a set of slices storing the object data, each slice comprising k small data fragments and m coded fragments; for each slice, retrieving at least k small data and coded fragments within the slice from storage; and recovering a segment of the object data using the retrieved small data and coded fragments. A related system and computer program product are also described.

Abstract: An Open Compute Project (OCP) mezzanine riser with repurposed connectivity to allow for increased PCIe card count on a motherboard server. The OCP mezzanine riser includes at least one OCP connector, where the OCP connectors are mounted on the bottom of the mezzanine riser card and mate with at least one of three OCP connection points that are mounted on a server motherboard. Further, the OCP mezzanine riser includes one or more PCIe lanes mounted on the top of the mezzanine riser card, where a PCIe card may be connected to the one or more PCIe lanes of the mezzanine riser.

Abstract: A data storage device includes a storage medium including a plurality of memory units; and a controller suitable for performing a state determination operation to first memory units in order of a write sequence until a memory unit stored with an error-correction-failed data when a power supply is restored after an abnormal power-off, skipping the state determination operation to second memory units between the memory unit storing the error-correction-failed data and a pointed memory unit, performing the state determination operation to third memory units after the pointed memory unit in order of the write sequence, and performing a garbage collection operation to the first to third memory units based on a result of the state determination operation.

Abstract: Provided herein are a memory system and an operating method thereof. A method of operating a controller for controlling a memory block including a plurality of pages includes determining whether the memory block is in an open state or a closed state, if the memory block is in the open state, reading merged metadata included in the plurality of pages, and rebuilding logical to physical (L2P) mapping data of a plurality of logical pages included in each of the plurality of pages based on the merged metadata.

Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations. For example, the computing device generates and transmits a read request for a set of encoded data slices (EDSs) of a data object to primary storage units (SUs). The data object is stored within primary and secondary SUs. The computing device then receives at least the read threshold number of EDSs from the plurality of primary SUs. The primary SUs operate selectively to provide the at least the read threshold number of EDSs to the computing device either from memory of primary SU(s) or from secondary SU(s).

Abstract: A method for execution by a dispersed storage and task (DST) execution unit includes receiving a request for rebuilding dispersed error encoded data slices and determining a rate for rebuilding the data slices. The method continues by the DST receiving one or more requests for dispersed error encoded data slices not associated with rebuilding and modifying the rate of processing for the one or more requests for dispersed error encoded data slices not associated with rebuilding dispersed error encoded data slices in accordance with the rate for rebuilding dispersed error encoded data slices. When the sending rebuilding dispersed error encoded data slices has concluded the method continues by reverting the rate of processing of requests for dispersed error encoded data slices to the previous rate.

Abstract: A data processing system includes a network of interconnected switch points having a plurality of edge switch points located at an edge of the network; a plurality of network interface controllers, wherein each edge switch point of the plurality of edge points is coupled to a corresponding network interface controller of the plurality of network interface controllers; a plurality of target controllers; and a crossbar switch coupled between the plurality of network interface controllers and the plurality of target controllers. The crossbar switch is configured to communicate read/write signals between any one of the plurality of network interface controllers and any one of the plurality of target controllers.

Abstract: A device securely accesses data in a memory via an addressing unit which provides a memory interface for interfacing to a memory, a core interface for interfacing to a core processor and a first and second security interface. The device includes a security processor HSM for performing at least one security operation on the data and a remapping unit MMAP. The remapping unit enables the security processor to be accessed by the core processor via the first security interface and to access the memory device via the second security interface according to a remapping structure for making accessible processed data based on memory data. The device provides a clear view on encrypted memory data without requiring system memory for storing the clear data.

Abstract: A method includes receiving a plurality of streams of data from a plurality of data sources. During a first time interval of receiving the streams of data, the method further includes dividing each of the plurality of streams into a first time-aligned data segment to produce a set of first time-aligned data segments. The method further includes generating a first data matrix from data blocks of the set of first time-aligned data segments. The method further includes encoding the first data matrix using an encoding matrix to produce a first coded matrix. The method further includes slicing the first coded matrix into a first set of encoded data slices based on the first orientation. The method further includes outputting a first set of encoded data slices of the first coded matrix.

Abstract: A system may comprise a first group of switches, each switch including a first group of inputs and outputs, and a first group of controllers, each controller being independent from one another and corresponding to a switch of the first group of switches, to selectively control the switch to connect the switch's inputs with outputs. The first group of switches and controllers may be installed in a chassis. The system may comprise a second group of switches, each switch including a second group of inputs and outputs, and a second group of controllers, each controller corresponding to a switch of the second group of switches, to selectively control the switch to connect the switch's inputs with outputs. The second group of controllers may control and connect, via a group of control links, to the first group of controllers.

Abstract: A method for generating a high-precision packet train includes configuring an initial packet generation flow of duration T in a network node and sending a packet to a loopback port to initiate the initial packet generation flow in the network node, where the loopback port loops packets back to the network node or recirculates packets within the network node, and where the loopback port is configured for traffic shaping that establishes a pre-determined inter-packet gap for packets output by the loopback port. The method further includes configuring a main packet generation flow having a duration t1 that commences on expiration of the duration T. Looped back packets in the network node are sent to the loopback port for the entirety of durations T and t1, while one copy of each looped back packet in the network node is sent to a network port during the duration t1.