Abstract: There is provided with a software executing device co-operating with a hardware circuit or a hardware simulator, including: a software executing unit configured to execute a software; an execution monitoring unit configured to monitor execution of the software by the software executing unit to sequentially obtain an execution state of the software; a determining unit configured to determine whether the software executing unit and the hardware circuit or the hardware simulator are to be synchronized based on an obtained execution state of the software; and a synchronization controlling unit configured to control synchronization between the software executing unit and the hardware circuit or the hardware simulator.

Abstract: In a communication system, one of a plurality of communication apparatuses that acts as a host controls data transmission and the other communication apparatuses that act as devices perform data transmission under control of the host over a predetermined communication interface. The communication apparatuses have both host and device roles, and are configured to exchange the host and device roles by using a predetermined communication protocol are connected to the predetermined communication interface. A first apparatus acts as a host and a second apparatus as a device. The second apparatus transmits information concerning the second apparatus to the first apparatus. The first apparatus compares the transmitted information with information concerning the first apparatus to determine whether or not to switch the host and device roles according to a predetermined criterion. In response to an affirmative determination, the host and device roles are switched by using the predetermined communication protocol.

Abstract: An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced.

Abstract: A method for enhancing the memory bandwidth available through a memory module of a memory system is provided. The memory system includes a memory hub device integrated in a memory module. The memory system includes a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module. The memory system also includes a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module. In the memory system, the first set of memory devices are separate from the second set of memory devices. In the memory system, the first and second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces.

Abstract: Embodiments of the present invention provide a system that transfers data between the components in the computer system through a switch. In these embodiments, the switch includes multiple switch chips which are coupled together and are configured to collectively function as a switch. During operation, each switch chip, receives cells from the subset of the set of inputs and selectively transfers each of the cells to at least one output of the subset of the set of outputs coupled to the switch chip or of the subset of the set of outputs coupled to the other switch chips.

Abstract: A multi-port memory, comprising: m (m?2) input/output ports independent of one another; n (n?2) memory banks independent of one another; and a route switching circuit capable of optionally setting signal routes of a command, an address, and input/output data between the m input/output ports and the n memory banks, wherein the route switching circuit allocates p (1?p?m) input/output ports optionally selected from the m input/output ports to a memory bank optionally selected from the n memory banks.

Abstract: A processor local bus bridge for a processor block ASIC core for embedding in an IC is described. A core logic-to-core logic bridge includes a slave processor local bus interface, a crossbar switch coupled to the slave processor local bus interface and a master processor local bus interface coupled to the crossbar switch. The slave processor local bus interface and the master processor local bus interface are coupled to one another via the crossbar switch for bidirectional communication between a first and a second portion of core logic. The bridge provides rate adaptation for bridging for use of a frequency of operation associated with the crossbar switch which has substantially greater frequencies of operation than those associated with the core logic sides of the master and slave processor local bus interfaces.

Abstract: A cross bar multipath resource controller system and method permit multiple processors in a computer system to access various resource of the computer system, such as memory or peripherals, with zero blocking access. In particular, each processor has its own bus so that the processors can each independently access different resources in the computer system simultaneously.

Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

Abstract: A master device sends a request to communicate with a slave device to a switch. The master device waits for a period of cycles the switch takes to decide whether the master device can communicate with the slave device, and the master device sends data associated with the request to communicate at least after the period of cycles has passed since the master device sent the request to communicate to the switch without waiting to receive an acknowledgment from the switch that the master device can communicate with the slave device.

Abstract: Crossbar circuitry has an array of data input and output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided which includes a configuration storage circuit programmable to store a routing value, a transmission circuit, and an arbitration circuit. In a transmission mode of operation, the transmission circuit is responsive to the routing value being a first value, indicating that the data input path should be coupled to the data output path, to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection. In an arbitration mode of operation, the arbitration circuitry is operable to selectively modify the voltage on said plurality of bit lines in order to apply an adaptive priority scheme.

Abstract: According to an aspect of the embodiment, an input/output device transmits a message to a first node controller of a parent node which is set in advance via a cross bar. At this point, the cross bar generates information based on node information of the input/output device, and adds the generated information to the message. The first node controller transmits, via the cross bar, the message to a second node controller of a parent node corresponding to an input/output device that is to receive the message. The second node controller transmits, via the cross bar, the message to an input/output device that is to receive the message. At this point, the cross bar transmits the message restored by deleting the generated information from the message to the input/output device which is set as a destination.

Abstract: Cross-bar segment routing and access table address remapping functions are combined within a cross-bar of a system-on-a-chip. In this manner, address remapping may occur prior to segment routing. One or more access table caching registers may be included for each master port. The caching registers may allow for a rapid lookup of one or more access table entries associated with each master, as well as allow for the simultaneous lookup by multiple masters without adding ports to the access table. A segment identifier may be stored in the caching registers to indicate how to route a matching request to the appropriate slave segment.

Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

Abstract: A cluster internal routing network for use in a programmable logic device with a cluster-based architecture employs a Clos network-based routing architecture. The routing architecture is a multi-stage blocking architecture, where the number of inputs to the first stage exceeds the number of outputs from the first stage.

Abstract: Embodiments of the present invention provide a system that transfers data between the components in the computer system through a switch. In these embodiments, the switch includes multiple switch chips which are coupled together and are configured to collectively function as a switch. During operation, each switch chip, receives cells from the subset of the set of inputs and selectively transfers each of the cells to at least one output of the subset of the set of outputs coupled to the switch chip or of the subset of the set of outputs coupled to the other switch chips.

Abstract: The invention sets forth an L1 cache architecture that includes a crossbar unit configured to transmit data associated with both read data requests and write data requests. Data associated with read data requests is retrieved from a cache memory and transmitted to the client subsystems. Similarly, data associated with write data requests is transmitted from the client subsystems to the cache memory. To allow for the transmission of both read and write data on the crossbar unit, an arbiter is configured to schedule the crossbar unit transmissions as well and arbitrate between data requests received from the client subsystems.

Abstract: The invention sets forth a crossbar unit that includes multiple virtual channels, each virtual channel being a logical flow of data within the crossbar unit. Arbitration logic coupled to source client subsystems is configured to select a virtual channel for transmitting a data request or a data packet to a destination client subsystem based on the type of the source client subsystem and/or the type of data request. Higher priority traffic is transmitted over virtual channels that are configured to transmit data without causing deadlocks and/or stalls. Lower priority traffic is transmitted over virtual channels that can be stalled.

Abstract: When a new data relaying device that has yet to have configuration information set therein is incorporated, the configuration information of an existing data relaying device is copied to the new data relaying device.

Abstract: Methods and systems for performing direct memory access (DMA) transfers are described. An invalidate queue (or other storage device) contains an entry associated with a DMA transfer in progress. If the invalidate queue detects an invalidation of a memory page associated with that entry, then it is marked invalid. If the entry is marked invalid during the DMA transfer, then that DMA transfer is aborted. This enables, among other things, DMA transfers to unpinned virtual memory.

Abstract: A system and method for single hop, processor-to-processor communication in a multiprocessing system over a plurality of crossbars are disclosed. Briefly described, one embodiment is a multiprocessing system comprising a plurality of processors having a plurality of high-bandwidth point-to-point links; a plurality of processor clusters, each processor cluster having a predefined number of the processors residing therein; and a plurality of crossbars, one of the crossbars coupling each of the processors of one of the plurality of processor clusters to each of the processors of another of the plurality of processor clusters, such that all processors are coupled to each of the other processors, and such that the number of crossbars is equal to [X*(X?1)/2], wherein X equals the number of processor clusters.

Abstract: Various embodiments of the disclosure provide systems, methods and circuits for implementation and use of a memory system. As one example, a memory system is disclosed that includes a plurality of memory devices and a configuration circuit. The configuration circuit includes at least one input, a plurality of outputs, and a programmable control circuit. The plurality of outputs are communicably coupled to the plurality of memory devices, and the programmable control circuit is operable to selectably couple the input to at least one of the plurality of outputs.

Abstract: A backplane arrangement 200; 500 and method for distributing network connections in said backplane arrangement 200; 500 comprising a number of board positions Ac-Fc; Gc-Kc each arranged to operatively receive a board Ab-Fb; Gb-Kb, and a backplane-network arrangement 250, 300; 550, 600, 600? arranged to operatively make a plurality of network connections a-n; a-g available at a first board position Ac; Gc. The backplane arrangement 200; 500 is characterized in f/?af a first allocation arrangement Aen1-Aen14; Gen8-Gen14 is arranged to operatively allocate a set of the available network connections a-n; a-g to be used by a board Ab received in the first board position Ac; Gc; and a first bypass arrangement Ap; Aps; Aps'; Gp is arranged to operatively bypass a set of the available network connections b-n; b-g unallocated at the first board position Ac; Gc to a second subsequent board position Bc; Hc via the backplane-network arrangement 250; 550.

Abstract: A connection device for selecting an optimum receiver includes a single first port, in which a transmitter is connected via a bidirectional type cable, and a plurality of second ports, in which a plurality of receivers are connected via respective bidirectional type cables. The connection device further includes a transmission control unit which acquires transmitter function information from the transmitter via the first port as well as acquiring receiver function information from each of the plurality of receivers via their respective second ports. A transmission control unit links together the first port and the respective second port from among the plurality of second ports, which is connected to the receiver which is endowed with receiver function information closest to the transmitter function information.

Abstract: A computer system comprises a computer that includes a plurality of CPU sockets including one or more CPU cores, a crossbar switch, and a memory controller each, and memories connected under the respective plurality of CPU sockets, the plurality of CPU sockets being connected to each other. When all the CPU cores in a CPU socket enter a power saving state and a total amount of memory use falls below a predetermined threshold, the computer relocates contents of the memory connected under the CPU socket to a memory under another CPU socket, thereby eliminating an access to the memory connected under the CPU socket and bringing a whole of the CPU socket into the power saving state.

Abstract: Methods and apparatus are provided for efficiently and intelligently communicating characteristic information in video graphics switcher environments. An intelligent video graphics switcher obtains display device characteristic information associated with multiple display devices and maintains updated characteristic information. When an event such as a connection/disconnection or switching event occurs between the video graphics switcher and a display device, the characteristic information is communicated to an appropriate host by triggering a connection/disconnection event with the host.

Abstract: In a communication system, one of a plurality of communication apparatuses that acts as a host controls data transmission and the other communication apparatuses that act as devices perform data transmission under control of the host over a predetermined communication interface. The communication apparatuses have both host and device roles, and are configured to exchange the host and device roles by using a predetermined communication protocol are connected to the predetermined communication interface. A first apparatus acts as a host and a second apparatus as a device. The second apparatus transmits information concerning the second apparatus to the first apparatus. The first apparatus compares the transmitted information with information concerning the first apparatus to determine whether or not to switch the host and device roles according to a predetermined criterion. In response to an affirmative determination, the host and device roles are switched by using the predetermined communication protocol.

Abstract: A network system includes a crossbar switch, and a plurality of crossbar interfaces having ports connected to the crossbar switch. A bypass route directly connects crossbar interfaces forming a group in which a frequency of use of the ports is greater than or equal to a predetermined value amongst the plurality of crossbar interfaces.

Abstract: A method includes identifying a first set of masters and a second set of masters from a plurality of masters. The plurality of masters have access to a multi-channel memory via a crossbar interconnect. The method includes partitioning the crossbar interconnect into a plurality of partitions comprising at least a first partition corresponding to the first set of masters and a second partition corresponding to the second set of masters. The method also includes allocating a first set of buffer areas within the multi-channel memory. The first set of buffer areas correspond to the first set of masters. The method further includes allocating a second set of buffer areas within the multi-channel memory. The second set of buffers correspond to the second set of masters.

Abstract: A USB printer sharing switch device with automatic switching capabilities is provided for multiple computers to share a USB printer. The sharing switch device transfers USB data between the computers and the printer without changing the data format. The automatic switching function is performed by hardware and firmware of the sharing switch device in cooperation with driver software on the computers. In one implementation, the sharing switch device includes multiple USB device controllers corresponding to the multiple computers, and employs multiple switches and a USB hub so that each computer is connected to its corresponding controller and the computer that is currently connected to the printer can communicate with its controller while printing. The current computer transmits a spooling finished command to its controller when spooling is finished. After receiving the spooling finished command, the sharing switch device automatically switches the printer to another computer.

Abstract: A multiprocessor computer system includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each node controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input/output port, a network port, and a plurality of independent processor ports. A first and a second processor port is connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. The memory port includes a memory data port including a memory data bus and a memory address bus coupled to the first subset of memory chips, and a directory data port including a directory data bus and a directory address bus coupled to the second subset of memory chips.

Abstract: Cross bar control circuits are connected to each other by two buses, which are a broadcast bus for transmitting a broadcast packet from a system board to all system boards other than the system board and a point-to-point bus for transmitting a unicast packet from a system board to another system board. When unicast packets passing through the point-to-point bus are too many, the unicast packets are output by using the broadcast bus in addition to the point-to-point bus if the broadcast bus is not used. In this way, the unicast packets can be output quickly and efficiently, so that use efficiency of the broadcast bus and the point-to-point bus can be increased as a whole.

Abstract: A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces.

Abstract: A processor is provided. The processor includes at least two cores. The at least two cores have a first level cache memory and are multi-threaded. A crossbar is included. A plurality of cache bank memories in communication with the at least two cores through the crossbar is provided. Each of the plurality of cache bank memories communicates with a main memory interface. A plurality of input/output interface modules in communication with the main memory interface and providing a link to the at least two cores are included. The link bypasses the plurality of cache bank memories and the crossbar. Threading hardware configured to enable the at least two cores to switch from a first thread to a second thread in a manner hiding delays caused by cache accesses is included. A server and a method for determining when to switch threads in a multi-core multi-thread environment are included.

Abstract: Streaming data is processed through one or more pipes of connected modules including mixers and/or splitters. The data is carried in composite physically allocated frames having virtual subframes associated with different ones of the splitters, mixers, and other transform modules. Nesting trees and pipe control tables represent the structure of the pipes. A frame allocator is assigned to a particular module in a pipe. Rather than issuing a control transaction to all modules when any one of them completes an operation upon its source data, a control manager requests a module to begin its operation only when all of its input subframes have become available. Frame control tables record when any module has completed an operation, and a pipe control table lists which modules provide data to which other modules.

Abstract: A system and method for routing packets from one node to another node in a system having a plurality of nodes connected by a network. A node router is provided in each node, wherein the node router includes a plurality of network ports, including a first and a second network port, wherein each network port includes a communications channel for communicating with one of the other network nodes, a plurality of virtual channel input buffers and a plurality of virtual channel staging buffers, wherein each of the virtual channel staging buffers receives data from one of the plurality of input buffers.

Abstract: An extension to the Universal Serial Bus (USB) protocol that utilizes reserved bits in the OHCI Endpoint Descriptors to signal which root hub port(s) should transmit the data. Typically, all ports transmit (broadcast) data. The present invention encodes transmission information that can be used by the hardware to effectively control which port(s) need to be tri-stated. However, by setting, the “on” bits for all the ports, the present invention retains standard USB functionality. Also provided is a method to increase the bandwidth of low speed devices connected to the USB bus by increasing the data payload for such devices.

Abstract: Access is provided to user registers of a user design implemented on an integrated circuit (IC). A memory of the IC is initialized with instructions, and a portion of the programmable logic and interconnect resources of the IC is configured to implement an access interface, multiplexer logic, and the user design. A processor is coupled to the programmable logic and interconnect resources and executes the instructions from the memory. The processor receives from an external user interface, via the access interface, an access command. For a read command, the processor reads a value from an identified user register and transmits the value to the external user interface. For a write command, the processor writes a write value specified by the access command to the specified user register via the multiplexer logic. The processor and the user design are both coupled to write to the user registers via the multiplexer logic.

Abstract: In an LSI system using an on-chip bus, when a transfer on the bus is delayed due to a fully loaded buffer in a destination module, a source module cannot proceed to the next processing. Such an unwanted situation is eliminated by plural transferring buffers which are provided in an on-chip bus on the LSI for temporarily storing transfer data. With the transferring buffers, even if a buffer within a slave module, specified as the destination, is fully loaded and cannot accept any more transfer, a bus master can transfer data to a transferring buffer provided on the on-chip bus. Thus, the bus master is not kept waiting for execution of a transfer, irrespective of the state of the buffer within the slave. With the provision of plural transferring buffers, input/output operations can be performed in parallel.

Abstract: An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits.

Abstract: A system and method are disclosed for crossbar switching in an emulation environment. The switch is designed to coordinate scheduling between different crossbars in the system and to be dynamically reconfigurable during operation. In one aspect, a crossbar switch includes a switching matrix and an array of control cells. The control cells use a high-frequency clock to perform high-speed switching and a low-frequency clock in order to initiate a switching sequence. The low-frequency clock initiates the sequence at a time coordinated with other crossbars in the system to optimize scheduling. In another aspect, the control cells include a memory containing control bits for the switching matrix. The memory may be reconfigured without stopping traffic management through the crossbar switch. In yet another aspect, the high-frequency sequence may provide for the ability to loop.

Abstract: A method and apparatus includes identifying an address portion of a first message in an address slice of a switch, the first message associated with a first priority, the address portion of the first message including a first routing portion specifying a network resource; identifying an address portion of a second message in the address slice, the second message associated with a second priority, the address portion of the second message including a second routing portion specifying the same network resource; identifying a non-address portion of the first message in a non-address slice of the switch; identifying a non-address portion of the second message in the non-address slice, wherein neither of the non-address portions includes a routing portion specifying the network resource; selecting, independently in each slice, the same one of the first and second messages based on the first and second priorities; transferring the address portion of the selected message to the network resource specified by the rout

Abstract: A shared memory is described having a plurality of receive ports and a plurality of transmit ports characterized by a first data rate. A memory includes a plurality of memory banks organized in rows and columns. Operation of the memory array is characterized by a second data rate. Non-blocking receive crossbar circuitry is operable to connect any of the receive ports with any of the memory banks. Non-blocking transmit crossbar circuitry is operable to connect any of the memory banks with any of the transmit ports. Buffering is operable to decouple operation of the receive and transmit ports at the first data rate from operation of the memory array at the second data rate. Scheduling circuitry is operable to control interaction of the ports, crossbar circuitry, and memory array to effect storage and retrieval of the data segments in the shared memory.

Abstract: A communication apparatus is disclosed that includes a transmission circuit configured to transmit transmission data to a communication counterpart; a reception circuit configured to receive reception data from the communication counterpart; a storage device configured as at least two buffers including a transmission buffer that stores the transmission data and a reception buffer that stores the reception data; and an address mapping unit configured to perform address mapping of the buffers including the transmission buffer and the reception buffer on the storage device, and adjust the storage capacity of the transmission buffer and the storage capacity of the reception buffer.

Abstract: Methods and apparatus are provided optimizing system memory map decoder logic. A system is configured with multiple master and slave components. Using information known about the system configuration, optimized decoder logic can be configured. Critical path delay and system resource usage are reduced by optimizing decoder logic.

Abstract: The present invention describes a flexible routing scheme between masters and slaves in complex digital systems. The routing scheme is optimized for maximum versatility and configurability using switched resources in the form of configurable crossbar switches.

Abstract: A process for configuring rendezvous points in switch routers of a PIM-SM network that includes static rendezvous point configuration and bootstrap router protocol messaging. A user will input static rendezvous point commands into one of the routers in the network that identifies the rendezvous points for all of the group ranges in the network. The rendezvous commands will include instructions for the router to transmit the static rendezvous point configuration to the other routers using BSR protocol messages, where the messages are designated as special BSR messages.

Abstract: An apparatus connected to a first and second buses, the apparatus having a first controller that transforms first form data into second form data, transforms second form data into first form data, and outputs the transformed data, a second controller that transforms first form data into second form data, transforms second form data into first form data, and outputs the transformed data, a first distributing unit connected to the first and second controllers, the first distributing unit distributing first form data to the first and second controllers, respectively, a first selector that selects one of the second form data, and outputs the selected data, a second distributing unit connected to the first and the second controllers, the second distributing unit distributing second form data to the first and second controllers, respectively, and a second selector that selects one of the first form data, and outputs the selected data

Abstract: Systems and methods for improving performance of a rentable fabric are disclosed. In an exemplary embodiment a system may comprise a plurality of compute nodes, a routable fabric, and a plurality of chipsets connected by the routable fabric to the plurality of compute nodes. The chipsets have range registers dynamically directing traffic from any device to any of the plurality of compute nodes over the routable fabric.

Abstract: Crossbar circuitry, and a method of operation of such crossbar circuitry, are provided. The crossbar circuitry has an array of data input paths and data output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided that comprises a storage circuit programmable to store a routing value, and a transmission circuit. In a transmission mode of operation the transmission circuit is responsive to the routing value indicating that the data input path should be coupled to the data output path to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection. Control circuitry is used to issue control signals to the crossbar cells, and during a configuration mode of operation the control circuitry re-utilises at least one of the data output paths to program the storage circuitry of one or more of the crossbar cells.