Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

Abstract: Techniques for facilitating communication between a portable media device (PMD) and an accessory via multiple communication paths. The accessory has a unique accessory identifier that it can send to the PMD upon establishing a connection via each communication path. The PMD can determine whether the same accessory is connected via multiple communication paths based on the accessory identifier received via each communication path. The PMD can route information to the accessory and control routing of information from the accessory based on the set of communication paths that are currently connected and can dynamically change the routing as communication paths are connected and disconnected.

Abstract: An information processing system includes: CPUs; storage devices; switches; dummy storage devices which are with respective storage devices and each of which sends, when receiving an identifying information request, its own identifying information back to a sender of the identifying information request; and dummy CPUs which are associated with respective CPUs and each of which tries to, when receiving an instruction for acquiring identifying information from a dummy storage device, acquire the identifying information of the dummy storage device by transmitting the identifying information request, and sends the identifying information as response information back to a sender device of the acquiring instruction.

Abstract: According to one embodiment, a first controller is connected to one of a plurality of terminals. A detector is configured to detect a connection between each of the plurality of terminals and an MHL cable. A power supply module supplies electric power to a first connected apparatus connected via a first MHL cable in response to a first connection detection between a first terminal and the first MHL cable. A second controller is configured to connect the first terminal and the first controller, in response to the first connection detection, and to connect a second terminal and the first controller, when a signal is not received from the first connected apparatus via the first terminal at a timing of a second connection detection between the second terminal and a second MHL cable.

Abstract: A protocol controller disposed between switches in a fiber channel fabric switch circuit and disk drive units for converting a protocol to enable one-to-one connectivity established between controllers and disk drive units.

Abstract: Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit (“LSB”) and most significant bit (“MSB”) ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide.

Abstract: An interface device for a cabin monument, in particular for assembly in an aircraft or spacecraft, including a routing device, a first plurality of interface connection sockets, which are connected to the routing device via a first plurality of connection lines and to which a vehicle interface of the aircraft or spacecraft can be connected. A second plurality of interface connection sockets are provided which are connected to the routing device via a second plurality of connection lines and to which a cabin monument can be connected. The routing device is constructed so as to selectively electrically connect interface connection sockets of the first plurality of interface connection sockets to interface connection sockets of the second plurality of interface connection sockets.

Abstract: Techniques for performing I/O load balancing are provided. In one embodiment, a computer system can receive an I/O request destined for a storage array, where the computer system is communicatively coupled with the storage array via a plurality of paths, and where the plurality of paths include a set of optimized paths and a set of unoptimized paths. The computer system can further determine whether the I/O request can be transmitted to the storage array via either an optimized path or an unoptimized path, or solely via an optimized path. The computer system can then select a path in the plurality of paths based on the determination and transmit the I/O request to the storage array via the selected path.

Abstract: A storage system and method for setting parameters and determining latency in a chained device system. Storage nodes store information and the storage nodes are organized in a daisy chained network. At least one of one of the storage nodes includes an upstream communication buffer. Flow of information to the storage nodes is based upon constraints of the communication buffer within the storage nodes. In one embodiment, communication between the master controller and the plurality storage nodes has a determined maximum latency.

Abstract: Described is a data switching device comprising a plurality of input ports, a plurality of output ports, a plurality of first conductive connectors, a plurality of second conductive connectors, a plurality of crosspoint regions, and a memory device at each crosspoint region. The first conductive connectors are in communication with the input ports. The second conductive connectors are in communication with the output ports. Each crosspoint region includes a first conductive connector and a second conductive connector. The memory device is coupled between the first conductive connector and the second conductive connector for exchanging data between the input ports and the output ports.

Abstract: Described is an integrated circuit (IC) that allows for communication between any input/output (I/O) pin and onboard peripherals. Accordingly, the resultant IC can be easily documented and connections between I/O pins and peripherals can be managed for each peripheral independently. The IC may include one or more sets of hardwired connections that provide a connection between of any I/O pin and any onboard peripheral. The hardwired connections may include the use of one or more crossbars. This increases the overall functionality and potential applications for an IC as the only limitation on peripheral connectivity is the number of I/O pins.

Abstract: In one embodiment, a fulfillment request is received. A solution set comprising a plurality of fulfillment solutions is determined. The solution set, including values for fulfillment solutions according to a plurality of negotiation attributes, is presented. Selection of a negotiation attribute to be prioritized is invited. The solution set is redetermined according to a selected negotiation attribute. A redetermined solution set is presented. The fulfillment request is fulfilled according to a solution selected from the redetermined solution set.

Abstract: A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

Abstract: Embodiments of the present invention provide an approach for a networked computing environment (e.g., a cloud computing environment) to be dynamic in nature in that it may automatically be resized based on current/predicted workload and current/predicted resource availability. For example, when a workload is received, a data structure (e.g., a mapping) will be created on a computer storage device and populated with data related to a set of current resources of the networked computing environment that are allocated to the workload. It will then be determined whether a mismatch (e.g., a shortfall) exists between the set of current resources and resources required for processing the workload. If so, a set of peripheral resources will be identified to rectify the mismatch. The networked computing environment will then be resized to accommodate the set of peripheral resources, and the workload will be processed using the resized networked computing environment.

Abstract: A SAS expander configured to operate as a SAS expander hub receives IO requests from a plurality of connected SAS expanders. Each SAS expander determines if it is capable of servicing a received IO request and sending such IO requests to the SAS expander hub if necessary. The SAS expander hub relays the IO requests to SAS expanders connected to data storage devices capable of servicing such IO requests.

Abstract: A host I/F unit has a management table for managing an MPPK which is in-charge of the control of input/output processing for a storage area of an LDEV, and if a host computer transmits an input/output request for the LDEV, the host I/F unit transfers the input/output request to the MPPK which is in-charge of the input/output processing for the LDEV based on the management table, an MP of the MPPK performs the input/output processing based on the input/output request, and the MP of the MPPK also judges whether the MPPK that is in-charge of the input/output processing for the LDEV is to be changed, and sets the management table so that an MPPK which is different from the MPPK that is in-charge is to be in-charge of the input/output processing for the LDEV.

Abstract: A data processing device includes a plurality of devices, a processor core, a memory, and a queue manager. The processor core stores one or more commands in a command queue of the memory to be executed by the plurality of devices to implement a data transfer path. The queue manager stores a frame queue for each of the plurality of devices. Each frame queue includes a first field having a pointer to an address of the command queue, and a second field to identify a next-in-sequence frame queue. A first device stores a data descriptor in the frame queue of the second device to initiate a data transfer from the first device to the second device. The data descriptor includes a field to indicate an offset value from the address of the command queue to a location of a command to be executed by the second device.

Abstract: A power consumption of a semiconductor integrated circuit is reduced. A semiconductor integrated circuit comprises a first path P1 for performing data processing in a data processing circuit and a second path P2 for bypassing the data processing circuit or for performing data processing in a simplified circuit. The semiconductor integrated circuit exclusively selects the first path and the second path depending on an operational mode, and stops a data input into a path that is not selected, resulting in a reduction of the power consumption.

Abstract: An IOP 14 includes a path-state determining unit 54 and a path selecting unit 55. The path-state determining unit 54 determines whether there is any path which is neither in process of data transmission nor in a prohibition period in which data transmission is prohibited for a predetermined time since the last data transmission has been completed out of multiple paths connecting a device to a communication partner device. When the path-state determining unit 54 determines that there is no path which is neither in process of data transmission nor in the prohibition period, the path selecting unit 55 selects a path which completes data transmission but does not pass through the prohibition period as a path for data transmission.

Abstract: A method for replacing logical path resources, a host is able to replace a logical path it owns with a new logical path. Such a system is especially applicable when the condition of “out of resources” has been reached for a port. With this system, a host is guaranteed that it can replace a logical path it owns with a new logical path. It is not necessary for a control unit to have reached its maximum number of logical paths per port. A host is able to replace one logical path with a new logical path any time.

Abstract: A hub device includes an upstream port, multiple downstream ports, a first and a second sub-hub module, a data-format detector, a transaction translator, and a controller. The upstream port is coupled to a host device supporting a first and/or a second data format. Each downstream port is coupled to one of a plurality of slave devices supporting a first and/or a second data format. The first sub-hub module supports transmission of data in the first data format. The second sub-hub module supports transmission of data in the second data format. The data-format detector detects the data format supported by the host device and the slave devices. The transaction translator transforms the data format between the first data format and the second data format. The controller determines whether to control the transaction translator to perform data-format transformation.

Abstract: Methods and apparatus for reducing power consumption in a host bus adapter (HBA) are provided. The methods include reducing a number of active lanes in an HBA link when link traffic is low, and increasing the number of active lanes when link traffic is high.

Abstract: Described embodiments provide a method and user equipment for controlling a plurality of coupled external devices. The method may include determining whether one of applications installed in user equipment is activated upon receipt of a user input when the user equipment is coupled to a plurality of external devices, selecting one of the coupled external devices as a target external device to be mapped, when the application is determined as being activated, and mapping the selected coupled external device with the activated application and establishing a signal route between the user equipment and the selected coupled external device in association with the activated application.

Abstract: In one aspect of the present description, in an input/output (I/O) device having multiple CPUs and multiple I/O ports, a cycle of I/O port rotations is initiated in which each port rotation of the cycle includes rotating an assignment of at least one I/O port from one CPU to a different CPU of a plurality of the CPUs. In the illustrated embodiment, an I/O port assignment for each CPU of the plurality CPUs is rotated for at least a portion of the cycle. Other features and aspects may be realized, depending upon the particular application.

Abstract: Methods and apparatus for dispatching memory operations are disclosed. An example memory controller for controlling operation of a data storage device includes a command dispatcher that dispatches memory operation commands for execution by a plurality of memory devices. The command dispatcher includes a command buffer that separately and respectively queues the memory operation commands by maintaining a respective linked list of memory operation commands for each memory device. The command dispatcher also includes a selection circuit with a plurality of leaf nodes. Each leaf node corresponds with one of the linked lists and indicates whether its corresponding linked list includes memory operation commands awaiting dispatch. The selection circuit also includes an OR-reduction tree that reduces the plurality of leaf node indications to a root node indication. The selection circuit iterates over the nodes of the OR-reduction tree to select memory operation commands for dispatch by the command dispatcher.

Abstract: A management method is provided, suitable for an electronic system having electronic devices connected in a daisy-chain configuration. The management method comprises the steps of: the electronic devices are sequentially connected with a host, thereby obtaining universal unique identifiers corresponding to the electronic devices; serial numbers corresponding to the electronic devices are generated according to a first order of obtainment of the universal unique identifiers of the electronic devices; and the host communicates with the electronic devices according to the serial numbers.

Abstract: An embodiment of a method of managing multipathing in a computer system including the steps of establishing a plurality of concurrent multipathing processes on the computer system; disassociating a plurality of operational data paths from a first of the multipathing processes; and associating the operational data paths with a second of the multipathing processes.

Abstract: A method of assigning resources to an input/output adapter having multiple ports may include determining a first port of the input/output adapter that includes a first bandwidth availability. A first number of resources assigned to the first port may be modified. The method may further include comparing a total count of resources assigned the ports to a maximum number of resources, where the total count includes the modified first number of resources. At least a portion of the modified first number of resources to the first port may be allocated to the first port.

Abstract: First and third current paths are connected at mutual one end, and second and fourth current paths are connected at mutual one end. A transmitter sends signals utilizing the change of a current by changing the current flowing between other ends of the first and second current paths. A switching part brings about a non-conductive state between the other end of the third current path and the other end of the fourth current path by being applied with a control signal from a controller. By contrast with this, the switching part brings about a conductive state between the other end of the third current path and the other end of the fourth current path by not being applied the control signal.

Abstract: A given port at a storage controller is used for communication with storage devices. In response to an indication that at least a portion of the given port is to be dedicated to a group of at least one of the storage devices, the storage controller divides the given port into multiple smaller ports.

Abstract: A method of extending a standard primitive in a data storage fabric is disclosed. A group of primitives are combined into a sequence including the standard primitive and a variable information primitive. The variable information primitive includes data particular to a broadcast of the sequence. The sequence is broadcast through the data storage fabric.

Abstract: Disclosed is a method of managing a connection with a device for a wireless communication-based Wireless universal Serial Bus (WSB) service in a host, including controlling to create an initial channel to connect to a target device for a WSB service, considering a device class of the target device, and configured to create a new channel to substitute for the initial channel considering a particular service, at a user's request, to provide the particular service through association with the target device.

Abstract: A computer system includes a server using a virtual volume (virtual logical volume) shared by a plurality of storage apparatuses. A management system managing the computer system accepts a selection of a first storage apparatus to be a determination target from among the storage apparatuses, performs a first determination of whether a first access path including the first storage apparatus exists or not. If the first access path exists, the management system performs a second determination of whether or not the first access path is an active access path used by the server for accessing the storage area (the storage area of the storage apparatus) assigned to a part of the virtual volume used by the server, and determines whether the first storage apparatus can be stopped or not on the basis of a result of the first determination or a result of the second determination. The access path is a path from the server to one of the storage apparatuses.

Abstract: Each communication path between controllers and a plurality of storage devices has a plurality of expanders coupled in series. In order to shorten the time during which the communication path is not used for I/O, either (A) the length of time for which I/O suppression is set for the communication path is shortened, or (B) the overall time it takes for processing other than I/O processing is shortened. In the (A), a determination as to whether or not the coupling between the expanders has been disconnected is made for the I/O-suppressed communication path, and in a case where the result of this determination is negative, a discover process is carried out after releasing the I/O suppression with respect to this communication path. In the (B), the number of command issue times of updating routing control information of the expander is reduced.

Abstract: An access method includes: obtaining, by a computer, a result of monitoring a busy rate and a number of access operations per unit time of a storage device, the storage device having a first storage area and a second storage area; calculating a characteristic of correlation between the busy rate and the number of access operations per unit time based on the result; calculating a second number of access operations per unit time based on the characteristic of the correlation such that a sum of a first busy rate corresponding to a first number of access operations per unit time and a second busy rate corresponding to a second number of access operations per unit time becomes equal to or lower than a given busy rate; and controlling a number of operations to access the second storage area per unit time based on the second number of access operations.

Abstract: To enable signal transmission at a high data rate while securing backward compatibility. A source device 110 and a sink device 120 are connected by an HDMI cable 200. The source device 110 is compatible with both current HDMI and new HDMI. The number of differential signal channels for transmitting digital signals such as video data is three in the current HDMI, but is six in the new HDMI, for example. In a case where the cable 200 is compatible with the new HDMI, and the sink device 120 is compatible with the new HDMI, a control unit 113 of the source device 110 controls a data transmitting unit 112 to operate in a new HDMI operating mode. In a case where the control unit 113 determines that at least the sink device 120 is compatible only with the current HDMI, or at least the cable 200 is compatible with the current HDMI, the control unit 113 controls the data transmitting unit 112 to operate in a current HDMI operating mode.

Abstract: An I2C system comprises an inter-integrated circuit (I2C) master device coupled to an I2C multiplexer via a master I2C bus. A plurality of slave I2C busses emanating from the I2C multiplexer couple the I2C multiplexer to a plurality of I2C slave devices. Each of the slave I2C busses comprises a serial data (SDA) line and serial clock (SCL) line. Each of the slave I2C busses, which is coupled to two I2C slave devices, has a first channel and a second channel. The first channel puts bidirectional serial data on the SDA line and clock signals on the SCL line, and the second channel puts bidirectional serial data on the SCL line and clock signals on the SDA line. A channel selector, associated with the I2C multiplexer, selectively couples the I2C master device to one of the two I2C slave devices via the first channel or the second channel.

Abstract: According to an aspect of the invention, a computer comprises a memory; and a processor operable to manage a plurality of path groups, each of which includes a plurality of logical paths associated with a host computer, wherein each logical path of the plurality of logical paths connects the host computer to a logical volume of one or more logical volumes in one or more storage systems. The processor is operable to manage a priority of each path group of the plurality of path groups, and to use a logical path of a first path group instead of a logical path of a second path group for I/O (input/output) usage between the host computer and the one or more storage systems, representing a migration of I/O usage from the second path group to the first path group, based on at least the priorities of the first and second path groups.

Abstract: An example method and system process a SuperSpeed packet transferred at a SuperSpeed transfer rate and based on processing the SuperSpeed packet, generate a Universal Serial Bus (USB) 2.0 packet to be transferred at a USB 2.0 transfer rate, the USB 2.0 transfer rate being less than the SuperSpeed transfer rate.

Abstract: A host computer accesses a federated storage volume at first and second frames (physical storage assemblies). The host identifies a preferred frame by (1) obtaining representative values of a performance metric for sets of paths to the volume, each set associated with a different frame, and (2) selecting the frame associated with the path set having the best representative value. In one example a response latency is used to detect different distances to the host and identify the closer frame, which will be preferred. Operating modes of the paths for non-preferred frames are set to “standby”. During subsequent operation using path selection to send storage operations to the volume, the host selects among paths in an “active” operating mode so as to access the volume at the preferred frame under normal operating condition. Standby paths are reserved for less normal operating conditions, such as when no active path is available.

Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

Abstract: One data processor is provided with an interface for realizing connection with the other data processor. This interface is provided with a function for connecting the other data processor as a bus master to an internal bus of the one data processor, and the relevant other data processor is capable of directly operating peripheral functions that are memory mapped to the internal bus from an external side via the interface. Accordingly, the data processor can utilize the peripheral functions of the other data processor without interruption of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor.

Abstract: Techniques for performing I/O load balancing are provided. In one embodiment, a computer system can receive an I/O request destined for a storage array, where the computer system is communicatively coupled with the storage array via a plurality of paths, and where the plurality of paths include a set of optimized paths and a set of unoptimized paths. The computer system can further determine whether the I/O request can be transmitted to the storage array via either an optimized path or an unoptimized path, or solely via an optimized path. The computer system can then select a path in the plurality of paths based on the determination and transmit the I/O request to the storage array via the selected path.

Abstract: An apparatus includes at least one first input/output (I/O) module having multiple first I/O channels. Each first I/O channel is configured to provide a communication path. The apparatus also includes a second I/O module having multiple second I/O channels. Each second I/O channel is configured to provide a redundant communication path for one of the first I/O channels. The apparatus is configured to provide the redundant communication paths for only a subset of the first I/O channels. The first I/O channels may include critical I/O channels and non-critical I/O channels, and the apparatus may be configured to provide the redundant communication paths for only the critical I/O channels. The apparatus can be configured to provide the redundant communication paths for the first I/O channels of a single first I/O module or multiple first I/O modules.

Abstract: An input/output module for use in an industrial control system and connectable to a programmable logic controller (PLC), the input/output module having an interface configured for an electrical connection to the PLC, a plurality of pins configured for connection to one of a plurality of peripherals, an application specific integrated circuit (ASIC) disposed in the I/O module and electrically coupled to a system controller, the ASIC having a plurality of connection paths, each path being configured for a function, and a switch block configured to reassign a signal from a first connection path of the plurality of connection paths to a second connection path of the plurality of connection paths.

Abstract: A server includes a baseboard management controller (BMC), an input/output (I/O) chip, a serial port, and a serial port connection circuit. The serial port connection circuit is connected to the BMC, the I/O chip, and the serial port, and selectively connects either the BMC or the I/O chip to the serial port.

Abstract: An electronic measuring device includes a detection channel module, a sampling module, a control unit, a data path selector and a memory device. A user will be able to selectively enable the desired detection channels and store only data collected from enabled channels. The data collected from the detection channels are in serial data form. The device utilizes a serial-parallel shifter in its sampling module to convert the serial data to parallel data bytes. Two indicators in the storage unit of the memory device allow users to effectively store the parallel data bytes in designated locations. The innovative data conversion and storage methods of this invention will significantly conserve memory space that otherwise will be occupied by data from the disabled channels and allow accurate and efficient reading of the stored data.

Abstract: A Direct Memory Access (DMA) device for a multi-core system, and an operating method of the DMA device are provided. The DMA device includes a channel state determining unit to determine whether at least one channel among a source channel and a destination channel is available, the source channel being formed between a source core and the DMA device, and the destination channel being formed between a destination core and the DMA device, and a data transmission processing unit to process data of the source core to be transmitted to the destination core, when both the source channel and the destination channel are determined to be available.

Abstract: The present disclosure describes techniques for scalable embedded memory programming. In some aspects data is received at a first communication interface from a host device, at least a portion of the data is stored to a memory device supported by a printed circuit board, and the data is transmitted to a target device via a second communication interface.

Abstract: In a communication apparatus data is inputted to an input section. A priority determination section determines priority of the data inputted by the input section. If the priority of the data determined by the priority determination section is higher than a determined value, then a speed control section sets a transmission speed of the data outputted from an output section to a high value. On the other hand, if the priority of the data determined by the priority determination section is lower than the determined value, then the speed control section sets the transmission speed of the data outputted from the output section to a low value. The output section outputs the data at the set transmission speed.