Path Selection Patents (Class 710/38)
  • Patent number: 8296468
    Abstract: A storage controller that performs user-friendly information display, simplifies updating of support information, has external storage controllers to provide sufficient input/output performance, and expands the range of external storage controllers to be supported; and a controlling method for that storage controller. The storage controller includes a code extract/convert unit for converting a first code indicating a vendor name and/or device name of an external storage controller, obtained based on inquiry data transmitted from the external storage controller, into a second code indicating a real vendor name and/or real device name of the external storage controller. The storage controller creates support information that compiles information of each model regarding whether or not it can be connected to the respective external storage controllers. Furthermore, a path control system and a timeout time can be set for the respective external storage controllers.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: October 23, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Kosaku Kambayashi, Dai Taninaka
  • Patent number: 8291425
    Abstract: A computer in which functions of its resources are divided to realize a plurality of virtual computers 12 and which includes a plurality of physical devices. A managing unit of the computer, when usage of a virtual device has changed, selects a physical device compatible with the virtual device from physical devices usable for a control scheme and makes the physical device be associated with the virtual device and changes the control scheme of the virtual device, thereby achieving the control of devices in the virtual computers, where a plurality of control schemes including a shared scheme and a dedicated scheme are switched.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: October 16, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Souichi Takashige, Naoki Utsunomiya
  • Patent number: 8291177
    Abstract: A method for dynamically allocating control of a storage device, the method comprising receiving an access request from a first computer requesting access to a storage device; directing, based upon the access request, a first storage controller computer to assume an inactive state with respect to control of the storage device; and directing, based upon the access request, a second storage controller computer to assume an active state with respect to control of the storage device.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: October 16, 2012
    Assignee: CommVault Systems, Inc.
    Inventors: Varghese Devassy, Rajiv Kottomtharayil, Manoj Kumar Vijayan Retnamma
  • Publication number: 20120260121
    Abstract: A first path for forwarding an I/O request from a host device to a disk in a disk array is identified. The first path includes two endpoints (a first initiator endpoint on the host device and a first target endpoint on the disk array) separated by a storage area network. In response to an indication that the first path is non-functional, a second path to the disk for the I/O request is identified as an alternative to the first path. The second path includes a second initiator endpoint and a second target endpoint and is identified by selecting a path from among those paths that have at least one endpoint that is different from the two endpoints of the first path.
    Type: Application
    Filed: April 7, 2011
    Publication date: October 11, 2012
    Applicant: SYMANTEC CORPORATION
    Inventor: Praveen Kumar Yadav
  • Patent number: 8285893
    Abstract: A system and method is disclosed in which a switch is located between the I/O hubs of the computer system. The I/O hubs are coupled to I/O devices of the computer system. The I/O hubs are also coupled to one or more processors via direct point-to-point communication links. The I/O hub provides a connection point between various I/O devices and processors. The switch includes a set of internal communications pathways that can be set according to the communication status of links between the processors and I/O hubs of the system. When the communication links of the system are operational, the switch allocates all of I/O hub transmission bandwidth to I/O devices. When the communication links are determined to be not operational, the switch allocates some of I/O hub transmission bandwidth to establish a communication link between the I/O hubs of the computer system, while the remaining I/O hub transmission bandwidth is allocated to I/O devices.
    Type: Grant
    Filed: October 13, 2006
    Date of Patent: October 9, 2012
    Assignee: Dell Products L.P.
    Inventors: Joseph V. Rispoli, Thai H. Nguyen
  • Patent number: 8285933
    Abstract: A storage system provides virtual ports, and is able to transfer the virtual ports among physical ports located on multiple storage control units making up the storage system. The storage system is able to manage logical volumes and/or virtual volumes and virtual ports as a group when considering whether to move logical/virtual volumes and/or virtual ports to another storage control unit in the storage system. When the storage system is instructed to transfer volumes, virtual ports, or a group of volumes and virtual ports among the storage control units, the storage system determines whether an inter-unit network will be required to be used following the transfer. When the storage system determines that the inter-unit network will be required if the transfer takes place, the storage system determines and presents an alternate storage control unit for the transfer to avoid use of the inter-unit network, thereby avoiding degraded performance.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: October 9, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Junichi Hara, Takashi Oeda
  • Patent number: 8285945
    Abstract: A switch 100 includes a plurality of ports 101 for exchanging data. A shared memory 102 enables the exchange of data between first and second ones of the ports 101 and includes an array 202 of memory cells arranged as a plurality of rows and a single column having width equal to a predetermined word-width and circuitry 202, 204, 206, 208 for writing selected data presented at the first one of the ports 101 to a selected row in the array as a word of the predetermined word-width during a first time period and for reading the selected data from the selected row as a word of the predetermined wordwidth during a second time period for output at a second one of the ports 101.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: October 9, 2012
    Assignee: S. Aqua Semiconductor, LLC
    Inventor: G. R. Mohan Rao
  • Publication number: 20120254482
    Abstract: A storage system includes: an access path management unit managing a state of each access path for each logical disk; an I/O speed calculation unit storing, for each of the access paths, a data size and required time obtained when an I/O is executed, and calculates an I/O speed for every calculation cycle; a path candidate selection unit selecting an access path in the available state as an I/O use candidate; and a path candidate exclusion unit which excludes access paths of which speed is slow from the candidates, using a highest speed value among the speed values of the access paths selected as candidates, and the access path management unit sequentially changes the states of the access paths, out of the remaining candidates, to the I/O use states, in order of the I/O speed from the fastest until the number of access paths reaches the maximum number of paths.
    Type: Application
    Filed: March 20, 2012
    Publication date: October 4, 2012
    Applicant: NEC CORPORATION
    Inventor: Masanori KABAKURA
  • Patent number: 8275938
    Abstract: The computer system of the present invention has a plurality of SAS target devices, an SAS initiator device, and a service delivery subsystem that is connected to each SAS target device by means of a physical link that is physical wiring and connected to the SAS initiator device by means of a wide link constituted by a plurality of physical links. The SAS initiator device controls how many physical links in the wide link are allocated to a particular SAS target device, whereby access from the SAS initiator device to the SAS target device is made via a physical link that is allocated to the SAS target device and is not made via a physical link that is not allocated to the SAS target device.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: September 25, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Akio Nakajima, Ikuya Yagisawa
  • Patent number: 8261039
    Abstract: A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: September 4, 2012
    Assignee: RAMBUS Inc.
    Inventors: Richard E. Perego, Frederick A. Ware
  • Patent number: 8255596
    Abstract: Exemplary methods, systems, and computer program product embodiments for migrating existing data from a source storage controller to a target storage controller, each associated with a data processing storage subsystem, using a processor device in communication with a memory device, are provided. The target storage controller is configured with at least one target volume having pass-through support to a source volume of the source storage controller. An input/output (I/O) path to the existing data through the target storage controller is configured. The I/O path is added to an existing I/O path connected to the existing data using an operating system (OS) operational on at least one host in communication between the source and target storage controllers. The OS is adapted for I/O multipath support. Upon completion of data migration, the existing I/O path is removed.
    Type: Grant
    Filed: June 10, 2009
    Date of Patent: August 28, 2012
    Assignee: International Business Machines Corporation
    Inventors: Leon Kull, Maxim Kozover, Kariel Sandler, Moshe Yanai
  • Patent number: 8255588
    Abstract: A signal processing apparatus and method for processing an input signal. A first signal processing unit processes the input signal, and an expansion unit adds a second signal processing unit. A detecting unit detects whether the one or more additional second signal processing units has been added on to the expansion unit. A communication unit performs data transfers between the first signal processing unit and second additional signal processing unit via wireless communication, and a control unit coordinates the first signal processing unit and the one or more additional signal processing units.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: August 28, 2012
    Assignee: Sony Corporation
    Inventor: Tetsujiro Kondo
  • Patent number: 8250259
    Abstract: In a storage system having a plurality of storage apparatuses, each of the storage apparatuses stores therein a coupling mode that is information indicative of whether or not to permit setting of a communication path between each of the storage apparatuses and a plurality of other storage apparatuses. A management apparatus is provided to be coupled for communication to each of the storage apparatuses. The management apparatus has a communication path setting part that provides a user interface for setting the communication path. The communication path setting part does not permit setting of the communication path, at the time of setting the communication path, when the coupling modes of both of the storage apparatuses between which the communication path is to be set are set permissible.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: August 21, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Yoshiyuki Noborikawa, Koji Nagata, Kosuke Sakai
  • Patent number: 8250256
    Abstract: Methods, system and computer products for user-managed multi-path performance in balanced or unbalanced fabric configurations. Exemplary embodiments include a path priority selection method, including selecting a first I/O data path to be a highest priority path in a storage area network system, selecting a second I/O data path to be a low priority path, selecting an I/O threshold value, the I/O threshold value indicating that I/O data load is excessive, directing the load balance of I/O traffic to the first I/O data path, thereby placing the second I/O data path in a standby state, monitoring the first I/O data path, determining if the first I/O data path has reached the threshold value and performing a controlled failover of the first I/O data path to the second I/O data path when an I/O data load on the first data path has reached the threshold value.
    Type: Grant
    Filed: July 24, 2007
    Date of Patent: August 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Vishal V. Ghosalkar, Che Lui Shum, Stanley Y. Wu
  • Patent number: 8250257
    Abstract: Described are techniques for performing I/O operations. A graph is received including a plurality of nodes and edges. The graph includes a first level with a root node and one or more other levels of nodes. Each edge has a value indicating an I/O load metric. A thread associated with a first node determines whether to perform a background I/O operation directed to a first device and having a first priority. The first priority is compared to a first value of an I/O load metric. The first value is determined in accordance with criteria including a maximum usage of an I/O buffer of the first device and priorities of other I/O operations directed to the first device. If it is determined that the background I/O operation is to be performed, the background I/O operation is forwarded for processing on an I/O path having a corresponding path in the graph.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: August 21, 2012
    Assignee: EMC Corporation
    Inventors: Shay Harel, Peter Puhov
  • Patent number: 8250258
    Abstract: A hybrid serial peripheral interface (SPI) data transmission architecture adapted in a network device for connecting a host and a network is provided. The architecture comprises a RX buffer and RX SPI for maintaining a data receiving process, a TX buffer and TX SPI for maintaining a data transmission process, a configuration and status register and a hybrid SPI processing module. The hybrid SPI processing module makes the RX SPI performs the data transmission process as well when the RX SPI idles and the data transmission process proceeds at the same time and makes the TX SPI to performs the data receiving process as well when the TX SPI idles and the data receiving process proceeds at the same time. A hybrid SPI data transmission method is disclosed herein as well.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: August 21, 2012
    Assignee: Asix Electronics Corp.
    Inventors: Wei-Lu Su, Jian-Liang Chen, Tsung-Han Tsai, Shih-Ming Hwang
  • Patent number: 8244934
    Abstract: Disclosed is a method of managing a data storage network comprising a plurality of data storage volumes and a plurality of paths for connecting a server to a selected one of said data storage volumes, comprising determining, for an individual path, a plurality of performance parameters of said path during an interval; calculating a path performance metric from a combination of the determined performance parameters; and, if the path performance metric falls below a predefinable quality standard blocking the individual path from being used for a data communication with one of the data storage volumes; and signaling the blocking of the individual path. A computer program product and a server adapted to implement this method are also disclosed.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: August 14, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Sakshi Chaitanya Veni, Vijayakumar Balasubramanian, Guruprasad Ramachandrachar
  • Patent number: 8244924
    Abstract: A computer program product for processing communications between a host processor and a plurality of devices includes a tangible storage medium for performing a method comprising: receiving, by the host processor, physical configuration information including identification of a location of each physical endpoint connected to the host processor and a plurality of communication paths associated with each physical endpoint; sending at least one message to each physical endpoint on each of the plurality of communication paths, the at least one message requesting identification of a logical entity at the endpoint, and receiving logical configuration information identifying the logical entity; and generating a data collection accessible by the host processor, the data collection including the physical configuration information and the logical configuration information for each logical entity, and identification of a location of each physical endpoint connected to the host processor and a plurality of communication
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: August 14, 2012
    Assignee: International Business Machines Corporation
    Inventors: Tracy D. Butler, Scott B. Compton, Patricia G. Driever, Ilene A. Goldman, Craig D. Norberg, Dale F. Riedy, Matthew H. Sabins, Michael J. Shannon, Harry M. Yudenfriend
  • Patent number: 8244926
    Abstract: One data processor is provided with an interface for realizing connection with the other data processor. This interface is provided with a function for connecting the other data processor as a bus master to an internal bus of the one data processor, and the relevant other data processor is capable of directly operating peripheral functions that are memory mapped to the internal bus from an external side via the interface. Accordingly, the data processor can utilize the peripheral functions of the other data processor without interruption of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: August 14, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Junichi Nishimoto, Takuichiro Nakazawa, Koji Yamada, Toshihiro Hattori
  • Patent number: 8234437
    Abstract: The storage system includes a plurality of disk drives; a plurality of disk array controllers, each disk array controller controlling Redundant Array of Independent Disks (RAID) processes on said disk drives; and a plurality of switches external of said disk array controllers. The switches are coupled to the disk array controllers and to the disk drives, whereby each of the disk drives is coupled to each of the disk array controllers via the switches. Connections between disk array controllers and disk drives can be made independently via the switches.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: July 31, 2012
    Assignee: Hitachi, Ltd.
    Inventor: Kazuhisa Aruga
  • Patent number: 8234470
    Abstract: Described is a method, system, and computer program product for selecting a data repository within a computing environment. The data repository can exist on multiple target computing systems as a logical entity called a volume or a file system. When selecting at least one data repository, a data protection system of the computing environment analyzes the incoming data from a source computing system, in conjunction with information describing the data repositories. The data repository information, or repository characteristic information, can be stored on a repository volume table (RVT) of the data protection system. By determining a weighted selection score from the analysis of all the information available to the data protection system, the data protection system can intelligently select a data repository for storing data from the source computing system.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Gregory John Tevis, Ofer Peretz, Eran Raichstein, David Gregory Van Hise, Oren Wolf, Uri Wolloch
  • Publication number: 20120179846
    Abstract: Various embodiments for an Input/Output (I/O) path selection based on workload types are provided. A port workload controller is adapted to control the workload types of ports for accessing a storage device. A storage access command is received by the port workload controller from an application being executed on a virtual server on a physical server. The workload types related to the storage access command are determined. Storage access paths between the application and the storage device having the same workload types as the determined workload types related to the storage access command are determined. Storage access paths mapping data that is controlled by the port workload controller is used. A selected storage access path is selected out of the determined storage access paths having the least utilization. The storage device is accessed via the selected one of the plurality of storage access paths.
    Type: Application
    Filed: January 9, 2012
    Publication date: July 12, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nils HAUSTEIN, Thorsten KRAUSE, Ulf TROPPENS
  • Patent number: 8219715
    Abstract: The present invention is a method for providing multi-pathing via Small Computer System Interface Input/Output (SCSI I/O) referral between an initiator and a storage cluster which are communicatively coupled via a network, the storage cluster including at least a first target device and a second target device. The method includes receiving an input/output (I/O) at the first target device from the initiator via the network. The I/O includes a data request. The method further includes transmitting a SCSI I/O referral list to the initiator when data included in the data request is not stored on the first target device, but is stored on the second target device. The referral list includes first and second port identifiers for identifying first and second ports of the second target device respectively. The first and second ports of the target device are identified as access ports for accessing the data requested in the data request.
    Type: Grant
    Filed: December 15, 2008
    Date of Patent: July 10, 2012
    Assignee: Netapp, Inc.
    Inventors: Ross E. Zwisler, Andrew J. Spry, Gerald J. Fredin, Kenneth J. Gibson
  • Patent number: 8219725
    Abstract: A balancing process between I/O processor groups of a non-uniform multiprocessor system enables spreading of I/O workload across multiple I/O processor groups on a group base as soon as the I/O processor group with maximum group utilization reaches a certain high limit together with other processor groups being utilized significantly lower. The additional balancing is decreased step by step again when a certain low utilization limit is reached or the workload becomes more evenly balanced between the I/O processor groups. Checking if increase or decrease of the balancing is required is done periodically, but with low frequency to not affect overall performance. The checking and balancing happens asynchronously in predefined intervals. This solves the problem that with an increasing number of I/O processors the handling of initiatives leads to increased cache traffic and contention due to shared data structures, which slows down the I/O workload handling significantly.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: July 10, 2012
    Assignee: International Business Machines Corporation
    Inventors: Udo Albrecht, Michael Jung, Elke Nass
  • Patent number: 8209449
    Abstract: The present disclosure relates to a method for enabling a virtual processing unit to access a peripheral unit, the virtual processing unit being implemented by a physical processing unit connected to the peripheral unit, the method comprising a step of transmitting to the peripheral unit a request sent by the virtual processing unit to access a service provided by the peripheral unit, the access request comprising at least one parameter and an identifier of the virtual unit, the method comprising steps, executed by the peripheral unit after receiving an access request, of allocating a set of registers to the virtual unit identifier received, storing the parameter received in the register set allocated, and when the peripheral unit is available for processing a request, selecting one of the register sets, and triggering a process in the peripheral unit from the parameters stored in the selected register set.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: June 26, 2012
    Assignee: STMicroelectronics Rousset SAS
    Inventors: Christian Schwarz, Joel Porquet
  • Patent number: 8205018
    Abstract: A method and apparatus for allowing a limited functionality Universal Serial Bus (USB) host controller to manage specific USB peripheral devices on a downstream facing USB port is provided. The port is also capable of dynamically interfacing to any USB compliant peripheral device, even one not supported directly by the limited capabilities of the host controller.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: June 19, 2012
    Assignee: RGB Systems, Inc.
    Inventors: Brian E. Tauscher, Michael Izquierdo
  • Publication number: 20120151105
    Abstract: In a storage system having a plurality of storage apparatuses, each of the storage apparatuses stores therein a coupling mode that is information indicative of whether or not to permit setting of a communication path between each of the storage apparatuses and a plurality of other storage apparatuses. A management apparatus is provided to be coupled for communication to each of the storage apparatuses. The management apparatus has a communication path setting part that provides a user interface for setting the communication path. The communication path setting part does not permit setting of the communication path, at the time of setting the communication path, when the coupling modes of both of the storage apparatuses between which the communication path is to be set are set permissible.
    Type: Application
    Filed: February 9, 2012
    Publication date: June 14, 2012
    Applicant: Hitachi, Ltd.
    Inventors: Yoshiyuki NOBORIKAWA, Koji NAGATA, Kosuke SAKAI
  • Patent number: 8200883
    Abstract: In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: June 12, 2012
    Assignee: Intel Corporation
    Inventors: Peter MacWilliams, James Akiyama, Douglas Gabel
  • Patent number: 8200871
    Abstract: A system including a storage processing device with an input/output module. The input/output module has port processors to receive and transmit network traffic. The input/output module also has a switch connecting the port processors. Each port processor categorizes the network traffic as fast path network traffic or control path network traffic. The switch routes fast path network traffic from an ingress port processor to a specified egress port processor. The storage processing device also includes a control module to process the control path network traffic received from the ingress port processor. The control module routes processed control path network traffic to the switch for routing to a defined egress port processor. The control module is connected to the input/output module. The input/output module and the control module are configured to interactively support data virtualization, data migration, data journaling, and snapshotting.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: June 12, 2012
    Assignee: Brocade Communications Systems, Inc.
    Inventors: Venkat Rangan, Edward D. McClanahan, Michael B. Schmitz
  • Patent number: 8194697
    Abstract: A selective connection device allowing the connection of at least one peripheral to a target computer and a selective control system comprising such a device. It relates to the field of devices for the selective connection of a control device composed of input/output peripherals to various target computers. The selective connection device affords security guarantees by preventing communication between the various target computers that may be controlled.
    Type: Grant
    Filed: February 25, 2008
    Date of Patent: June 5, 2012
    Assignee: Sagem Defense Securite
    Inventors: François Guillot, Jean-Marie Courteille
  • Patent number: 8195848
    Abstract: A method, system, and apparatus of medical device created through resource leverage of a host processing system are disclosed. In one embodiment, a method of a medical component includes automatically communicating a medical operating system to a host processing system from a memory location of the medical component when it is determined that the host processing system does not include a medical operating system optimized to operate with the medical component, processing a confirmation from the host processing system that the medial operating system has repurposed the host processing system of the host processor and that the medical operating system is now active on the host processing system, capturing a patient reading through the medical component, and leveraging at least one of a processing resource and an input-output (I/O) resource of the host processing system in providing a measurement of the patient reading to a user.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: June 5, 2012
    Assignee: EconoMEDics, Inc.
    Inventor: Zach Jones
  • Patent number: 8195864
    Abstract: An apparatus for transmitting data across a high-speed serial bus includes an IEEE 802.3-compliant PHY having a GMII interface; an IEEE 1394-compliant PHY in communication with the IEEE 802.3-compliant PHY via a switch; the switch determining whether data transmission is be routed to the IEEE 802.3-compliant PHY or the IEEE 1394-compliant PHY; a first connection, the first connection for transmitting data between a device and the IEEE 802.3-compliant PHY; and a second connection, the second connection for transmitting data between a device and the IEEE 1394-compliant PHY.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: June 5, 2012
    Assignee: Apple Inc.
    Inventors: Colin Whitby-Strevens, Michael D. Johas Teener
  • Publication number: 20120137166
    Abstract: Each of SAS expanders (“expander(s)” hereinafter) has a switch device for switching whether to bypass the expander in each communication path or not. Of the plurality of switch devices, an actual connection destination of a switch device bypassing the expander is a switch device in a upper-level and/or a lower-level of the switch device. Of the plurality of switch devices, an actual connection destination of a switch device that does not bypass an expander is the expander.
    Type: Application
    Filed: November 30, 2010
    Publication date: May 31, 2012
    Inventors: Tomoaki Kurihara, Toshihiro Nitta
  • Publication number: 20120131237
    Abstract: An extension device that extends a communication path between a host device and an input/output (IO) device, the extension device including a determination unit configured to determine whether a first logical path exists between the host device and the IO device, a logical path establishment unit configured to request the IO device to establish a second logical path between the extension device and the IO device when the first logical path does not exist between the host device and the IO device, and a communication check unit configured to check communication on the second logical path established between the extension device and the IO device that establishes the second logical path.
    Type: Application
    Filed: October 27, 2011
    Publication date: May 24, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Masanori NAGANUMA, Takashi Sawakuri, Shotaro Nakayama, Shigeki Sekine
  • Publication number: 20120131238
    Abstract: A redundancy manager manages commands to peripheral devices in a computer system. These peripheral devices have multiple pathways connecting it to the computer system. The redundancy manager determines the number of independent pathways connected to the peripheral device, presents only one logical device to the operating system and any device driver and any other command or device processing logic in the command path before the redundancy manager. For each incoming command, the redundancy manager determines which pathways are properly functioning and selects the best pathway for the command based at least partly upon a penalty model where a path may be temporarily penalized by not including the pathway in the path selection process for a predetermined time. The redundancy manager further reroutes the command to an alternate path and resets the device for an alternate path that is not penalized or has otherwise failed.
    Type: Application
    Filed: January 31, 2012
    Publication date: May 24, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Scott A. Bauman, Brian L. Bowles, Anthony P. Vinski, Rick A. Weckwerth
  • Patent number: 8185675
    Abstract: An interface system which is adapted to a portable device is provided. The interface system includes a control chip, a first peripheral device, an external interface port, a first, a second, a third bus driver and a control unit. The control chip provides at least a first and a second interface port. The first bus driver has a first, a second input port and an output port. The first bus driver is used to interface the first input port with the output port or interface the second input port with the output port according to a first control signal. The second bus driver is used to interface the first interface port with the external interface port or interface the output port with the external interface port according to a second control signal. The third bus driver is used to interface the first peripheral device with the second input port or interface the second interface port with the first peripheral device according to the first control signal.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: May 22, 2012
    Assignee: Wistron Corp.
    Inventor: Ming-Xing Ji
  • Publication number: 20120124253
    Abstract: A switch circuit for switching input/output port includes a control unit, a built-in input/output (I/O) port, an external I/O port and a switch unit. The switch unit is electrically connected to the control unit, the built-in I/O port and the external I/O port. The switch unit receives a control signal and selectively forms a channel between the control unit and the built-in I/O port or between the control unit and the external I/O port accordingly.
    Type: Application
    Filed: November 9, 2011
    Publication date: May 17, 2012
    Inventor: Hsu-Hung CHENG
  • Patent number: 8180937
    Abstract: Methods and systems for a low noise amplifier with tolerance to large inputs are disclosed and may include generating at least one control signal that controls a plurality of directional modes of at least one contact pad on a mobile multimedia processor (MMP) in an integrated circuit. Selectable modes may include: bidirectional, input, and an output mode. Each of the modes includes a bypass mode and a processing mode that may be controlled by the generated control signal. Received data may be processed by circuitry in the MMP when the processing mode may be enabled. Received data may be passed through the MMP without being processed by the MMP when the bypass mode may be enabled. An additional signal may be generated to dynamically pull-down a potential of the at least one contact pad and/or to pull-up a potential of said at least one contact pad.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: May 15, 2012
    Assignee: Broadcom Corporation
    Inventor: Timothy James Ramsdale
  • Patent number: 8176218
    Abstract: Apparatus and methods for real-time routing of received frames in a split-path architecture storage controller. In one exemplary embodiment, a split-path storage controller comprises a soft-path I/O processor for processing of any received frames and comprises a fast-path I/O processor for efficient processing of common read and write command. A content parsing circuit of the storage controller parses each frame substantially concurrent with reception of the frame and selects an I/O processor for processing of an initial frame and subsequent related frames. Received frames are then routed concurrently as they are received for processing by the selected I/O processor of the multiple I/O processors of the split-path storage controller.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: May 8, 2012
    Assignee: LSI Corporation
    Inventors: Howard Young, Dante Cinco, Thomas P. Anderson
  • Patent number: 8171176
    Abstract: Disclosed is a method and a SAS controller device that abstract access from one or more virtual machines operating on a host system to SAS physical devices connected to the SAS controller without a routing table for port-to-port messaging on the SAS controller. An embodiment may create a virtual expander for each physical port of the SAS controller and further create virtual ports within the virtual expanders to provide abstracted access to SAS physical devices for the virtual machines. The SAS physical devices may be replicated/cloned within the virtual ports. Each replicated/cloned SAS physical device may be assigned a unique SAS address for the SAS controller (i.e., unique for the SAS controller such that other replicates/clones on other virtual ports have a different SAS address).
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: May 1, 2012
    Assignee: LSI Corporation
    Inventors: Sayantan Battacharya, Lawrence J. Rawe, Edoardo Daelli
  • Patent number: 8161209
    Abstract: A peer-to-peer special purpose processor architecture and method is described. Embodiments include a plurality of special purpose processors coupled to a central processing unit via a host bridge bus, a direct bus directly coupling each of the plurality of special purpose processors to at least one other of the plurality of special purpose processors and a memory controller coupled to the plurality of special purpose processors, wherein the at least one memory controller determines whether to transmit data via the host bus or the direct bus, and whether to receive data via the host bus or the direct bus.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: April 17, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Stephen Morein, Mark S. Grossman, Warren Fritz Kruger, Brian Etscheid
  • Patent number: 8156266
    Abstract: A method for determining transfer rate comprising selecting a first transfer rate of a plurality of transfer rates, transmitting a message at the first transfer rate over a Consumer Electronics Control (CEC) line of a High Definition Multimedia Interface (HDMI) network, determining whether an acknowledgment to the message having been transmitted at the first transfer rate is received, storing, in the event the acknowledgment to the message having been transmitted at the first transfer rate is received, the first transfer rate and storing, in the event no acknowledgment is received, a default transfer rate of the plurality of transfer rates.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: April 10, 2012
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventors: Davender Agnihotri, Lee Pedlow
  • Patent number: 8151013
    Abstract: A host I/F unit has a management table for managing an MPPK which is in-charge of the control of input/output processing for a storage area of an LDEV, and if a host computer transmits an input/output request for the LDEV, the host I/F unit transfers the input/output request to the MPPK which is in-charge of the input/output processing for the LDEV based on the management table, an MP of the MPPK performs the input/output processing based on the input/output request, and the MP of the MPPK also judges whether the MPPK that is in-charge of the input/output processing for the LDEV is to be changed, and sets the management table so that an MPPK which is different from the MPPK that is in-charge is to be in-charge of the input/output processing for the LDEV.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: April 3, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Kazuyoshi Serizawa, Yasutomo Yamamoto, Norio Shimozono, Akira Deguchi, Hisaharu Takeuchi, Takao Sato, Hisao Homma
  • Patent number: 8151029
    Abstract: A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: April 3, 2012
    Assignee: Silicon Laboratories Inc.
    Inventors: Scott Haban, Dylan Hester, Ruifeng Sun
  • Patent number: 8151018
    Abstract: A system and corresponding method for transferring data. Data may be selectively communicated via a USB port of a device. An indication of a device type may be received at the USB port from an external interface. USB protocol data or uncompressed high definition media data may be caused to be selectively supplied to the USB port as a function of the indication. The selected data may be transmitted via the USB port to an external interface. The uncompressed high definition media data may include at least one lane of media data or multimedia data in accordance with a DisplayPort standard. In some embodiments, either USB protocol data or multimedia data comprising audio data and uncompressed high definition video data may be caused to be selectively supplied to the USB port as a function of the indication. The indication may be a data format signal.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: April 3, 2012
    Assignee: Analogix Semiconductor, Inc.
    Inventors: Soumendra Mohanty, Ning Zhu
  • Publication number: 20120072623
    Abstract: The storage system includes a first storage subsystem having a first logical volume to be accessed by a host computer, and a second storage subsystem connected to the first storage subsystem and having a second logical volume to be mapped to the first logical volume. The first storage subsystem includes a memory having definition information for defining a plurality of logical paths that transfer, to the second logical volume, I/O from the host computer to the first logical volume, and a transfer mode of the I/O to the plurality of logical paths. At least two or more logical paths among the plurality of logical paths are defined as active, and the controller transfers the I/O to the at least two or more logical paths set as active.
    Type: Application
    Filed: November 29, 2011
    Publication date: March 22, 2012
    Applicant: HITACHI, LTD.
    Inventors: Yutaka Watanabe, Keishi Tamura
  • Patent number: 8140725
    Abstract: Provided is an article of manufacture, system and method for a management system for using host and storage controller port information to configure paths between a host and storage controller in a network. The management system obtains information on ports on at least one host, at least one storage controller, and at least one fabric over which the host and storage controller ports connect. The management system gathers, for at least one host port and storage controller port, a connection metric and a traffic metric. The management system processes the connection and traffic metrics for the host and storage ports to select at least one host port and at least one storage controller port configures the port pair to provide at least one path enabling the access at least one storage volume managed by the selected storage controller.
    Type: Grant
    Filed: May 14, 2010
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Eric Kevin Butler, Pi-Wei Chin, Scott J. Colbeck, Kaladhar Voruganti
  • Patent number: 8140720
    Abstract: In a storage system having a plurality of storage apparatuses, each of the storage apparatuses stores therein a coupling mode that is information indicative of whether or not to permit setting of a communication path between each of the storage apparatuses and a plurality of other storage apparatuses. A management apparatus is provided to be coupled for communication to each of the storage apparatuses. The management apparatus has a communication path setting part that provides a user interface for setting the communication path. The communication path setting part does not permit setting of the communication path, at the time of setting the communication path, when the coupling modes of both of the storage apparatuses between which the communication path is to be set are set permissible.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: March 20, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Yoshiyuki Noborikawa, Koji Nagata, Kosuke Sakai
  • Patent number: 8135882
    Abstract: In order to appropriately manage configuration information acquired from a storage system for the purpose of performance management, etc., an information processing apparatus managing the configuration information, i.e.
    Type: Grant
    Filed: May 8, 2009
    Date of Patent: March 13, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Hirokazu Uchi, Hideo Ohata
  • Patent number: 8135883
    Abstract: Hub apparatus that supports multiple high speed devices and a super speed device. The hub apparatus may include at least one upstream port for coupling to a host device and at least one downstream port for coupling to at least one downstream device. The hub apparatus may further include an embedded device as well as an internal hub coupled to the upstream port, the embedded device, and the at least one downstream port. The internal hub may be configured to provide a connection between the host device and the embedded device at a first speed (e.g., USB high speed). However, when supported by the host device, the embedded device may communicate with the host device at a higher speed than the first speed (e.g., USB super speed), e.g., without using the internal hub.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: March 13, 2012
    Assignee: Standard Microsystems Corporation
    Inventors: Morgan H. Monks, Terry R. Altmayer, Satish N. Anand