Abstract: An automated backup and reversion system comprising at least two storage systems with one source storage system being physically connected to at least one host system during normal processing at any given time. During the backup process, involved storage devices are physically disconnected from the host system. The at least one destination storage system receiving the information backup may thereafter be connected to the host system to allow for subsequent host processing. The initial source storage system may then remain disconnected from the host system and assume the role of a destination storage system. Each storage system is located at the same logical location while being processed so that the host system is unaware that any storage system change has occurred. A plurality of storage systems may be configured with only one being processed at any given time, and the remainder may comprise successive backups after any negative event.

Abstract: A method is provided for processing operation command in a computer that has a display and a host which includes a first display processing unit for local displaying and a second display processing unit for remote displaying. The operation command is from a remote data processing terminal. The method includes: receiving a first operation command from the data processing terminal, the first operation command being a power-on command; performing power-on of the computer, shielding the first display processing unit and loading only a driver of the second display processing unit according to first operation command; receiving a second operation command from the data processing terminal, the second operation command being not a power-on command; executing the second operation command to obtain operation results, the operation results being image data processed by the second display processing unit, and sending the operation results to the remote data processing terminal, for remote displaying.

Abstract: A redundancy manager manages commands to peripheral devices in a computer system. These peripheral devices have multiple pathways connecting it to the computer system. The redundancy manager determines the number of independent pathways connected to the peripheral device, presents only one logical device to the operating system and any device driver and any other command or device processing logic in the command path before the redundancy manager. For each incoming command, the redundancy manager determines which pathways are properly functioning and selects the best pathway for the command based at least partly upon a penalty model where a path may be temporarily penalized by not including the pathway in the path selection process for a predetermined time. The redundancy manager further reroutes the command to an alternate path and resets the device for an alternate path that is not penalized or has otherwise failed.

Abstract: Provided is an information processing apparatus and method of controlling same in which, when data transfer is performed among a plurality of control circuits, which control circuit is used to execute data transfer is controlled appropriately based on the transfer conditions of data transfer. To accomplish this, the apparatus has first and second control circuits, a request for data transfer performed between the first and second control circuits is acquired, the transfer conditions of the acquired data transfer are analyzed and which of the first and second control circuits is to execute the data transfer is selected.

Abstract: A circuit that selectively connects an integrated circuit to elements external to the integrated circuits. The circuit includes an input/output element that selectively connects an input/output pin as a function of a power requirement or a signal bandwidth requirement of the integrated circuit. The input/output element includes one or more switching devices that connect the input/output pin to an external element, such as a power supply or external signal path. The input/output element also includes one or more switching devices that connect the input/output pin to an internal element, such as a power network or internal signal line.

Abstract: Apparatus and methods for real-time routing of received frames in a split-path architecture storage controller. In one exemplary embodiment, a split-path storage controller comprises a soft-path I/O processor for processing of any received frames and comprises a fast-path I/O processor for efficient processing of common read and write command. A content parsing circuit of the storage controller parses each frame substantially concurrent with reception of the frame and selects an I/O processor for processing of an initial frame and subsequent related frames. Received frames are then routed concurrently as they are received for processing by the selected I/O processor of the multiple I/O processors of the split-path storage controller.

Abstract: A real-time customer relation management system is disclosed. The system can provide increased availability, reduced internal latencies, and reduced data processing and transfer. The system can provide real time processing and batch processing. The system architecture can have an in-memory write-through cache. The cache can store data that would have otherwise been sent to a database. The system can have a backup in-memory write-through cache. The system can use a warm standby, for example, to enhance data backup efficiency.

Abstract: A signal processing device is a predetermined signal processing device among signal processing devices which perform signal processing on an input signal that is input to any one of the signal processing devices in such a manner that the signal processing devices share signal processing. The signal processing device includes a signal processing section that performs signal processing on a first-bandwidth signal, which is included in the input signal, in accordance with a processing capability of the signal processing device to generate a first output signal; and a signal integration section that integrates a second output signal with the first output signal, and that outputs the integrated signal to a second different signal processing device, the second output signal being generated in a first different signal processing device by performing signal processing on a second-bandwidth signal, which is included in the input signal.

Abstract: Port management information is prepared for managing information related to the status of each of a plurality of ports possessed by a storage system in a unified manner. Change of the status related to any one of a plurality of ports from “normal” to anomalous is detected. For a subject external device which is using the anomalous path as an I/O path, a “normal” port is selected, on the basis of the port management information, from one or more ports related to one or more paths which are being used as alternate paths. And information related to this “normal” port which has been selected is notified to the subject external device. During path changeover, the subject external device selects as an I/O path an alternate path which is related to the “normal” port specified from the notified information.

Abstract: A single fibre channel switch or serial attached SCSI expander applies zoning on the initiator ports to each of the two ports of one or more drives. The fibre channel switch or serial attached SCSI expander uses zoning to connect both ports of each drive to a single expander and set the zones in the expander such that each zone includes at least one initiator port and one drive port.

Abstract: A shared memory system for a multicore computer system utilizing an interconnection network that furnishes tens of processing cores or more with the ability to refer concurrently to random addresses in a shared memory space with efficiency comparable to the typical efficiency achieved when referring to private memories. The network is essentially a lean and light-weight combinational circuit, although it may also contain non-deep pipelining. The network is generally composed of a sub-network for writing and a separate multicasting sub-network for reading, whose topologies are based on multiple logarithmic multistage networks, e.g. Baseline Networks, connected in parallel. The shared memory system computes paths between processing cores and memory banks anew at every clock cycle, without rearrangement.

Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

Abstract: A wireless communicating function is provided for a printer, a digital camera, a computer, or another external apparatus can be connected without needing an operation, such as a connection exchange of a device or the like, and the burden on the power supply on the printer can be lightened. A wireless communicating apparatus has a first universal serial bus I/F for connecting to the printer, a communication control unit for allowing the printer to make wireless communication with another external wireless apparatus, and a second universal serial bus I/F for connecting an external universal serial bus apparatus. Either the communication control unit or the second universal serial bus I/F is connected to the first universal serial bus I/F in accordance with a connecting state of the external universal serial bus apparatus to the second universal serial bus I/F.

Abstract: One embodiment of the present invention is an integrated circuit implementing a storage-shelf router, used in combination with path controller cards and optionally with other storage-shelf routers, to interconnect SATA disks within a storage shelf or disk array to a high-bandwidth communications medium, such as an FC arbitrated loop. When two, four, six, or eight or more storage-shelf routers are used within a storage shelf, and the interconnections between the storage-shelf routers, disk drives, and external communications media are properly designed and configured, the resulting storage shelf constitutes a discrete, highly-available component that may be included in a disk array or in other types of electronic devices. The storage-shelf router features a disk-drive adaptation layer that allows a storage-shelf router to interface to, and manage, any of many different types of disk drives. The disk-drive adaptation layer includes a disk-profile table and associated firmware logic.

Abstract: A method and apparatus are provided for implementing connection management in SAS expander devices. SAS expanders are commonly used within a SAS network topology to allow multiple disk drives to connect to multiple host devices. The method and apparatus provides arbitration of connection requests to be setup or removed among multiple end devices and expander devices so as to increase system performance and reduce hardware cost in a standard compliant manner.

Abstract: A method and apparatus for intelligently routing and managing audio signals within an electronic device is disclosed. The routing is responsive to a set of logical and physical policies which are stored in data tables which can be updated as needed.

Abstract: An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced.

Abstract: The present invention relates to the field of embedded processing systems and electronic control units (ECUs) and to autonomic embedded computing solutions. The present invention proposes to remove or extract the application-specific support functions and respective I/O subsystems from the main processors or controllers of the system, to include said extracted circuits into a respective number of ASIC chips or the like, and to connect them preferably via a supervising General Controller Unit (12) to a plurality of standard and low-price processors (40), which have the task to supply the ASIC and the multiple functions thereof with enough computing power.

Abstract: A semiconductor device coupled to input/output pins includes a first core to operate a first function and a second core to operate a second function. A multiplexer is arranged to set the input/output pins to the first function or to the second function, and an arbiter is configured to receive requests from the cores to use the input/output pins and to grant use of the input/output pins to a selected core. A register is arranged to store a value indicative of a delay to be applied by the arbiter when granting use of the input/output pins to the second core.

Abstract: The storage system includes a first storage subsystem having a first logical volume to be accessed by a host computer, and a second storage subsystem connected to the first storage subsystem and having a second logical volume to be mapped to the first logical volume. The first storage subsystem includes a memory having definition information for defining a plurality of logical paths that transfer, to the second logical volume, I/O from the host computer to the first logical volume, and a transfer mode of the I/O to the plurality of logical paths. At least two or more logical paths among the plurality of logical paths are defined as active, and the controller transfers the I/O to the at least two or more logical paths set as active.

Abstract: A first free port present in a controller or a switch device is physically connected to a second free port present in a switch device (switch device in another storage device unit) other than the controller or switch device comprising the first free port. The possibility of logical connection via a physical path connecting the first free port and second free port is controlled.

Abstract: A balancing process between I/O processor groups of a non-uniform multi-processor system enables spreading of I/O workload across multiple I/O processor groups on a group base as soon as the I/O processor group with maximum group utilization reaches a certain high limit together with other processor groups being utilized significantly lower. The additional balancing is decreased step by step again when a certain low utilization limit is reached or the workload becomes more evenly balanced between the I/O processor groups. Checking if increase or decrease of the balancing is required is done periodically, but with low frequency to not affect overall performance. The checking and balancing happens asynchronously in predefined intervals. This solves the problem that with an increasing number of I/O processors the handling of initiatives leads to increased cache traffic and contention due to shared data structures, which slows down the I/O workload handling significantly.

Abstract: The physical server includes a hypervisor for managing an association between the virtual server and the I/O device allocated to the virtual server. The I/O switch includes: a setting register for retaining a request to inhibit a transaction from being issued from the I/O device to the virtual server; a Tx inhibition control module for performing an inhibition of the transaction from the I/O device to the virtual server, and guaranteeing a completion of a transaction from the I/O device issued before the inhibition; a virtualization assist module for converting an address of the virtual server into an address within a memory of the physical server; and a switch management module for managing a configuration of the I/O switch.

Abstract: Systems and methods for path selection for application commands are described. To this end, information associated with at least one application command that were processed at least one port of a target device is received. For a subsequent application command, a set of ports of the target device is determined. In one implementation, the set of ports is determined based on information associated with the subsequent application command. Once the set of ports is determined, the subsequent application command is directed to a port selected from the set of ports.

Abstract: A redundancy manager manages commands to peripheral devices in a computer system. These peripheral devices have multiple pathways connecting it to the computer system. The redundancy manager determines the number of independent pathways connected to the peripheral device, presents only one logical device to the operating system and any device driver and any other command or device processing logic in the command path before the redundancy manager. For each incoming command, the redundancy manager determines which pathways are properly functioning and selects the best pathway for the command based at least partly upon a penalty model where a path may be temporarily penalized by not including the pathway in the path selection process for a predetermined time. The redundancy manager further reroutes the command to an alternate path and resets the device for an alternate path that is not penalized or has otherwise failed.

Abstract: Techniques for host to host transfer of media and the use of persistent reservation to protect media during host to host transfer is disclosed. Exemplary embodiments may be realized as methods and systems for transferring a sequential media loaded in a drive from a first host to a second host without physically unloading the media. The first host may have a persistent reservation or non-persistent reservation of the drive. Likewise, the second host may have a persistent reservation or non-persistent reservation of the drive. Logical unload, logical load and preemption commands are utilized as is error recovery from a failed reservation.

Abstract: An integrated circuit input/output interface with empirically determined delay matching is disclosed. In one embodiment, the integrated circuit input/output interface uses empirical information of signal traces coupled to the integrated circuit to adjust a transmit/receive clock of each pin of the interface so as to compensate for delay mismatches caused by differences in signal trace lengths. In one embodiment, values representative of the empirical information are stored for use by the integrated circuit to generate trace-specific signals so as to compensate for delay differences that are at least partially caused by unmatched signal trace lengths. The empirical information, in one embodiment, includes signal flight time of each signal trace, which can be pre-measured or pre-calculated from known signal trace lengths. The empirical information, in another embodiment, includes trace-specific phase offset values calculated from pre-calculated or pre-measured signal flight times or signal trace lengths.

Abstract: According to one embodiment, an information reproducing apparatus includes a memory, a decoder, an intermediate memory which is disposed between the memory and the decoder and which temporarily stores, in succession, the data that are supplied from the memory and then outputs the data to the decoder, switching circuit for switching an output of the memory to one of the decoder and the intermediate memory, memory management circuit for managing arrangement information of the data that are stored in the memory, determination circuit for determining whether the data that are stored in the memory are arranged in physically discontinuous memory areas of the memory, and switching control circuit for switching, in a case where the determination circuit determines that the data are arranged in the physically divided memory areas, the switching circuit in a manner to input the data output from the memory to the decoder via the intermediate memory.

Abstract: An aspect of the invention is directed to a method for storage I/O (input/output) path configuration in a system that includes a storage system connected via a network to a plurality of nodes. The method comprises receiving an I/O access to one or more storage volumes in the storage system from one of the nodes; if the I/O access is an initial I/O access to any of the storage volumes in the storage system from any of the nodes in the system, allowing the initial I/O access from the one node and prohibiting I/O access to the storage volumes in the storage system by other nodes in the system; and if the I/O access is not an initial I/O access to any of the storage volumes in the storage system from any of the nodes in the system, allowing the I/O access only if the I/O access is from the one node which made the initial I/O access and rejecting the I/O access for other nodes in the system.

Abstract: A safety control block interfaces to one or more devices utilizing one or more communication protocols wherein a network interface receives and/or transmits data directly from a network. A backplane interface receives and/or transmits data from a backplane. A backplane extension receives and/or transmits data from a backplane. A processing component receives data from at least one of the network interface, backplane interface and backplane extension and determines if the received data is related to safety or non-safety. A safety I/O circuitry receives safety data from the processing component; wherein the safety data is utilized to communicate to at least one control device.

Abstract: The present disclosure is directed to a method for communication between an initiator system and a block storage cluster. The method may comprise receiving an initial data request from the initiator system to a first storage system, a portion of the data requested in the initial data request is not stored by the first storage system, but is stored by a second storage system; retrieving the portion of the data that is stored by the second storage system; forwarding the portion of the data to the initiator system; and transmitting a referral list comprising at least one referral from the first storage system to the initiator system, wherein the initiator system is configured for maintaining a referral cache based on the referral list, and a subsequent data request initiated by the initiator system is directed to the block storage cluster based on the referral cache.

Abstract: A storage controller that performs user-friendly information display, simplifies updating of support information, has external storage controllers to provide sufficient input/output performance, and expands the range of external storage controllers to be supported; and a controlling method for that storage controller. The storage controller includes a code extract/convert unit for converting a first code indicating a vendor name and/or device name of an external storage controller, obtained based on inquiry data transmitted from the external storage controller, into a second code indicating a real vendor name and/or real device name of the external storage controller. The storage controller creates support information that compiles information of each model regarding whether or not it can be connected to the respective external storage controllers. Furthermore, a path control system and a timeout time can be set for the respective external storage controllers.

Abstract: A physical layer device (PLD), comprising: a first serializer-deserializer (SERDES) device having a first parallel port; a second SERDES device having a second parallel port; a third SERDES device having a third parallel port; and a path selector being selectively configurable to provide either (i) a first signal path between the first and second parallel ports, or (ii) a second signal path between the first and third parallel ports.

Abstract: A memory device includes a high speed port, a low speed port, at least a first memory bank, a first register, and a multiplexer. The at least first memory bank is shared by the high speed port and the low speed port. The first register store information that indicates which one of the ports has permission to access the first memory bank. The multiplexer connects one of the high speed port or the low speed port to the first memory bank, in response to the information stored in the first register.

Abstract: A method and apparatus for intelligently routing and managing audio signals within an electronic device is disclosed. The routing is responsive to a set of logical and physical policies which are stored in data tables which can be updated as needed.

Abstract: A path creation support apparatus acquires either a portion of the parameters required for path creation or parameter decision information for deciding this portion of the parameters from a storage system or a host. The path creation support apparatus decides the portion of the parameters based on the parameter decision information. Upon receiving an access path creation start request, the path creation support apparatus sends an access path creation indication to the host and the storage system which specifies the parameters together with the access path creation start request, and either the parameters acquired beforehand or the acquired parameters decided based on the parameter decision information.

Abstract: A method of communication in a communication apparatus includes steps of suppressing communication with a first communication device, which has been connected to a first communication interface, in accordance with data from the first communication device; establishing communication with a second communication device by a second communication interface; removing suppression of communication with the first communication device after communication with the second communication device has been established; and communicating data between the first and second communication devices via the first communication and second communication interfaces.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder.

Abstract: A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

Abstract: An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced.

Abstract: A method and system suitable for grouping a plurality of multifunction devices (MFDs), the system including a storage station for storing information gathered from the plurality of MFDs by selectively polling the plurality of MFDs; wherein the information is selectively processed based on static performance data and dynamic performance data relating to the plurality of MFDs.

Abstract: The Distributed Virtual I/O Tool replaces dedicated VIO server LPARs by distributing the virtual I/O functions across several application LPARs connected by a high-speed communication channel. The physical I/O devices are distributed across available LPARs. The Distributed Virtual I/O Tool assigns each I/O request to an appropriate I/O device. The Distributed Virtual I/O Tool monitors each I/O request and reassigns I/O devices when performance drops on a specific device or when a device is no longer available.

Abstract: A computer-implemented method, system and computer program product for managing USB ports on blades in a blade center are presented. A set of remotely-transmitted instructions causes a multiplexer to physically disconnect one or more selected USB ports on a blade. In one embodiment, the same one or more selected USB ports are also software-disabled by a USB software-based controller.

Abstract: A plurality of system controllers 300 each comprising a memory medium 400 and an I/O device 500 under the control of the system controller 300 are connected to a CPU node 100 by way of a plurality of system buses 200. The CPU node 100 executes a memory interleave for distributing memory accesses to the system buses 200 (i.e., the system controllers 300). In performing an I/O access to the I/O device 500, the CPU node 100 firstly inquires from a representative system controller 300 (SC0) as to which system bus 200 (i.e., a system controller 300) has a target I/O device 500 and then executes an actual I/O access to the system bus 200 returned in a response from the SC0. Even when the CPU node 100 executes a memory interleave in the case of a memory-mapped I/O, the CPU node 100 is not required to manage the location information of the I/O device 500.

Abstract: An architecture and associated methods and devices are described in which a first selectable data path may be associated with a first port operating at a first data rate, a second selectable data path may be associated with a second port operating at a second data rate, and a third selectable data path may be associated with a third port operating at a third data rate that is higher than the first data rate and the second data rate. A plurality of security engines may be included which may be configurable to provide cipher key-based security for data associated with the first port and the second port using the first selectable path and the second selectable path, respectively, and configurable to provide cipher key-based security of data associated with the third port using the third selectable data path.

Abstract: For a storage system provided with a plurality of storage modules including a first storage module and a second storage module, the first storage module is provided with a first switch circuit including a plurality of ports and a first circuit connected to any of the plurality of ports included in the first switch circuit via an internal path, and the second storage module is provided with a second circuit. A direct path that is a path for connecting the first switch circuit and the second circuit is connected to any of the plurality of ports included in the first switch circuit. The first circuit issues a packet addressed to the second circuit. The first switch circuit receives the packet addressed from the first circuit to the second circuit, and outputs the packet from a port connected to the direct path to the second circuit.

Abstract: Described are techniques for storage configuration. Defined are one or more initiator groups each including one or more initiator ports, one or more target groups each including one or more target ports, and one or more storage groups each including one or more devices. A masking view is created where the masking view includes a first of the initiator groups, a first of the target groups, and a first of the storage groups. The masking view indicates which devices of the first storage group are accessible using one or more paths. Each of the one or more paths is specified using an initiator port from the first initiator group and a target port from the first target group.

Abstract: A path creation support apparatus acquires beforehand, from a storage system or a host, either a portion of the parameters required for path creation or parameter decision information which is information for deciding this portion of the parameters. The path creation support apparatus decides the portion of the parameters based on the parameter decision information. Upon receipt of an access path creation start request, the path creation support apparatus sends to the host and the storage system an access path creation indication which specifies the parameters specified together with the access path creation start request, and either the parameters acquired beforehand or the parameters decided based on the parameter decision information acquired beforehand.

Abstract: A non-volatile storage device has first and second controllers that provide external access to non-volatile memory using different protocols. In response to a request from the first controller, the second controller retrieves parameters from the non-volatile memory and provides the retrieved parameters to the first controller. In one embodiment, the device parameters are USB descriptors, which may include a vendor ID, a product ID, a product string, and/or a serial number. The first controller may be a Universal Serial Bus (USB) card reader controller. Examples of the second controller include a Secure Digital (SD) controller, a CompactFlash (CF) controller, a MemoryStick controller, or a different type of controller that is able to provide external access to the non-volatile memory. The first controller provides the device parameters to a host during enumeration of the non-volatile storage device. The device parameters may be used to establish settings for the first controller.

Abstract: An apparatus for providing I/O support to a computer system and a method of use thereof is disclosed. The apparatus in accordance with the present invention includes an internal control element located within the apparatus. The control element allows the apparatus in accordance with the present invention to relinquish ownership of the associated I/O devices for the purpose of being used by another computer. Accordingly, through the use of the apparatus in accordance with the present invention, expensive KVM switches and cabling, along with the accompanying I/O devices, are no longer needed to provide I/O support for computer networks. A first aspect of the present invention provides an apparatus for providing I/O support to a computer system. The apparatus comprises an I/O device and an internal control element coupled to the I/O device for relinquishing ownership of the I/O device from the apparatus to the computer network.