Abstract: In an embodiment, an apparatus is provided that may include an integrated circuit including switch circuitry to determine, at least in part, an action to be executed involving a packet. This determination may be based, at least in part, upon flow information determined, at least in part, from the packet, and packet processing policy information. The circuitry may examine the policy information to determine whether a previously-established packet processing policy has been established that corresponds, at least in part, to the flow information. If the circuitry determines, at least in part, that the policy has not been established and the packet is a first packet in a flow corresponding at least in part to the flow information, the switch circuitry may request that at least one switch control program module establish, at least in part, a new packet processing policy corresponding, at least in part, to the flow information.

Abstract: A method for operating a storage system, including storing data redundantly in the system and measuring respective queue lengths of input/output requests to operational elements of the system. The queue lengths are compared to an average queue length to determine respective performances of the operational elements of the storage system. In response to the average queue lengths and a permitted deviation from the average an under-performing operational element among the operational elements is identified. An indication of the under-performing operational element is provided to host interfaces in the storage system. One of the host interfaces receives requests for specified items of the data directed to the under-performing element, and in response to the indication, some of the requests are diverted from the under-performing operational element to one or more other operational elements of the storage system that are configured to provide the specified items of the data.

Abstract: A system for communicating command parameters between a processor and a memory flow controller is provided. The system makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

Abstract: Disclosed is a computer implemented method and apparatus for queuing I/O requests to a pending queue. The I/O device driver sets a maximum ordered queue length for an I/O device driver coupled to a storage device then receives an I/O request from an application. The I/O device driver determines whether the pending queue is sorted and responds to a determination that the pending queue is sorted, determining if queued I/O requests exceed the maximum ordered queue length. Responding to a determination that the pending queue exceeds the maximum ordered queue length, the I/O device driver adds the I/O request based on a high pointer, and points the high pointer to the I/O request.

Abstract: A network interface adapter includes a network interface and a client interface, for coupling to a client device so as to receive from the client device work requests to send messages over the network using a plurality of transport service instances. Message processing circuitry, coupled between the network interface and the client interface, includes an execution unit, which generates the messages in response to the work requests and passes the messages to the network interface to be sent over the network. A memory stores records of the messages that have been generated by the execution unit in respective lists according to the transport service instances with which the messages are associated. A completion unit receives the records from the memory and, responsive thereto, reports to the client device upon completion of the messages.

Abstract: A disk drive is disclosed having a disk, a head actuated over the disk, a buffer memory for storing control routine op codes and control routine data, and a microprocessor for receiving the control routine op codes and control routine data. Control circuitry within the disk drive services an access request generated by the microprocessor by accessing the buffer memory, and monitors at least one interrupt. If the interrupt occurs while servicing the access request, the control circuitry enables the microprocessor to execute an interrupt service routine corresponding to the interrupt. Enabling the microprocessor to execute the interrupt service routine rather than wait for the access request reduces the latency in servicing the interrupt.

Abstract: A computer-implemented method, system and computer program product for managing USB ports on blades in a blade center are presented. A set of remotely-transmitted instructions causes a multiplexer to physically disconnect one or more selected USB ports on a blade. In one embodiment, the same one or more selected USB ports are also software-disabled by a USB software-based controller.

Abstract: In a system in which an information processing apparatus and a peripheral are connected to each other. Initially, the information processing apparatus transmits, to the peripheral, a request to use a service provided by the peripheral. The peripheral determines whether to grant use permission to the received request, and notifies the information processing apparatus which has transmitted the request of the determination result. The peripheral stores information associated with the information processing apparatus to which use permission is granted in response to the request. The information processing apparatus then receives, from the peripheral, a response to the request.

Abstract: Arbitration of IO accesses and band control based on the priority of virtual servers is enabled while curbing performance overhead during IO sharing among the virtual servers. A virtual machine system includes a CPU, a memory, a hypervisor that generates plural virtual servers, and an IO controller that controls an IO interface. The IO controller includes: a DMA receiving unit that receives DMA requests from the IO interface; a decoder that decodes received DMA requests and locates the corresponding virtual servers; a DMA monitoring counter that monitors DMA processing status for each of the virtual servers; a threshold register set in advance for each of the virtual servers; and a priority deciding unit that compares the DMA monitoring counter and the value of the threshold register, and based on processing priority obtained as a result of the comparison, decides the priority of processing of the received DMA requests.

Abstract: An apparatus, system, and method are disclosed for enqueue prioritization. The apparatus for enqueue prioritization is provided with a plurality of modules configured to functionally execute the steps of holding one or more queued requests in a queue, sorting the queued requests according to a first priority identifier associated with each of the queued requests, and assigning a second priority identifier to a delayed request in response to a determination that the delayed request has resided in the queue for a predetermined length of time, wherein the second priority identifier indicates a higher priority than the first priority identifier indicates. These modules in the described embodiments include a queue module, a sorting module, and a reassignment module.

Abstract: There is provided a technique of accessing a memory of a processor from a peripheral device, thereby the security is ensured while efficiency is being pursued. An address converter 14 includes an address conversion table for converting an effective address into a physical address. The address conversion table stores the effective address to which an area in a memory of a processor unit 10 is allocated to each peripheral device 30 and identification information of an access source to which access permission is given, in association with each other. When the peripheral device 30 accesses, the address converter 14 determines to permit access to the effective address under the condition that the device identification information, included in an access request packet, by which the peripheral device 30 can be uniquely identified, matches the identification information of the access source corresponding to the effective address, in the address conversion table, designated by the access request packet.

Abstract: An input and output (IO) scheduler dispatches a first IO request from a first IO queue during a first dispatch cycle and dispatches a second IO request from a second IO queue during a second dispatch cycle to one or more disks, where the first IO request is the last remaining IO request in the first queue and the second IO request is the first overall IO request in the second queue. The first and second IO requests are selected from multiple IO requests received from one or more clients for accessing the one or more disks. A seek time monitor measures disk seek time (IO queue switch time) incurred between the first IO request and the second IO request, and determines whether the first IO request and the second IO request belong to the same group. The disk seek time is attributed to a group associated with the first IO request and the second IO request, if the first IO request and the second IO request belong to the same group.

Abstract: A method of bridging a plurality of buses within a bus bridge can include determining whether a queue of the bus bridge includes a transaction request directed to a restricted address range and, for each received transaction request, determining whether an address to which the transaction request is directed is within the restricted address range. Each transaction request received by the bus bridge can be selectively rejected according to whether the address to which the transaction request is directed is within the restricted address range and whether the queue includes a transaction request directed to the restricted address range.

Abstract: A microprocessor system in which an array of processors communicates more efficiently through the use of a worker mode function. Processors that are not currently executing code remain in an inactive but alert state until a task is sent to them by an adjacent processor. Processors can also be programmed to temporarily suspend a task to check for incoming tasks or messages.

Abstract: Embodiments of the present invention provide a resource management mechanism to monitor the availability of resources, detect the cause of a rejection, distinguish between different types of rejections, and manage the different types accordingly. For example, a queue manager in accordance with embodiments of the invention may be able to classify rejected requests, for example, as either a “long reject” or a “short reject” based on the cause of the rejection and the amount of time the rejection conditions are expected to remain valid. A short reject request may be rescheduled in an appropriate service queue, while a long reject request may be suspended in a reject queue. Other features are described and claimed.

Abstract: A method and system for providing quality of service to a plurality of hosts accessing a common resource is described. According to one embodiment, a plurality of IO requests is received from clients executing as software entities on one of the hosts. An IO request queue for each client is separately managed, and an issue queue is populated based on contents of the IO request queues. When a host issue queue is not full, a new IO request is entered into the host issue queue and is issued to the common resource. A current average latency observed at the host is calculated, and an adjusted window size is calculated at least in part based on the current average latency. The window size of the issue queue is adjusted according to the calculated window size.

Abstract: An apparatus for maintaining a limit value of a resource for use in a concurrent limit checking system comprising: a resource having an associated limit value; a plurality of request handlers having access to a plurality of sub-limit values, wherein the sub-limit values when summed equal the limit value and wherein each request handler is operable to check a request value of a request for consuming the resource against its associated sub-limit value, in order to determine whether the request can be satisfied. The apparatus comprises a coordinator, responsive to the first request handler determining that the first request cannot be satisfied, for generating a coordination request comprising a coordination request value required to satisfy the first request, a receiver for receiving a coordination response from the second request handler; and an updater for updating the sub-limit values in accordance with the coordination request value.

Abstract: Mechanisms for communicating with a processor event facility are provided. The mechanisms make use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

Abstract: Methods, systems, and computer program products for performing an input/output (I/O) operation that includes a virtual drain. According to one aspect, the subject matter described herein includes a method for performing an input/output operation that includes a virtual drain. The method includes receiving a request to perform a consistent operation involving a storage entity, and in response to receiving the request: arresting write requests to the storage entity; performing a virtual drain, where performing a virtual drain includes identifying, and indicating as deferred, pending writes to the storage entity; performing the consistent operation; releasing write requests to the storage entity; and processing each deferred write using information that is associated with the write and that describes the context in which the write request was accepted.

Abstract: The present invention relates to managing I/O requests in a storage system. By dynamically changing the scheduling parameters to achieve optimal turn around time for I/O requests pending for processing at a component in the storage system. The scheduling parameters are changed based on a feedback mechanism. The turn around time of the I/O request are calculated as the ratio of I/O request processing rate and the average number of I/O requests in the component.

Abstract: A cache managing unit creates a list of elements corresponding to each data block arranged based on a priority of writing data blocks to a magnetic disk apparatus, and when a group of elements corresponding to data blocks to be written to the same magnetic disk apparatus exists, provides a link connecting elements at both ends of the group. A write control unit searches, upon selecting a data block for writing, elements belonging to the list in descending order of priority, and if a link is set at an element corresponding to a data block to be written to a magnetic disk that cannot perform a writing, follows the link to search a subsequent element.

Abstract: A network apparatus is provided that is capable of requiring a reservation for an access right to a peripheral device that is not yet connected to the network apparatus from one of the terminals on a network. A server (network apparatus) may receive a reservation command and a sender identifier (ID) from one of the terminals on the network that requests to reserve an access right for a peripheral device that is not yet connected to the server. In a case where a new connection of a peripheral device is detected, the server allows the terminal identified by the sender ID that accompanied the reservation command to access the peripheral device. While the reservation is established, access to the detected peripheral device from senders other than the identified terminal is rejected.

Abstract: Disclosed herein are methods and apparatuses for requesting and obtaining data, in which time information is generated by use of a first device, and a data request command requesting data output by a second device is generated at a time point indicated by the time information. The generated data request command is transmitted, wherein the data request command includes the time information.

Abstract: A data transfer control device in accordance with an exemplary aspect of the present invention includes a first communication unit that processes data transfer with a peripheral device, and a second communication unit that processes data transfer with a host device, wherein one of the first and second communication units serves as a preferential communication unit whose data transfer should have a high priority, and another of the first and second communication units serves as a non-preferential communication unit, when the data transfer is being performed in the preferential communication unit, the preferential communication unit notifies the non-preferential communication unit that the data transfer is being performed, and when the non-preferential communication unit is being notified that the data transfer is being performed from the preferential communication unit, the non-preferential communication unit puts the data transfer in the non-preferential communication unit on hold.

Abstract: Methods and apparatus for configurably limiting performance of an I/O controller device in processing of I/O requests. A performance monitor and control module in the I/O controller device monitors performance of the I/O request processing module and limits its processing to assure that maximum performance threshold values are not exceeded. In one embodiment, the performance monitoring may average performance over one or more periods of time and may provide a moving average window to determine the performance of the I/O controller device. The measured performance may determine a variety of performance measures each of which may be compared against one or more corresponding maximum performance threshold values. Requests that cannot be processed during a present period of time are delayed until a subsequent period of time to thereby limit performance of the I/O controller device.

Abstract: A first-in-first-out (FIFO) queue optimized to reduce latency in dequeuing data items from the FIFO. In one implementation, a FIFO queue additionally includes buffers connected to the output of the FIFO queue and bypass logic. The buffers act as the final stages of the FIFO queue. The bypass logic causes input data items to bypass the FIFO and to go straight to the buffers when the buffers are able to receive data items and the FIFO queue is empty. In a second implementation, arbitration logic is coupled to the queue. The arbitration logic controls a multiplexer to output a predetermined number of data items from a number of final stages of the queue. In this second implementation, the arbitration logic gives higher priority to data items in later stages of the queue.

Abstract: A storage system, consisting of one or more data storage logical units (LUs) formed in physical media. The LUs are adapted to receive command and respond to the commands to store and recall data. The storage system further includes a plurality of ports, each port being adapted to maintain a respective LU command queue for each of the LUs, such that upon receiving a command directed to one of the LUs, the port places the received command in the respective LU command queue. The port converts the received command to one or more converted commands at least some of which are directed to the physical media of the one of the LUs. The port then conveys the commands directed to the physical media in an order determined by the respective LU command queue.

Abstract: A mechanism for communicating instructions and data between a processor and external devices are provided. The mechanism makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

Abstract: The invention relates to management of a plurality of I/O requests in a storage system. The host interface module is configured to receive a plurality of I/O request which includes an associated priority; create an I/O request queue for each associated priority; define a threshold value for the queue length for each of the plurality of I/O request queues; and determine if the queue length for one of the plurality of the I/O request queue corresponding to the associated priority is less than the defined threshold value for the queue length for the one of the plurality of the I/O request queues. If the queue length of the one of the plurality of I/O request queues is more than the defined threshold value for the queue then the host interface module is further configured to rejecting the I/O request and sending a queue full message; wherein the threshold value for the queue length is based on the processing rate of the I/O requests in the plurality of the I/O request queues.

Abstract: A processor of an apparatus in an example upon a failure of an earlier attempt to directly acquire ownership of an access coordinator for a resource shared with one or more additional processors, locally determines an amount to delay a later attempt to directly acquire ownership of the access coordinator. Upon a failure of the later and/or a subsequent attempt to directly acquire ownership of the access coordinator the processor would enter into an indirect waiting arrangement for ownership of the access coordinator.

Abstract: This is directed to methods and systems for handling access requests from a device to a host. The device may be a device that is part of the host, such as an HBA, an NIC, etc. The device may include a processor which runs firmware and which may generate various host access requests. The host access requests may be, for example, memory access requests, or DMA requests. The device may include a module for executing the host access requests, such as a data transfer block (DXB). The DXB may process incoming host access requests and return notifications of completion to the processor. For various reasons, the processor may from time to time issue null or zero length requests. Embodiments of the present invention ensure that the notifications of completion for all requests, including the zero length requests, are sent to the processor in the same order as the requests.

Abstract: A method and mechanism for managing requests to a resource. A request queue receives requests from multiple requestors and maintains a status for each requestor indicating how many requests the requestor has permission to issue. Upon initialization, the request queue allots to each requestor a predetermined number of “hard” entries, and a predetermined number of “free” entries. Un-allotted entries are part of a free pool of entries. If a requestor has an available entry, the requestor may submit a request to the request queue. After receiving a request, the request queue may allot a free pool entry to the requestor if the free pool currently has entries available. Upon de-allocation of a queue entry, if the entry corresponds to a hard entry, then the hard entry is re-allotted to the same requestor. If the entry is a free entry, the entry is made available and a free pool counter is incremented.

Abstract: Provided are a method, system, and article of manufacture for using priority to determine whether to queue an Input/Output (I/O) request directed to storage. A maximum number of concurrent requests directed to a storage is measured. The measured maximum number of concurrent requests is used to determine a threshold for a specified priority. Subsequent requests of the specified priority directed to the storage are allowed to proceed in response to determining that a current number of concurrent requests for the specified priority does not exceed the determined threshold for the specified priority. Subsequent requests directed to the storage having a priority greater than the specified priority are allowed to proceed. Subsequent requests directed to the storage having the specified priority are queued in a queue in response to determining that the current number of concurrent requests for the specified priority exceeds the overall threshold.

Abstract: This invention provide a data processor capable of multiplexing data transfers with desired data transfer characteristics guaranteed, without multiplexing buses. The data processor includes: a transfer path that mutually connects plural processors and plural transfer element circuits such as memory; an arbitration circuit that controls data transfer in the transfer path; and a control register that defines the priority and minimum guaranteed bandwidth of data transfer. The arbitration circuit decomposes data packets sent from plural data transfer sources into subunits, and reconstructs plural data packets having the same data transfer target, based on priority and minimum guaranteed bandwidth stored in a control register. Thereby, the one reconstructed data packet can include subunits of plural data packets from transfer sources having different priorities, and data amounts of subunits contained in it can satisfy minimum guaranteed bandwidth of data transfer.

Abstract: Apparatus and method for command queue management of back watered requests. A selected request is released from a command queue, and further release of requests from the queue is interrupted when a total number of subsequently completed requests reaches a predetermined threshold.

Abstract: A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a fixed port address. The DMA command messages are arranged in a first-in first-out (FIFO) queue, in the order in which they are received. The DMA command messages are supplied to a DMA controller from the FIFO queue, and in response to the DMA command message, data transfer operation are managed by the DMA controller. Following the completion of each data transfer operation, a transfer complete message indicating completion is sent. In one aspect, DMA command messages are arranged in a plurality of parallel FIFO queues, and CD sets are stored in a plurality of context memories, where each context memory is associated with a corresponding FIFO queue.

Abstract: Apparatus and methods for improved tree data structure management in a storage controller. A tree assist circuit coupled with a tree memory is provided for integration in a storage controller. I/O processors of the storage controller transmit requests to the tree assist circuit to create, modify, and access tree data structures stored in the tree memory. In one exemplary embodiment, the tree assist circuit is adapted to manage AVL trees. The tree data structures may be used by the I/O processors of the storage controller to manage region lock requests, cache-line lookup request, and other storage management functions of the controller. The I/O processors of the controller may comprise suitable programmed general-purpose processors and/or fast-path I/O request processor circuits.

Abstract: There is provided a transfer apparatus having a bridge that transfers a transaction between a first and a second bus, and a data transfer unit that performs a data transfer by DMA between the first and second bus. The transfer apparatus controls a transfer sequence of transaction transfers by the bridge and data transfers by the data transfer unit, in which transaction transfers by the bridge are based on bus sequencing rules and data transfers by the data transfer unit are based on a data transfer activation condition.

Abstract: A method for managing IO requests from a virtual machine to access IO resources on a physical machine includes determining a request priority associated with an IO request. The IO request is placed in an appropriate queue in response to determining the request priority.

Abstract: In certain, currently available data-storage systems, incoming commands from remote host computers are subject to several levels of command-queue-depth-fairness-related throttles to ensure that all host computers accessing the data-storage systems receive a reasonable fraction of data-storage-system command-processing bandwidth to avoid starvation of one or more host computers. Recently, certain host-computer-to-data-storage-system communication protocols have been enhanced to provide for association of priorities with commands. However, these new command-associated priorities may lead to starvation of priority levels and to a risk of deadlock due to priority-level starvation and priority inversion. In various embodiments of the present invention, at least one additional level of command-queue-depth-fairness-related throttling is introduced in order to avoid starvation of one or more priority levels, thereby eliminating or minimizing the risk of priority-level starvation and priority-related deadlock.

Abstract: An interface controller is connected to a host apparatus and a memory, and receiving multiple responses to one request. The interface controller includes a packet generation unit which adds header data to a request issued by the host apparatus to generate a request packet and outputs the request packet to the memory, a receive buffer which stores a response packet with respect to the request packet, a protocol generation unit which generates a response according to a prescribed protocol based on the response packet stored in the receive buffer, and outputs the response to the host apparatus, a maximum division number calculation unit which calculates a maximum division number of the request issued by the host apparatus, and a request issue control unit which gives a request issue permission to the host apparatus based on the maximum division number calculated by the maximum division number calculation unit, a maximum division number of processed request and a maximum division number of processed response.

Abstract: A method for communicating instructions and data between a processor and external devices are provided. The method makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

Abstract: A method and an apparatus that synchronize an application state in a client with a data source in a backend system in an asynchronous manner are described. A response is sent to the client based on a priority determined according to a history of received update requests. When a notification message from a data source in a backend system is received, an update request is selected from a plurality of update requests currently pending to be served according to the priority associated with each update request. A response is sent to the client over a network corresponding to the selected update request. The response includes state updates according to the changes in the data source and the current application state in the corresponding client.

Abstract: An information processing apparatus according to an embodiment of the present invention includes: a CPU; a plurality of peripheral devices connected to the CPU through a bus; and a peripheral access protection setting unit storing access protection information representing whether an access to each of the peripheral devices is permitted or inhibited in accordance with a task to be performed by the CPU, wherein an access by the CPU to the peripheral devices is limited based on the access protection information and address information of the peripheral device.

Abstract: An apparatus and method of speculatively decoding non-memory read commands. A command register and decoder, within the apparatus, compares high-order command bits provided on a serial bus with corresponding bits of recognized non-memory read commands. An early non-memory read command is asserted when incoming command bits match a non-memory read command. Early responsive data is prepared speculatively during the time the remainder of command bits is received and decoded. A determination of command speculation correctness is made after receipt of the full command. If the full command received is not the speculated non-memory read command, the prepared data is discarded. Earlier prepared data is produced as the subsystem response if the full command matches the speculative non-memory read command. For incoming commands with operands, such as an address, the same speculative determination based on high-order operand bits is performed.

Abstract: A method and system for optimizing network I/O throughput is disclosed. In one embodiment, a method for optimizing an input/output (I/O) throughput for a storage network comprises measuring a service time for a storage device of the storage network in completing an I/O request serviced by a storage driver. The method also comprises determining a status of an I/O performance between the storage driver and the storage device by comparing the service time with an expected service time for the storage device in completing the I/O request, where the expected service time is calculated based on a type of the storage device and a size of the I/O request. The method further comprises adjusting a maximum queue depth associated with the storage device based on the status of the I/O performance.

Abstract: In some embodiments, a chip includes a link interface, monitoring circuitry to provide an activity indicator that is indicative of activity of the chip, and scheduling circuitry to schedule commands. The chip also includes mode selection circuitry to select a first mode or a second mode for the scheduling circuitry depending on the activity indicator, wherein in the first mode the scheduling circuitry schedules certain commands as separate single commands and in the second mode the scheduling circuitry schedules at least one consolidated command to represent more than one of the separate single commands. Other embodiments are described.

Abstract: The present disclosure relates to a method for enabling a virtual processing unit to access a peripheral unit, the virtual processing unit being implemented by a physical processing unit connected to the peripheral unit, the method comprising a step of transmitting to the peripheral unit a request sent by the virtual processing unit to access a service provided by the peripheral unit, the access request comprising at least one parameter and an identifier of the virtual unit, the method comprising steps, executed by the peripheral unit after receiving an access request, of allocating a set of registers to the virtual unit identifier received, storing the parameter received in the register set allocated, and when the peripheral unit is available for processing a request, selecting one of the register sets, and triggering a process in the peripheral unit from the parameters stored in the selected register set.

Abstract: A method, apparatus and system for transmitting multiple I/O requests from an input/output processor (IOP) to an I/O device. The IOP is configured with multiple I/O threads, each having a corresponding active I/O, that allow a queuing thread to coordinate the transfer of multiple I/O requests at a time from the output of the device queue to the active I/Os and their I/O threads. The queuing thread and a promotion algorithm are configured to consider the promotion of one or more I/O requests ahead of other I/O requests in the device queue, based on a set of promotion requirements. After processing by the I/O threads, multiple I/O requests are transferred at a time from the multiple active I/Os to the I/O device. Promotion of I/O requests based on the promotion requirements improves processing efficiency by making better use of the multiple I/O thread processing resources.

Abstract: Disclosed is a computer implemented method and apparatus for queuing I/O requests to a pending queue. The I/O device driver sets a maximum ordered queue length for an I/O device driver coupled to a storage device then receives an I/O request from an application. The I/O device driver determines whether the pending queue is sorted and responds to a determination that the pending queue is sorted, determining if queued I/O requests exceed the maximum ordered queue length. Responding to a determination that the pending queue exceeds the maximum ordered queue length, the I/O device driver adds the I/O request based on a high pointer, and points the high pointer to the I/O request.