Abstract: A mechanism is presented for processing conditional payment requests in an electronic financial transaction system. In particular, the mechanism provides for the handling of concurrent conditional payment events. The status of a payment condition may be categorized into three categories, and a priority assigned relative to the category. In this way, concurrent events may be prioritized according to their respective categories. Events may then be executed in order of assigned priority.

Abstract: A data transfer device connected to data transfer destination via serial attached SCSI includes a plurality of buses. A queuing unit queues processing requests associated with data transfer. A transferring unit obtains data transferred associated with processing request upon receiving processing request and transfer obtained data to the destination by using one of the buses. A transmitting unit transmits processing request queued in the queuing unit to transfer unit. A detecting unit detects the number of processing requests. A determining unit determines whether the number of processing requests detected by the detecting unit is smaller than the number of buses. If the determining unit determines the number of processing requests is smaller than the number of buses, the transmitting unit divides the processing requests into a plurality of processing requests in accordance with the number of buses and the number of processing requests.

Abstract: The present invention provides a method that enables application instances to pass block mode storage requests directly to a physical I/O adapter without run-time involvement from the local operating system or hypervisor. Specifically, a mechanism for providing and using a linear block address (LBA) translation protection table (TPT) to control out of user space I/O operations is provided. In one aspect of the present invention, the LBATPT includes an adapter protection table that has entries for each portion of a storage device. Entries include access control values which identify whether the entry is valid and what access type operations may be performed on a corresponding portion of a storage device. I/O requests may be checked against these access control values to determine if an application instance that submitted the I/O requests may access the LBAs identified in the I/O requests in the manner requested.

Abstract: A request control apparatus and a request control method are configured such that when an A type request that is an overtaking acceptable request allowed to overtake and to be overtaken among the other requests is turned to a retry matter on a pipeline, a request-order control unit performs an information renewal such that the A type request is rearranged to a place immediately preceding a B type request that is an overtaking inhibited request inhibited to overtake or to be overtaken among the other requests, and a request fetching unit fetches requests from ports by using the information renewed by the request-order control unit. Moreover, the request-order control unit is configured to perform request order control per request source.

Abstract: In response to multiple data transfer requests from an application, a data definition (DD) chain is generated. The DD chain is divided into multiple DD sub-blocks by determining a bandwidth of channels (BOC) and whether the BOC is less than the DD chain. If so, the DD chain is divided by the available DMA engines. If not, the DD chain is divided by an optimum atomic transfer unit (OATU). If the division yields a remainder, the remainder is added to a last DD sub-block. If the remainder is less than a predetermined value, the size of the last DD sub-block is set to the OATU plus the remainder. Otherwise, the size of the last DD sub-block is set to the remainder. The DD sub-blocks are subsequently loaded into a set of available DMA engines. Each of the available DMA engines performs data transfers on a corresponding DD sub-block until the entire DD chain has been completed.

Abstract: Queuing command information is stored in a content addressable memory (CAM) where a queuing command for a first queue is received, the CAM is examined to determine if commands for the first queue are present, and if commands for the first queue were found to be present, information is stored in a linked list for the received command in multiple CAM entries.

Abstract: According to one aspect of the present invention, a method is provided in which a request submitted by a user via a user-interface is sent from a client to a server for processing. Upon being notified by the server that the request may take a long time to process, inform the user of the status of the request. The user is informed of the progress of the request based upon progress information received from the server.

Abstract: A method and system for enforcing ordering rules for transactions are presented. The method and system generates transaction clump tags for each transaction before the transactions are stored in various type specific transaction queues. A transaction clump tag decoding unit decodes the transaction clump tag to recover temporal information regarding the transaction to avoid violations of the ordering rules.

Abstract: The present invention is a rotating priority queue manager. A rotating priority queue manager in accordance with the present invention may include a plurality of source data channels, a corresponding plurality of processing resources, and an arbitrating interface directing the flow of data from the source channels to the processing resources where the data must flow over a shared data path. The plurality of processing resources may comprise any system of parallel processors where the servicing of input data must be carried out in a manner where there the maximum latency for processing a given data channel is determinable, the arbitration between channels is equal, no input channel may prevent another channel from being serviced, and lower priority processing resources are not prohibited from receiving input data if higher priority processing resources are not currently available or if higher priority data is not currently available.

Abstract: Embodiments include storing graphics instructions at addresses in a memory in an original order, and storing in the memory pointers associated with each instruction pointing to the addresses of the instructions in the original order. A first pointer associated with a first graphics instruction may then be moved from pointing to a first address of the first graphics instruction to point to a second address of a second graphics instruction. Likewise, a second pointer associated with the second graphics instruction may be moved from pointing to the second address to point to the first address by accessing the first pointer before moving the first pointer to determine that the second pointer is to point to the first address (e.g., the address the first instruction points to before being moved). Afterwards, the instructions may be re-ordered into an optimized order for compiling, by switching them to different addresses according to the pointers.

Abstract: A storage control device 2A includes a host interface control unit 3, a storage control firmware A, and electrically rewritable non-volatile memory 7 and, using non-volatile memory 7, stores necessary information during exchange of an activation program of the storage control firmware A, and using the information exchanges the activation program without disconnection to a host 1 and without erroneous response to a command from the host 1.

Abstract: A network storage controller for transferring data between a host computer and a storage device, such as a redundant array of inexpensive disks (RAID), is disclosed. The network storage controller includes at least one channel interface module which is adapted to be connected to the host computer and storage device. The channel interface module is connected to a passive backplane, and selectively transfers data between the host computer and storage device and the passive backplane. The network storage controller also includes at least one controller memory module, attached to the passive backplane. The controller memory module communicates with the channel interface module via the passive backplane, and processes and temporarily stores data received from the host computer or storage device. In applications where redundancy is required, at least two controller memory modules and at least two channel interface modules are used.

Abstract: A method includes receiving a first memory access request from a first device during a first interval. The first memory access request is to access a first page of a multiple-page memory. The method further includes receiving a second memory access request from the first device during a second interval subsequent to the first interval and receiving a third memory access request from a second device during the second interval. The method additionally includes preferentially selecting the second memory access request over the third memory access request for provision to the multiple-page memory if an indicator indicates the second memory access request is expected to access the first page of the multiple-page memory.

Abstract: A method, apparatus, and computer program product includes identifying a plurality of memory transactions to be sent over a memory bus to a memory having a plurality of memory banks, each memory transaction addressed to one of the memory banks, the memory bus incapable of transmitting the plurality of memory transactions simultaneously; identifying a plurality of bank readiness signals, each bank readiness signal indicating the readiness of one of the memory banks to accept a memory transaction; and selecting one of the memory transactions for transmission over the memory bus based on the bank readiness signals.

Abstract: A computer implemented method, an apparatus, and a computer usable program product for tracking device driver requests in a data processing system is provided. A controller receives a request from a device driver. The controller associates a timestamp and at least one pointer to the request, wherein the timestamp indicates a time the request is received by an operating system. The controller then links the request from the device driver in a queue in the operating system, wherein the pointer identifies the location of the request in the queue.

Abstract: A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor-also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.

Abstract: A memory module includes a memory hub coupled to several memory devices. The memory hub is also coupled to receive a memory packet from a system controller containing a memory hint indicative of the subsequent operation of the memory devices. The memory module uses the hint to adjust the operation of the memory module, such as the number of pages to remain open or cache lines to be fetched.

Abstract: A content addressable memory (CAM) includes a linked list structure for a pending queue to order memory commands for maximizing memory channel bandwidth by minimizing read/write stalls due to read-modify-write commands.

Abstract: In general, in one aspect, the disclosure describes accessing multiple memory access commands from a one of multiple memory access command queues associated with, respective, banks of a Random Access Memory (RAM) and selecting one of the commands based, at least in part, on the memory access operations identified by the commands and the memory access operation of a previously selected memory access commands.

Abstract: An apparatus and method for accessing a data item from a storage system having a plurality of data storage devices are disclosed. I/O operation requests are submitted to multiple data storage devices for each data item to be accessed. The I/O operation requests are issued to copies of the data items that reside on a plurality of data storage devices. More I/O operation requests are submitted than the number of data items that are to be accessed, written, or updated.

Abstract: A method and apparatus for enqueuing and dequeuing packets to and from a shared packet memory, while avoiding collisions. An enqueue process or state machine enqueues packets for a communication connection (e.g., channel, queue pair, flow). A dequeue process or state machine operating in parallel dequeues packets and forwards them (e.g., to an InfiniBand node). Packets are stored in the shared packet memory, and status/control information is stored in a control memory that is updated for each packet enqueue and packet dequeue. Prior to updating the packet and/or control memory, each process interfaces with the other to determine if the other process is active and/or to identify the other process' current communication connection. If the enqueue process detects a collision, it pauses (e.g., for a predetermined number of clock cycles). If the dequeue process detects a collision, it selects a different communication connection to dequeue.

Abstract: A method and system for processing an input/output request on a multiprocessor computer system comprises pinning a process down to a processor issuing the input/output request. An identity of the processor is passed to a device driver which selects a device adapter request queue whose interrupt is bound to the identified processor and issues the request on that queue. The device accepts the request from the device adapter, processes the request and raises a completion interrupt to the identified processor. On completion of the input/output request the process is un-pinned from the processor. In an embodiment the device driver associates a vector of the identified processor with the request and the device, on completion of the request, interrupts the processor indicated by the vector.

Abstract: An interface controller connected to a read request device which performs a read request to a storage device stored with data, includes a receiving buffer which stores a read response of said storage device with respect to the read request sent from said read request device; and a control unit which performs read request authorization to said read request device on the basis of a capacity of said receiving buffer, a read request size and a read response size.

Abstract: A system and method for communicating command parameters between a processor and a memory flow controller are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

Abstract: An apparatus for maintaining a limit value of a resource for use in a concurrent limit checking system comprising: a resource having an associated limit value; a plurality of request handlers having access to a plurality of sub-limit values, wherein the sub-limit values when summed equal the limit value and wherein each request handler is operable to check a request value of a request for consuming the resource against its associated sub-limit value, in order to determine whether the request can be satisfied. The apparatus comprises a coordinator, responsive to the first request handler determining that the first request cannot be satisfied, for generating a coordination request comprising a coordination request value required to satisfy the first request, a receiver for receiving a coordination response from the second request handler; and an updater for updating the sub-limit values in accordance with the coordination request value.

Abstract: A method for processing a first input/output (I/O) request on a network attached storage (NAS) device that includes receiving the first I/O request from a source by the NAS device, placing the first I/O request in an I/O queue associated with the NAS device, wherein the first I/O request is placed in the I/O queue based on a priority of the first I/O request using a remote storage access protocol, and when the first I/O request is associated with the highest priority in the I/O queue, determining whether a bandwidth associated with the source of the first I/O request is exceeded, processing the first I/O request if the bandwidth associated with the source of the first I/O request is not exceeded, and placing the first I/O request in sleep mode if the bandwidth associated with the source of the first I/O request is exceeded.

Abstract: A device comprises a communication module connected to an external data link The communication module is arranged to receive a plurality of read and write requests from the data link, and a logic module connected to the communication module. The communication module is arranged to transmit at least some of the plurality of read and write requests to the logic module, the logic module being arranged to process the read and write requests in turn, to detect when the processing of a request is stalled, to execute a decision logic in response to the detection of a stalled request, and to process either the same request or a different request according to the output of the decision logic.

Abstract: In accordance with a computer program product, apparatus and a method there is provided a redundant network wherein a host computer operates with a plurality of storage devices by monitoring conditions of the multipath storage network and controlling a storage multipath device driver in conjunction with an associated storage multipath device input/output (I/O) pending queue to increase I/O throughput to a storage device driver, such as a disk device driver, when I/O demand increases, and to decrease I/O throughput to the storage device driver in the event of an I/O error condition.

Abstract: A system and method for dynamically accessing memory under normal operating conditions without interrupting computer system clocks that are otherwise executing. At least a memory access mode and a memory address(es) are scanned into a control scan chain from a maintenance system. When the scan is complete, the information is collectively transferred to an access register bank. Based on the control signals, a selection multiplexer selects the information from the control scan chain provided by the maintenance system as opposed to standard signals generated by the computer system. Memory control input signals are generated in response to a clock trigger signal, and the read or write data transfer is initiated.

Abstract: A conventional storage system immediately executes a received I/O command because of importance of response time. Provided is a storage system which is coupled to a network and executes an I/O command received from at least one host computer through the network, in which: the storage system holds judgment information including predetermined conditions set therein, and upon reception of the I/O command, the processor judges whether the received I/O command satisfies the predetermined conditions or not based on the judgment information, queues a plurality of I/O commands that satisfy the predetermined conditions, rearranges the plurality of queued I/O commands, executes the plurality of queued I/O commands in a rearranged order, and executes I/O commands that do not satisfy the predetermined conditions in a received order.

Abstract: On a dominant logical unit provided by a mass-storage device, hot spare disks are employed to create a much larger, disk-based time-ordered WRITE-request buffer that spans, in one embodiment, both electronic memory and hot spare disks. The much larger time-ordered WRITE-request buffer in the modified dominant logical unit allows for storing WRITE requests in time order for a much longer period of time during communications failure between the dominant logical unit and remote-mirror logical unit than in the current techniques that employ only an electronic-memory-based time-ordered WRITE-request buffer. On the remote-mirror logical unit, mass-storage space is provided for an alternate logical unit that can be resynchronized with the dominant logical unit following restoration of communications between the dominant logical unit and remote-mirror logical unit.

Abstract: A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of access (e.g. read/write, instruction/data, burst/non-burst, etc.), sequence or order of accesses, address being accessed (e.g. which address range is being accessed or which device is being accessed), the bus master requesting retraction (in an, e.g., multimaster system), or any combination thereof. A bus arbiter may also selectively retract currently pending access requests in favor of a subsequent access request based on one or more characteristics of the currently pending access request or the subsequent access request. These characteristics may include any of those listed above, priorities of the requesting masters (e.g. a priority delta between requesting masters), other attributes of the requesting masters, or any combination thereof.

Abstract: Methods and systems for keeping two independent busses coherent that includes writing data from an Input/Output (I/O) controller to a memory. The I/O controller sends the data to the memory via a first bus connected between a first port of a memory controller and the I/O controller. A tag is sent from the I/O controller, after the data, via the first bus through the first port. The tag is received by the memory controller. Completion status of the data write is requested from the I/O controller by a processing unit. The request is sent to the I/O controller via a second bus connected between a second port of the memory controller and the I/O controller. The I/O controller waits for a tag acknowledgment from the memory controller before providing notification to the processing unit that the data write has completed. Therefore, the first bus and the second bus are coherent.

Abstract: Systems, methods, and computer products that improve the performance of computer-implemented I/O operations for complex applications, such as a database, that are ported to target computer systems that are not tailored to support the high-performance services that may benefit applications. Complex applications, such as a database, often manage I/O access operations by a caching mechanism that is tailored to the needs of the application. When porting an application to a target computer system that does not support certain I/O access features, I/O performance of the application may be limited. The present invention may be implemented by introducing specialized I/O access features that are tailored to enhance I/O access performance for complex applications, such as a database.

Abstract: A controller for a random access memory includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues.

Abstract: A management agent ME1 of a target T1 receives a request of log-in from an initiator of interest and determines whether or not a number of initiators that currently log in the target T1 reaches a predetermined allowable number of simultaneous log-in (steps S210 and S212). In the case of an affirmative answer, the management agent ME1 reads an ordinal number of precedence ‘n’ allocated to a GUID of the initiator of interest from a queue (step S213) and reads a time constant mapped to the input ordinal number of precedence ‘n’ from a time constant table (step S214). The management agent ME1 subsequently sends a status packet, which includes a log-in error status and the time constant, to the initiator of interest (step S216). The initiator of interest receives the status packet, reads the time constant included in the input status packet, and outputs another request of log-in to the target T1 at a timing specified by the time constant.

Abstract: A printer has a queue for queuing a queued execution command, an immediate execution agent for executing a write command, and a queued execution agent for executing a read command. The immediate execution agent immediately executes the received write command, and writes data in a host. The queued execution agent picks up a read command from the queue, and reads out data from the host. The host appends a data transfer request from the printer to a queue, issues a write command to the printer on the basis of that data transfer request, and issues a read command to the printer on the basis of a print data transmission request or the like from an application. Independent full-duplex channels can be provided in two directions. Also, a write command can be immediately processed.

Abstract: Remotely obtaining exclusive control of a device by remotely establishing communication with the device over a network, requesting to obtain remote exclusive control of the device's capabilities, and determining whether remote exclusive control of the device's capabilities can be obtained based on whether or not another user already has exclusive control of the device's capabilities. In a first case where it is determined that remote exclusive control can be obtained, authenticating a user requesting to obtain remote exclusive control of the device's capabilities, providing the user remote exclusive control of the device's capabilities after the user has been authenticated, and temporarily deferring requests by users other than the user who has obtained remote exclusive control to perform operations utilizing the device's capabilities during a period in which the user maintains remote exclusive control of the device's capabilities.

Abstract: A mixed queue method for managing storage requests directed includes a low-priority request queue on which all low-priority requests are placed and where they are subject to throughput optimization by re-ordering. When a high-priority request limit has not been reached, high-priority requests are placed on a high-priority request queue where they are executed in a pre-emptive manner with respect to the queued low-priority requests, thus experiencing reduced access time. When the high-priority request limit has been reached, the high-priority requests are placed on the low-priority request queue, such that the high-priority requests are included in the throughput optimization along with the low-priority requests on the request queue. Starvation of the low-priority requests is avoided, and the overall throughput of the disk drive is maintained at a relatively high level.

Abstract: Provided are methods, apparatus and computer programs for scheduling storage input and/or output (I/O) requests. A method for scheduling storage access requests determines a request processing sequence calculated to maximize SLA-based revenues achievable from processing a number of requests. A storage controller includes a scheduler which implements a revenue-based scheduling function to determine a revenue-maximizing processing sequence, and then assigns storage access requests to locations in a queue corresponding to the determined sequence. In an on-line mode, the scheduler can adapt to additional received requests, evaluating the revenue function for the additional requests and modifying the schedule if required. The method may include analysing a request stream to predict requests that are likely to be received in the near future, and taking account of the predicted requests when determining a processing schedule.

Abstract: A cache memory subsystem including a fixed latency read/write pipeline. The cache memory subsystem includes a cache storage which may be configured to store a plurality of cache lines of data. The cache memory subsystem further includes a scheduler which may be configured to schedule reads and writes of information associated with the cache storage using a fixed latency pipeline. In response to scheduling a read request, the scheduler may be further configured to cause an associated write to occur a fixed number of cycles after the scheduling of the read request.

Abstract: In a method of controlling transmitting and receiving buffers of a network controller and a network controller operating under such a method, at least one request for access to a system bus from the transmitting buffer and the receiving buffer is received, and the occupancy level of data in the receiving buffer and the vacancy level of data in the transmitting buffer are determined. Access to the system bus is granted based on the determination result. Buffers in the transmitting and receiving paths are treated as a single virtual transmitting buffer and a single virtual receiving buffer, respectively. Bus priority is determined by the data occupancy level in each virtual buffer and any change in the occupancy level. Therefore, it is possible to prevent or reduce underflow of the transmitting buffer and overflow of the receiving buffer, thereby impartially arbitrating which of the buffers can access the memory.

Abstract: A method and apparatus for traversing a queue of commands containing a mixture of read and write commands places a Next Valid Write Address pointer in each queue entry. In this manner, time savings are achieved by allowing preprocessing of the next write command to be executed. The method may be practiced by setting a next valid address pointer in all queue entries. Queue traversal may be forward, backward, or bi-directional.

Abstract: A network device and method for sharing resources in a network. The network device includes a port through which a shared resource request may be received. A processor accesses a store of the shared resource data to determine if the shared resource request is grantable. If the request is grantable, the network device may grant the request and then update the shared resource data.

Abstract: A memory module includes a memory hub coupled to several memory devices. The memory hub is also coupled to receive a memory packet from a system controller containing a memory hint indicative of the subsequent operation of the memory devices. The memory module uses the hint to adjust the operation of the memory module, such as the number of pages to remain open or cache lines to be fetched.

Abstract: A host channel adapter is configured for servicing received work notifications based on identifying the work notifications associated with the virtual lanes (VL) having a prescribed ordering position identified by the link layer operations. The host channel adapter, in response to receiving a work notification for a prescribed service level (SL), determines the virtual lane associated with the specified service level based on a prescribed service level to virtual lane mapping. If necessary (e.g., for an unreliable datagram service type), the work notification supplies the prescribed service level (SL) for the host channel adapter. The host channel adapter also determines an ordering position for the determined virtual lane from the link layer module, and selectively services the work notification based on the corresponding ordering position.

Abstract: A serialization detection arrangement determines whether a received IO request requires serialization. An overlap detection arrangement then determines if the received IO request produces an impermissible overlap condition. Each IO request producing an impermissible overlap condition is blocked so that it cannot be executed by a storage device while the impermissible overlap condition exists. However, IO requests avoiding an impermissible overlap condition are passed on to the storage device to be executed at the device. Blocking or passing IO requests is preferably performed by an IO request control arrangement. Upon receipt of an IO done signal for a particular IO request, a completion arrangement starts any IO request that had been blocked by the particular IO request and updates the records for both pending requests requiring serialization and blocked IO requests.

Abstract: A command storage technique that fulfils ordering rules is provided. This technique may be used in HyperTransport compliant southbridge devices. A command transmit engine comprises a command storage unit that is adapted to receive incoming commands of different command types and store the command in the order in which the commands were received. The command transmit engine further comprises an ordering rule controller that is connected to the command storage unit to select stored commands to be transmitted. The ordering rule controller is adapted to perform the selection according to predefined command ordering rules. The command ordering rules are command type dependent.

Abstract: The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and determine if DMA contexts can be automatically configured and started to transfer the data for those commands. CQE can also program DMA contexts to automatically return status information either after the disk has completed a transfer (as in non-cached writes) or after the DMA transfer is completed (as in reads or cached writes). CQE also utilizes a buffer-based linked-list to queue the SCSI commands as they arrive for future DMA context configuration. The present invention provides automated recognition and linking of commands belonging to a common thread, i.e., are sequential. The present invention also provides extensive thread boundary information and flexible firmware control for reordering commands.

Abstract: In response to requests for I/O processing sent from a computer, I/O which should be processed at a priority is enabled to be processed without being affected by other processing, by classifying I/O into those to be processed at a priority and those not to be processed at a priority. The storage control apparatus comprises an I/O processing controller with a memory that is common for the whole controller. The storage control apparatus manages information for dividing and controlling a plurality of I/O processes as priority and non-priority in that memory and operates while suppressing non-priority I/O processing on the basis of information in the memory.