Abstract: A controller including an interface module and an index module. The interface module is configured to connect devices. The index module is configured to include, in a table stored in memory, an entry for each of the devices. Each entry includes an address field. The index module is configured to: receive a frame of data including an address of one of the devices; compare the address to the address fields associated with the entries in the table; in response to the address matching one of the address fields, access an index value identifying an entry of the table when the address matches one of the address fields; and in response to the address not matching one of the address fields, generate the index value. The index value is used to connect the device associated with the matching one of the address fields with the one of the devices.

Abstract: A method of bridging a plurality of buses within a bus bridge can include determining whether a queue of the bus bridge includes a transaction request directed to a restricted address range and, for each received transaction request, determining whether an address to which the transaction request is directed is within the restricted address range. Each transaction request received by the bus bridge can be selectively rejected according to whether the address to which the transaction request is directed is within the restricted address range and whether the queue includes a transaction request directed to the restricted address range.

Abstract: A transfer apparatus includes a connection status detection block, a storage status detection block, a no-operation status detection block, and a transfer block. The transfer block can automatically transfer candidate data to a memory device when a connected status is detected by the connection status block, the transfer candidate stored status is detected by the storage status detection block, and a no-operation status is detected by the no-operation status detection block.

Abstract: An embodiment of the present invention includes a communication system configured to conform to SATA or SAS standards and causing communication between one or more hosts and a SATA device. The communication system includes a communication device adapted to generate debug information incorporated through one or more links using an analyzer to identify problems associated with the communication system.

Abstract: Systems, methods and computer program products for providing indirect data addressing at an I/O subsystem of an I/O processing system. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving a control word for an I/O operation. The control word includes an indirect data address for data associated with the I/O operation. The indirect data address includes a starting location of a list of storage addresses that collectively specify the data, the list spans two or more non-contiguous storage locations. Data is gathered responsive to the list. The gathered data is transmitted to a control unit in the I/O processing system.

Abstract: This is generally directed to systems and methods for control of two or more devices through a shared control bus. For example, the devices can be coupled to a host system through the control bus. In some embodiments, the devices can be configured by the host system through address select pins of the devices. For example, the host system can sequentially program each device to change its default address to a unique address. In some embodiments, an event can be propagated through each device, thus resulting in each device receiving the event at a different time. In some embodiments, configuration by the host system can include programming each device with a value representing its own position in the chain. In this case, a device can use this value to delay its response to the event, thereby allowing all the devices in the chain to respond to the event simultaneously.

Abstract: A matrix architecture for KVM extenders connecting a plurality of console terminals and a plurality of computers. The matrix architecture for KVM extenders includes a plurality of first extenders and a plurality of second extenders. The first extenders transform keyboard, mouse analog signals into keyboard, mouse data packets and transform video data packets into video signals for console terminals. The second extenders transform video signals into video data packets and transform keyboard, mouse data packets into keyboard, mouse analog signals. The broadcasters broadcast keyboard, video, mouse data packets, each having a source address and a target address to couple computers to console terminals by broadcasting video data packets from second extenders to first extenders and to couple console terminals to computers by broadcasting keyboard, mouse data packets from first extenders to second extenders.

Abstract: The system according to the present invention for data transfer between microcomputer devices contains a standard protocol controller, a generally known ethernet controller, for example, as a coupling device instead of the known multipart RAM. Instead of a parallel data connection, the microcomputer devices are coupled to one another via a standardized, serial data connection, for example, ethernet. Using functions of ethernet switches already known, a number of microcomputer devices in the system may be increased.

Abstract: An article of manufacture, apparatus, and a method for facilitating input/output (I/O) processing for an I/O operation at a host computer system configured for communication with a control unit. The method includes the host computer system obtaining a transport command word (TCW) for an I/O operation having both input and output data. The TCW specifies a location of the output data and a location for storing the input data. The host computer system forwards the I/O operation to the control unit for execution. The host computer system gathers the output data responsive to the location of the output data specified by the TCW, and then forwards the output data to the control unit for use in the execution of the I/O operation. The host computer system receives the input data from the control unit and stores the input data at the location specified by the TCW.

Abstract: An accelerated access apparatus and reading and writing methods thereof are described. A processing unit is used to determine whether the continuation state of a plurality of first address parameters of first request signals. Each first request signal has a first address length. When the first address parameters are continuous thereamong, the processing unit converts one of the second request signals into a second reading command which has a second reading address and a second reading address length. The second reading address length is greater than one of the first address lengths. The processing unit executes the second reading command to read data content to be stored in a buffer unit based on the second reading address and the second reading address length for responding to the second request signals.

Abstract: Methods and systems for performing direct memory access (DMA) transfers are described. An invalidate queue (or other storage device) contains an entry associated with a DMA transfer in progress. If the invalidate queue detects an invalidation of a memory page associated with that entry, then it is marked invalid. If the entry is marked invalid during the DMA transfer, then that DMA transfer is aborted. This enables, among other things, DMA transfers to unpinned virtual memory.

Abstract: Routing between multiple hosts and adapters in a PCI environment is provided by a method and system. A Destination Identification (DID) field is inserted in a field of the PCI bus address (PBA) of transaction packets dispatched through PCI switches. A particular DID is associated with a particular host or system image, and thus identifies the physical or virtual end point of the packets. The method and system may track connections such that when particular host of a root node becomes connected to a specified switch, a PCI Configuration Master (PCM), residing in one of the root nodes, is operated to enter a destination identifier or DID into a table. The DID is then inserted in the PBA of packets directed through the specified switch from the particular host to one of the adapters.

Abstract: Particular embodiments include a system and method to enable a user-controlled proxy system or coordinating computer to automatically or semi-automatically communicate with multiple devices, determine the currently operating software contents and versions for each device, and to automatically or semi-automatically upgrade each device with updated software without requiring user intervention. The software may include communication, operating system or application-specific program codes that improve a given device's designed function.

Abstract: The present invention includes an adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., Discrete Cosine Transform (DCT), Fast-Fourier Transform (FFT) and other operations. Other features are provided.

Abstract: A computer program product, apparatus, and method are provided for determining a state of an input/output (I/O) operation in an I/O processing system. A request from a channel subsystem is received at a control unit for performing the I/O operation. After a predetermined amount of time passes without the I/O operation completing, an interrogation request is received from the channel subsystem at the control unit for determining the state of the I/O operation. A response is sent from the control unit to the channel subsystem indicating the state of the I/O operation in response to the interrogation request. The response also includes information regarding a state of an I/O device executing the I/O operation and information indicating a state of the control unit controlling the I/O device executing the I/O operation.

Abstract: A method, system, and program product for reserving resources in a networked environment, e.g. a storage area network. A resource is some object that a user must use or change to complete a task. When a user plans a task, the user selects some high-level resources and properties to reserve and a Reservation Service embodiment creates reservations for them. Accordingly, the method system and program product embodiments overcome inefficiencies in reserving resources in a data storage environment while still allowing such reservations to occur. The method includes reserving portions of properties for resources from more than one available choice.

Abstract: Wireless communication equipment which associates with a plurality of sets of peripheral equipment present in a prescribed range through wireless communication stores identification code information regarding the associated peripheral equipment, acquires identification code information from the peripheral equipment present in the prescribed range, and determines whether or not the peripheral equipment has already associated on the basis of the identification code information. If the peripheral equipment has not been associated, the wireless communication equipment stores the identification code information by associating them with an image. If the peripheral equipment has been associated, the wireless communication equipment displays the associated image stored by associating them with the acquired identification code information, and connects to the corresponding peripheral equipment in response to the selection of the displayed and associated image.

Abstract: Systems, methods and computer program products for providing indirect data addressing at an I/O subsystem of an I/O processing system. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving a control word for an I/O operation. The control word includes an indirect data address for data associated with the I/O operation. The indirect data address includes a starting location of a list of storage addresses that collectively specify the data, the list spans two or more non-contiguous storage locations. Data is gathered responsive to the list. The gathered data is transmitted to a control unit in the I/O processing system.

Abstract: A method for communicating video data between at least a first host and a second host comprises: identifying, at a server, an address of the first host, to which the second host may communicate video data, and a sequence number expected by a network security system coupled between the first host and the server; and communicating, from the second host to the first host, video data using the address of the first host and the sequence number expected. The method may further comprise: identifying, at the server, an address of the second host, to which the first host may communicate video data, and a second sequence number expected by a network security system coupled between the second host and the server; and communicating, from the first host to the second host, video data using the address of the second host and the second expected sequence number. The second host may be adapted to perform the act of communicating without use of an intermediate server.

Abstract: A modular distributed I/O system that allows one or more modules of an island to be omitted without requiring reconfiguration of the system and a method for auto-addressing the system. The island includes a network interface module that is operably connected to a user interface. The user interface allows a user to indicate for each of the nodes of the island whether the node has an I/O module physically present or not physically present. This allows a constant process image in a system where the process image is dependent upon node ID's of modules, and modules are assigned addresses (i.e., ID's) automatically without using unique markers or signatures.

Abstract: A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) is serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) as a packet are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID accompanying the fed DT for another device and the fed ID is latched in a register of the device. In a case of no match, the ID generation is skipped and no ID is generated for another device. The DT is combined with the generated or the received ID depending on the device type match determination. The combined DT and ID is as a packet transferred to a next device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection.

Abstract: A system and/or methodology that facilitates serial peripheral interface (SPI) addressing beyond 24 bits, by portioning a conventional SPI command byte into a plurality of nibbles. A new set of commands are mapped to the first nibble, and selected from the set of unused binary values under the conventional SPI command protocol. A number of address bytes required to access the storage location for the command are mapped on a second nibble, and a user and/or system definable number of dummy bytes to be sent after the command are mapped on a third nibble.

Abstract: The invention discloses an indexing device for a data storage system which comprises a plurality of data storage devices. The indexing device generates an I/O descriptor index number according to a target data storage device, where the I/O descriptor index number corresponds to a device ID number and a queued command tag number. After receiving from the target data storage device an information packet containing the queued command tag number and a second connection request data frame including the device ID number, the indexing device can calculate the I/O descriptor index number according to the device ID number and the queued command tag number.

Abstract: In one embodiment, a processor comprises execution circuitry and a translation lookaside buffer (TLB) coupled to the execution circuitry. The execution circuitry is configured to execute a store instruction having a data operand; and the execution circuitry is configured to generate a virtual address as part of executing the store instruction. The TLB is coupled to receive the virtual address and configured to translate the virtual address to a first physical address. Additionally, the TLB is coupled to receive the data operand and to translate the data operand to a second physical address. A hardware accelerator is also contemplated in various embodiments, as is a processor coupled to the hardware accelerator, a method, and a computer readable medium storing instruction which, when executed, implement a portion of the method.

Abstract: A software process receives a command initiating creation of a zone naming policy for automatically generating zone names in a storage area network. During creation of a zone naming policy, the software process receives selection of one or more format elements to be used in the zone naming policy. The one or more format elements each identify which corresponding at least one type of characteristic associated with a given zone in the storage area network shall be used to automatically generate a respective zone name for the given zone. For example, the format elements in a zone policy may identify how to generate a respective zone name using identifiers associated with resources associated with the zone. Accordingly, a network manager can create a zone naming policy for automatically generating zone names in a storage area network rather than having to manually create zone names for each created zone.

Abstract: An interface includes a controller that divides a burst access command into a plurality of command cycles and supplies the plurality of command cycles to a storage device including a plurality of blocks, and a block address converter that outputs an address at a first command cycle of the plurality of command cycles. The address is obtained by shifting at least one bit of an external block address input in response to the burst access command. The address is supplied to the storage device at the first command cycle, and the external block address is supplied to the storage device at a command cycle other than the first command cycle.

Abstract: An output apparatus includes an IP-address setting unit, a setting change detection unit, and a notification information creation unit. The IP-address setting unit sets an IP address of the output apparatus. The setting change detection unit detects a change in the setting of the IP-address setting unit. The notification information creation unit creates information that will be notified to a device that satisfies predetermined conditions upon detection of the setting change by the setting change detection unit.

Abstract: A matrix architecture for KVM extenders connecting a plurality of console terminals and a plurality of computers. The matrix architecture for KVM extenders includes a plurality of first extenders and a plurality of second extenders. The first extenders transform keyboard, mouse analog signals into keyboard, mouse data packets and transform video data packets into video signals for console terminals. The second extenders transform video signals into video data packets and transform keyboard, mouse data packets into keyboard, mouse analog signals. The broadcasters broadcast keyboard, video, mouse data packets, each having a source address and a target address to couple computers to console terminals by broadcasting video data packets from second extenders to first extenders and to couple console terminals to computers by broadcasting keyboard, mouse data packets from first extenders to second extenders.

Abstract: A graphics device delivers a graphics address to a graphics memory switch that includes a graphics random access memory translator and a graphics memory page table. The graphics memory address is delivered to the graphics memory switch via a point-to-point, packet based interconnect. The graphics memory switch generates a physical system memory address and delivers the physical address to a root complex. The physical system memory address is delivered to the root complex via a point-to-point, packet based interconnect.

Abstract: Consistent with one example embodiment, a communications system uses an I2C serial data transfer bus that has a serial data line (110) and a clock line (120) used to implement a communications protocol. The communications system includes a slave device having address pins (400), each coupled to the serial data line, clock line, power line, or ground. Communications circuitry communicates with a master device in accordance with the communications protocol over the data transfer bus. Decoding circuitry detects a first state of the address pins (410), detects a second state of the address pins (420) subsequent to the detection of the first state, wherein one or more logic values of the address pins differ between the first state and the second state, and decodes a slave device address (430) as a functional relationship between the first state and the second state of the address pins.

Abstract: A multi-input/output serial peripheral interface of an integrated circuit includes many pins coupled to the integrated circuit. The integrated circuit receives an instruction under a control of selectively using only a first pin or a combination of the first pin, a second pin, a third pin, and a fourth pin of the multi-input/output serial peripheral interface. The integrated circuit receives an address using the first pin, the second pin, the third pin, and the fourth pin of the multi-input/output serial peripheral interface. The integrated circuit sends a read out data using the first pin, the second pin, the third pin, and the fourth pin of the multi-input/output serial peripheral interface.

Abstract: A plurality of modes is provided for communicating between a host system and a peripheral storage system controller. A first communication mode may be selected from the plurality of communication modes based on a bit length required to communicate a physical address. During runtime, a switch from the first communication mode to a second communication mode may be performed in order to improve the efficiency of processing address requests at the storage system controller.

Abstract: Producers and consumer processes may synchronize and transfer data using a shared data structure. After locating a potential transfer location that indicates an EMPTY status, a producer may store data to be transferred in the transfer location. A producer may use a compare-and-swap (CAS) operation to store the transfer data to the transfer location. A consumer may subsequently read the transfer data from the transfer location and store, such as by using a CAS operation, a DONE status indicator in the transfer location. The producer may notice the DONE indication and may then set the status location back to EMPTY to indicate that the location is available for future transfers, by the same or a different producer. The producer may also monitor the transfer location and time out if no consumer has picked up the transfer data.

Abstract: According to one embodiment of the invention, a data modifying bus buffer generally includes a switch that is configured to selectively couple a first databus to a second databus. The switch is controlled by a buffer controller. The first databus and a second databus have a similar predetermined protocol. The buffer controller is operable to monitor the first databus for the presence of a particular sequence of the signals such that, when the particular sequence of the signals is found, the first switch may be selectively opened or closed.

Abstract: A method and system for transferring data between a host and a Serial Attached Small Computer Interface (“SAS”) device using a storage controller is provided. The storage controller includes, a World Wide Name (“WWN”) module that includes a table having plural entries, wherein each row includes a WWN address, an initiator tag value field, an input/output counter value that tracks plural commands for a connection. A WWN index value represents the address of a row having plural entries. The method includes, comparing frame elements of incoming frames, including a unique WWN address with the WWN module entries; and if there is a match, updating a counter value for a connection between the storage controller and a device sending frames. The counter value is increased when a command frame is received and decreased when a command is executed and a response is sent to the device.

Abstract: A matrix architecture for KVM extenders connecting a plurality of console terminals and a plurality of computers. The matrix architecture for KVM extenders includes a plurality of first extenders and a plurality of second extenders. The first extenders transform keyboard, mouse analog signals into keyboard, mouse data packets and transform video data packets into video signals for console terminals. The second extenders transform video signals into video data packets and transform keyboard, mouse data packets into keyboard, mouse analog signals. The broadcasters broadcast keyboard, video, mouse data packets, each having a source address and a target address to couple computers to console terminals by broadcasting video data packets from second extenders to first extenders and to couple console terminals to computers by broadcasting keyboard, mouse data packets from first extenders to second extenders.

Abstract: A method and apparatus is presented allowing multiple data pointers or addresses to be transferred without acknowledgment to Memory Controller (506) and Memory Controller (510) of Data Controller (500). Data is then transferred in response to the data pointers from BUFFER (512) and Buffer (514) and may be stalled during the transfer in favor of a second data transfer. Once the second data transfer finishes, the first data transfer may be completed.

Abstract: A controller which exits between a client apparatus and an image processing apparatus and which controls access from the client apparatus such that the client apparatus can use a network server function of the image processing apparatus, its control method and control program and storage medium. To accomplish this, the controller which exists between a client terminal and an image processing apparatus and which controls data transmitted from the client terminal to the image processing apparatus comprises information providing unit which provides setup information of the controller to the client terminal and transfer unit which transfers setup information of the image processing apparatus to the client terminal.

Abstract: A system and/or methodology that facilitates serial peripheral interface (SPI) addressing beyond 24 bits, by portioning a conventional SPI command byte into a plurality of nibbles. A new set of commands are mapped to the first nibble, and selected from the set of unused binary values under the conventional SPI command protocol. A number of address bytes required to access the storage location for the command are mapped on a second nibble, and a user and/or system definable number of dummy bytes to be sent after the command are mapped on a third nibble.

Abstract: A method for verifying data in a storage system is disclosed. A host computer transmits area management data to a storage controller. The area management data specifies a range of a storage area in a storage device to be used by an application program having a mechanism for verifying data suitability. Upon receipt of an input/output request transmitted from the host computer, the storage controller performs verification, which is usually performed by the application program, of the data that is to be processed according to the data input/output request and to be input/output to/from the storage area, which is specified in accordance with the received area management data.

Abstract: Methods, systems and apparatus for suppressing redundancy in data transmission over networks are provided. Data segments are transmitted from a transmitting DPU to a receiving DPU. Initially, only signatures of the transmitted data segments are stored in a cache at the transmitting DPU. A data segment is stored in the cache only if it satisfies a redundancy-suppressing admission policy. Such a data segment is referred to as a redundant data segment. The redundant data segment is also stored in a cache at the receiving DPU. The transmitting DPU transmits the signatures of the redundant data segments to the receiving DPU, which then extracts the redundant data segments from its cache. Therefore, transmission of the redundant data segments is suppressed.

Abstract: A method and system for testing a modular data-processing component. Register information associated with a modular data-processing component to be tested at a test location can be identified and stored. The modular data-processing component can then be tested and removed from said test location. Thereafter, the register information can be retrieved and provided for use with testing of a new data-processing component at said test location without losing said register information during testing of multiple modular data-processing components. The register information can be, for example, PCI configuration data and the modular data-processing component can be an HAB.

Abstract: A storage system that may include one or more memory devices, a memory interface device corresponding to one or more of the memory devices, which are organized in sections, and a section controller. In this system, a data request for the data may be received over a communications path by a section controller. The section controller determines the addresses in the memory devices storing the requested data, transfers these addresses to those memory devices storing the requested data, and transfers an identifier to the memory interface device. The memory device, in response, reads the data and transfers the data to its corresponding memory interface device. The memory interface device then adds to the data the identifier it received from the section controller and forwards the requested bits towards their destination, such that the data need not pass through the section controller.

Abstract: Methods and apparatus to improve address translation performance in virtualized environments are described. In one embodiment, a switching logic may translate a virtual address of a memory access request (e.g., transmitted by a transmitting agent and directed to a receiving agent) into a corresponding physical address. Other embodiments are also disclosed.

Abstract: Systems and methods for providing remote pre-fetch buffers. The systems include a computer memory system with a memory controller, one or more memory busses connected to the memory controller, and at least one memory subsystem in communication with the memory controller via the memory busses. The memory controller generates, receives and responds to memory access requests including unsolicited data transfers. The memory subsystem includes one or more memory devices and logic to initiate an unsolicited data transfer to the memory controller based on analysis performed at the memory subsystem of prior memory access requests received by the memory subsystem.

Abstract: One embodiment of the present invention provides a system that includes an I/O descriptor cache that is accessed by a bus mastering I/O controller. The I/O descriptor cache stores descriptors that describe data to be transferred during corresponding I/O operations. The system also includes an I/O controller configured to control one or more I/O devices. This I/O controller is configured to access I/O descriptors stored in the I/O descriptor cache without having to access the main memory, thereby conserving I/O bandwidth and power.

Abstract: Disclosed is a computer implemented method, data processing system and computer program product to discover an SCSI target. The method comprises a client adapter transmitting an N_port ID virtualization (NPIV) login to a virtual I/O server (VIOS). The client adapter receives a successful login acknowledgement from the VIOS and issues a discover-targets command to the fabric. Upon determining that the SCSI target information is received, wherein the SCSI target information includes at least one SCSI identifier. Responsive a determination that SCSI target information is received the client adapter issues a port login to a target port, wherein the target port is associated with the at least one SCSI target. The client adapter makes a process login to form an initiator/target nexus between a client and at least one SCSI target. The client adapter queries the SCSI target by using a world wide port name associated with the target port.

Abstract: A plurality of detectors can be evaluated to determine if more than one has been assigned the same address. Responsive thereto, such detectors could be identified for follow-up maintenance, or service.

Abstract: A system for determining slot specific information in a base station includes a switch provided in connection with each circuit pack in slots of the base station. The switches are selectively operated to isolate a particular circuit pack to associate the information relating to that circuit pack in a specific slot in the base station.

Abstract: The present invention includes a adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., discrete cosine transform (DCT), fast-Fourier transform (FFT) and other operations. Other features are provided.