Abstract: A system for synchronizing and re-ordering data transmitted between first and second clock domains associated with first and second device interfaces, respectively, includes a splitter, an arbiter, a transaction manager, and a read data buffer. The splitter receives a parent read request from one or more data input ports of the first device interface and splits it into one or more read requests. The arbiter receives the one or more read requests and selects one of the read requests and transmits it to the transaction manager. The transaction manager allocates an entry to the read request and then the read request is transmitted to the read data buffer. Thereafter, the read data buffer transmits the read request to the second device interface and transmits received response data to the first device interface.

Abstract: In response to receiving a request for a DMA data transfer, a DMA transfer mode may be determined based on based on the size of the requested DMA data transfer and profile data of an I/O adapter. The profile data for the I/O adapter may include a physical location of the I/O adapter or a number of clients supported by the I/O adapter. The DMA transfer mode may also be determined based on a preference of an application or an I/O device. Moreover, the DMA transfer mode may be determined based on a CPU usage metric being outside of a threshold for the CPU usage metric or on a memory usage metric being outside of a threshold for the memory usage metric.

Abstract: According to one embodiment, a method for dynamically changing a buffer threshold in a tape drive includes determining that a drive buffer is emptied of data, calculating a write size indicating an amount of data from a transaction size left to be written to a tape prior to a next anticipated sync command, setting a buffer threshold that triggers a back hitch to a smaller value when the transaction size is less than a buffer size, setting the buffer threshold to the smaller value when an absolute difference between the transaction size and the write size is greater than or equal to the buffer size, and setting the buffer threshold to a larger value when the transaction size is not less than the buffer size and/or the absolute difference between the transaction size and the write size is less than the buffer size.

Abstract: A method of operating a buffer memory of a data processing system on which two or more programs can run in parallel includes the following: a source code is generated for a program to be executed and the needed data of the program to be executed are stored in the buffer memory; at least one address register is simultaneously generated, with the memory content of the address register being addresses of each of the two or more programs in the buffer memory. The two or more programs in the buffer memory are accessed via the at least one address register.

Abstract: An information memory system in which data received is divided into pieces of data, which are stored in memories in parallel, includes controller configured to storing a number of the divided pieces of data and monitoring a read request and a buffer full notice, in a case where the number of read requests does not reach the number of valid memory units and the buffer full notice continues in all buffers except for one buffer which does not output the read request, performing a read control corresponding to the buffers which output the buffer full notice, and performing control of the integration of a piece of data reconstructed, after being read from the memory unit corresponding to the buffer which does not output the read request and the pieces of data read from the memory units corresponding to the buffers which output the buffer full notice.

Abstract: Embodiments of methods that are useful to avoid overflow in fixed-length buffers. In one embodiment, the methods dynamically adjust parameters (e.g., sample time) and reconfigure data in the buffer to allow new data samples to fit in the buffer. These embodiments allow data collection to automatically adapt, e.g., by adjusting the sample rate to allow the data to fit in the limited buffer size. These embodiments can configure hardware and/or software on a valve positioner of a valve assembly to improve data collection for use in on-line valve diagnostics and other data processing techniques.

Abstract: A data processing apparatus comprises a primary processor, a secondary processor configured to perform secure data processing operations and non-secure data processing operations and a memory configured to store secure data used by the secondary processor when performing the secure data processing operations and configured to store non-secure data used by the secondary processor when performing the non-secure data processing operations, wherein the secure data cannot be accessed by the non-secure data processing operations, wherein the secondary processor comprises a memory management unit configured to administer accesses to the memory from the secondary processor, the memory management unit configured to perform translations between virtual memory addresses used by the secondary processor and physical memory addresses used by the memory, wherein the translations are configured in dependence on a page table base address, the page table base address identifying a storage location in the memory of a set of des

Abstract: Buffer memory reservation techniques for use with NAND flash memory include dynamically reserving regions of the buffer memory, responsive to a read/write request. Where the read/write request includes a plurality of data transfer requests, following completion of a data transfer request, the reserved buffer space may be recycled for use in a further data transfer request or for other purposes. During fulfillment of a read request, a buffer region is reserved from a larger buffer pool for a time period significantly smaller than the time required to execute a sense operation associated with the read request. The reserved buffer region may be reused for unrelated processes during execution of the sense operation.

Abstract: Memory system controllers can include hardware masters, first buffers, and a switch coupled to the hardware masters and to the first buffers. The switch can include second buffers and a buffer allocation management (BAM) circuit. The BAM circuit can include a buffer tag pool. The buffer tag pool can include tags, each identifying a respective first buffer or a respective second buffer. The BAM circuit can be configured to allocate a tag to a hardware master in response to an allocation request from the hardware masters. The BAM circuit can be configured to prioritize allocation of a tag identifying a second buffer over a tag identifying a first buffer.

Abstract: Embodiments of the disclosure include methods, systems and computer program products for performing a data manipulation function. The method includes receiving, by a processor, a request from an application to perform the data manipulation function and based on determining that a specialized hardware device configured to perform the data manipulation function is available, the method includes determining if executing the request on the specialized hardware device is viable. Based on determining that the request is viable to execute on the specialized hardware device, the method includes executing the request on the specialized hardware device.

Abstract: A method and system for processing buffer status reports (BSRs) such that when BSR triggering is performed, the size(s) of the necessary sub-header(s) are also to be considered together in addition to the BSR size. The steps of checking whether any padding region is available in a MAC PDU that was constructed, comparing the number of padding bits with the size of the BSR plus its sub-header, and if the number of padding bits is larger than the size of the BSR plus its sub-header, triggering BSR are performed. Doing so allows the sub-header(s) to be inserted or included into the MAC PDU or transport block (TB) or other type of data unit.

Abstract: According to one embodiment, a method for implementing an array-based queue in memory of a memory system that includes a controller includes configuring, in the memory, metadata of the array-based queue. The configuring comprises defining, in metadata, an array start location in the memory for the array-based queue, defining, in the metadata, an array size for the array-based queue, defining, in the metadata, a queue top for the array-based queue and defining, in the metadata, a queue bottom for the array-based queue. The method also includes the controller serving a request for an operation on the queue, the request providing the location in the memory of the metadata of the queue.

Abstract: Techniques are described which simplify and/or automate many of the tasks associated with the configuration, deployment, and management of network resources to support cloud-based services.

Abstract: A system and method are disclosed for processing commands to network target devices through a SCSI router in a Fiber Channel network having a plurality of Fiber Channel hosts. The system may be configured to receive a command, and determine that the command requires a transfer of data larger than a threshold size. The system may also be configured to receive a plurality of data blocks associated with the command, store the plurality of data blocks in at least one buffer, and determine if there is an initial amount of data in the at least one buffer. The system may be further configured to forward at least one of the plurality data blocks, and request an additional data block associated with the command.

Abstract: One embodiment sets forth a technique for dynamically allocating memory during multi-threaded program execution for a coprocessor that does not support dynamic memory allocation, memory paging, or memory swapping. The coprocessor allocates an amount of memory to a program as a put buffer before execution of the program begins. If, during execution of the program by the coprocessor, a request presented by a thread to store data in the put buffer cannot be satisfied because the put buffer is full, the thread notifies a worker thread. The worker thread processes a notification generated by the thread by dynamically allocating a swap buffer within a memory that cannot be accessed by the coprocessor. The worker thread then pages the put buffer into the swap buffer during execution of the program to empty the put buffer, thereby enabling threads executing on the coprocessor to dynamically receive memory allocations during execution of the program.

Abstract: An adaptive multi-thread buffer supports multiple writer process and reader processes simultaneously without blocking. Writer processes are assigned a reserved write slot using a writer index that is incremented for each write request. When a reserved write slot is not null, the buffer is resized to make room for new data. Reader processes are assigned a reserved read slot using a reader index that is incremented for each read request. When data is read out to the reader process, the read slot content is set to null. When a writer process attempts to write null data to a write slot, the buffer replaces the null write data with an empty value object so that content of the buffer is null only for empty slots. When an empty value object is read from a slot, the buffer replaces the content with null data to send to the reader process.

Abstract: A system and method can support input/output (I/O) virtualization in a computing environment. The system comprise a free buffer pool that contains a plurality of packet buffers associated with one or more virtual host bus adaptors (vHBAs), wherein each said vHBA maintains a main linked list of buffer pointers that point to one or more packet buffers. Furthermore, a context table can be defined on an on-chip memory associated with an input/output (I/O) device, wherein the context table maintains a temporary linked list of buffer pointers that point to one or more packet buffers allocated for a disk read operation. The I/O device can open the context table when the I/O device receives disk read data from a physical host bus adaptor (HBA), update the temporary linked list of buffer pointers, and merge the temporary linked list into the main linked list when the context table is closed.

Abstract: An interface includes a first hardware register field to store respective chunks of a command directed to a device and respective chunks of a response to the command from the device. The interface also includes a second hardware register field to store a size of the command and a size of the response. The first and second hardware register fields are accessible by the device and by a processor external to the device that generates the command, in response to memory not being available to buffer the command and the response.

Abstract: A method and system of a host device hosting multiple workloads for controlling flows of I/O requests directed to a storage device is disclosed. In one embodiment, a type of a response from the storage device reacting to an I/O request issued by an I/O stack layer of the host device is determined. Then, a workload associated with the I/O request is identified among the multiple workloads based on the response to the I/O request. Further, a maximum queue depth assigned to the workload is adjusted based on the type of the response, where the maximum queue depth is a maximum number of I/O requests from the workload which are concurrently issuable by the I/O stack layer.

Abstract: A multicore system 2 includes a main system program 610 that operates on a first processor core 61 and stores synthesized audio data, which is mixed audio data, to a buffer for DMA transfer 63, a standby program 620 that operates on a second processor 62, and an audio output unit 64 that sequentially stores the synthesized audio data transferred from the buffer for DMA transfer 63 and plays the stored synthesized audio data. When an amount of storage of the synthesized audio data stored to the buffer for DMA transfer 63 has not reached a predetermined amount of data determined according to the amount of storage of the synthesized audio data stored to the audio output unit 64, the standby system program 620 takes over and executes the mixing and the storage of the synthesized audio data that is executed by the main system program 610.

Abstract: In one embodiment, a latency value is determined for an input/output IO request in a host computer of a plurality of host computers based on an amount of time the IO request spent in the host computer's issue queue. The issue queue of the host computer is used to transmit IO requests to a storage system shared by the plurality of host computers. The method determines a host specific value assigned to the host computer based in proportion on a number of shares assigned to the host in a quality of service policy for IO requests. The size for the host computer's issue queue is determined based on the latency value and the host specific value to control a number of IO requests that are added to the host computer's issue queue where other hosts in the plurality of hosts independently determine respective sizes for respective issue queues.

Abstract: An optical reading device has an optical reading unit having optical elements disposed in a line that reads a medium; a storage unit having a ring buffer formed in the storage space; and a control unit that writes scanned data read by the optical reading unit to the ring buffer, reads the scanned data written to the ring buffer, and transfers the scanned data that was read. The control unit also manages positions in the ring buffer for writing and reading the scanned data using a write pointer denoting the position for writing the scanned data to the ring buffer, and a read pointer denoting the position of scanned data that has not been read.

Abstract: Accessing a shared buffer can include receiving an identifier associated with a buffer from a sending process, requesting one or more attributes corresponding to the buffer based on the received identifier, mapping at least a first page of the buffer in accordance with the one or more requested attributes, and accessing an item of data stored in the buffer by the sending process. The identifier also can comprise a unique identifier. Further, the identifier can be passed to one or more other processes. Additionally, the one or more requested attributes can include at least one of a pointer to a memory location and a property describing the buffer.

Abstract: An efficient low latency buffer, and method of operation, is described. The efficient low latency buffer may be used as a bi-directional memory buffer in an audio playback device to buffer both output and input data. An application processor coupled to the bi-directional memory buffer is responsive to an indication to write data to the bi-directional memory buffer reads a defined size of input data from the bi-directional memory buffer. The input data read from the bi-directional memory buffer is replaced with output data of the defined size. In response to a mode-change signal, the defined size of data is changed that is read and written from and to the bi-directional memory buffer. The buffer may allow the application processor to enter a low-powered sleep mode more frequently.

Abstract: There are provided a message processing device and a method improved to store a plenty of messages used for processing. When a message is transmitted to another node for providing a service, a message processing unit (26) monitors the message transferred and stores it in a storage region whose allocation is released when the remaining memory amount has become little. When an error has occurred in the processing of a service providing unit (200), the message processing unit (26) stores the error type and a session identifier associated with it. When a message transmission is requested from outside and the error type, the session identifier, and a message associated with them are stored, the message processing unit (26) transmits them. If the storage region which was containing a message is released and no message exists, the message processing unit (26) transmits the other two items.

Abstract: Efficient and convenient storage systems and methods are presented. In one embodiment a storage system includes a plurality of storage nodes and a master controller. The storage nodes store information. The storage node includes an upstream communication buffer which is locally controlled at the storage node to facilitate resolution of conflicts in upstream communications. The master controller controlls the flow of traffic to the node based upon constraints of the upstream communication buffer. In one embodiment, communication between the master controller and the node has a determined maximum latency. The storage node can be coupled to the master controller in accordance with a chain memory configuration.

Abstract: A system and method can provide a flexible buffer management interface in a distributed data grid. The buffer manager in the distributed data grid can receive a request from a requester for a buffer in the distributed data grid, wherein the request contains at least one parameter that provides an indication on the size of the requested buffer. Then, the buffer manager can allocate a buffer based on the indication in the request and provide the allocated buffer to the requester, wherein an actual size of the buffer is determined by the buffer manager.

Abstract: A novel and efficient method is described that creates a monolithic high capacity Packet Engine (PE) by connecting N lower capacity Packet Engines (PEs) via a novel Chip-to-Chip (C2C) interface. The C2C interface is used to perform functions, such as memory bit slicing and to communicate shared information, and enqueue/dequeue operations between individual PEs.

Abstract: There are disclosed systems and methods for reducing the average delay and the average delay variation of network communication data in a buffer. The buffer comprises a plurality of memory entries, and associated with the buffer is a read point and a write pointer. The buffer has a depth defined as the number of memory entries in the buffer between the memory entry pointed to by the read pointer and the memory entry pointed to by the write pointer. In one embodiment, at least one of the read pointer and the write pointer is initially set to establish the depth of the buffer to be a first value. The variation of the depth of the buffer is then monitored for a predetermined period of time as network communication data flows through the buffer. The depth of the buffer is then reduced based upon this monitoring.

Abstract: Controlling I/O operations with a storage device includes establishing a quota that corresponds to a maximum amount of data to store on the storage device in a given amount of time, determining if processing an I/O operation would cause the quota to be exceeded, and performing the I/O operation if the quota is not exceeded. The quota may be provided in I/O operations per second or as I/O throughput. Controlling I/O operations with a storage device may also include accumulating credit in response to a rate of I/O operations being less than the quota and performing I/O operations when the quota is exceeded in response to the credit being greater than zero. The credit may be decreased if an I/O operation is performed when the quota is exceeded.

Abstract: A dynamic A-MSDU enabling method is disclosed. The method enables the recipient of an aggregate MAC service data unit (A-MSDU) under a block ACK agreement to reject the A-MSDU. The method thus distinguishes between A-MSDU outside of the block ACK agreement, which is mandatory, from A-MSDU under the block ACK agreement, which is optional. The method thus complies with the IEEE 802.11n specification while enabling the recipient to intelligently allocate memory during block ACK operations.

Abstract: A system and a process for deploying a computer file involves a client computer applying the computer file concurrently with downloading the computer file from a file server. The concurrent operations can be performed even when the data of the computer file is downloaded out of order. The computer file includes a plurality of file segments. The client computer obtains information defining the file segments and monitors the received data of the computer file during downloading. When downloading of a file segment is complete, the client computer applies the completed segment concurrently with receiving other segments of the computer file from the file server. The process can be used when the computer file is downloaded using a multicast protocol, but is not limited to use with multicast protocols. The client computer can request only needed segments of the computer file.

Abstract: An interfacing circuit comprising a First In First Out (FIFO) memory for exchanging data between a “data producer device” and a “data consumer device”. The FIFO memory is controlled by first write control signals (WR, CLK_WR) and second read control signals (ENABLE, Clk_Rd). The interfacing circuit further includes: a redundancy filter (230) for receiving a sequence of N data (Y0, Y1, Y2 . . . Yn?1 ) to be stored within said FIFO, and for generating a redundancy control word representative of the presence of consecutive identical data within said sequence; means (250) for controlling said first and said second control signals of said FIFO for the purpose of preventing the storage into said FIFO of multiple consecutive identical data and more important to make possible to accelerate the average speed of the data flux going to the “data consumer device” without need to accelerate the clocking of the memory feeding the said FIFO thanks to increase of efficiency of transfers due to redundancy filtering.

Abstract: Described are systems and methods for transmitting data at an aggregation device. The aggregation device includes a record queue and an output bypass queue. The data is received from an electronic device. A record is generated of the received data. The record is placed in the record queue. A determination is made that the record in the record queue is blocked. The blocked record is transferred from the record queue to the output bypass queue.

Abstract: Files on a secondary storage are accessed using alternative IO subroutines that buffer IO requests made by a user and mimic the IO subroutines provided by an operating system. The buffer used by the alternative IO subroutines is maintained by the user and not the operating system. User applications are not recompiled or relinked when using the alternative subroutines because the library that provides these subroutines intercepts requests for buffered IO made by user applications to the operating system's IO subroutines and replaces the requests with calls to the alternative IO subroutines that utilize the buffer maintained by the user.

Abstract: Memory system controllers can include hardware masters, first buffers, and a switch coupled to the hardware masters and to the first buffers. The switch can include second buffers and a buffer allocation management (BAM) circuit. The BAM circuit can include a buffer tag pool. The buffer tag pool can include tags, each identifying a respective first buffer or a respective second buffer. The BAM circuit can be configured to allocate a tag to a hardware master in response to an allocation request from the hardware masters. The BAM circuit can be configured to prioritize allocation of a tag identifying a second buffer over a tag identifying a first buffer.

Abstract: In one example, multimedia content is requested from a plurality of storage modules. Each storage module retrieves the requested parts, which are typically stored on a plurality of storage devices at each storage module. Each storage module determines independently when to retrieve the requested parts of the data file from storage and transmits those parts from storage to a data queue. Based on a capacity of a delivery module and/or the data rate associated with the request, each storage module transmits the parts of the data file to the delivery module. The delivery module generates a sequenced data segment from the parts of the data file received from the plurality of storage modules and transmits the sequenced data segment to the requester.

Abstract: A system and method for allocating memory locations in a buffer memory system is described. The system includes a plurality of memory locations for storage and a controller. The controller controls the storage and retrieval of data from the plurality of memory locations and allocate a first portion of the memory locations to a first buffer, wherein the remaining portion of the memory locations defines a second portion. The controller allocates a portion of the second portion to a second buffer and the remaining portion of the second portion defines a third portion. The controller reserves a portion of the third portion for assignment to the second buffer, wherein, the second buffer is assigned a higher priority over the first buffer. The controller selectively allocates one or more memory locations of the third portion to the first buffer or to the second buffer.

Abstract: Techniques for reacting to events in a switch module. Embodiments provide a plurality of predefined load/store operations stored in a first memory buffer of the switch module. An execution buffer capable of storing load/store operations within the switch module is also provided. Responsive to detecting that a first predefined event has occurred, embodiments copy the plurality of predefined load/store operations from the first memory buffer to the execution buffer for execution. Upon detecting the plurality of predefined load/store operations within the execution buffer, the plurality of predefined load/store operations within the execution buffer are executed.

Abstract: A method for providing a content entity from a storage disc is described. The storage disc comprises at least one further content entity. Each content entity comprises a main menu and at least one submenu accessible via the main menu. The storage disc further comprises an entity selection menu. The entity selection menu comprises a link to the main menu of the content entity to be provided. The method comprises providing the entity selection menu for reproduction, receiving a selection of the content entity to be provided, detecting that the storage disc comprises a plurality of content entities, mapping a pre-defined start address to a different start address and providing the selected content entity for reproduction based on the different start address. The pre-defined start address is mapped to a different start address of the storage disc associated with the main menu of the selected content entity to be provided.

Abstract: A first network device including a first port to provide first data traffic to a first storage area network, a second port to provide second data traffic to a local area network, and memory shared between the first port and the second port to temporarily store the first data traffic in N first buffers and the second data traffic in M second buffers. A queue control module allocates a first memory space of the N first buffers to the first port and a second memory space of the M second buffers to the second port. An adjustment module adjusts a first amount of the first memory space and a second amount of the second memory space in response to a congestion event caused by a first data traffic. Up to all of the first memory space and the second memory space is allocated to the N first buffers.

Abstract: Methods for managing a single memory pool comprising frame buffer memory and display list memory are presented. The single memory pool can comprise sub-pools including: a super-block pool comprising a plurality of super-block objects; a node pool comprising a plurality of node objects; and a block-pool comprising a plurality of blocks. The method may comprise: receiving a memory allocation request directed to at least one of the sub-pools; allocating an object local to the sub-pool identified in the memory request, if local sub-pool objects are available to satisfy the memory request; allocating an object from super-block pool, if the memory request is directed to the node-pool or block-pool and there are no available local objects in the respective sub-pools to satisfy the memory request; and applying at least one of a plurality of memory freeing strategies, if the sub-pools lack available free objects.

Abstract: A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device, and at least one data storage device to the processor. Also coupled to the processor bus is a memory hub controller coupled to a memory hub of at least one memory module having a plurality of memory devices coupled to the memory hub. The memory hub is coupled to the memory hub controller through a downstream bus and an upstream bus. The downstream bus has a width of M bits, and the upstream bus has a width of N bits. Although the sum of M and N is fixed, the individual values of M and N can be adjusted during the operation of the processor-based system to adjust the bandwidths of the downstream bus and the upstream bus.

Abstract: A gasket of a data processing device controls the number of released storage locations of a buffer where read and write access requests are stored so that more read access requests can be stored without a corresponding increase in the amount of space at the buffer to store write access requests. An interface of the gasket accepts new access requests from one or more requesting modules only when a number of released storage locations at a buffer associated with the interface (referred to as an outbound buffer) is above a threshold number. As long as the number of stored access requests at the outbound buffer are less than a threshold amount, a buffer location can be immediately released. In addition, the gasket is configured to issue read access requests from the outbound buffer without regard to whether the inbound buffer has space available.

Abstract: Managing buffers in a hybrid system, in one aspect, may comprise selecting a first buffer management method from a plurality of buffer management methods; capturing statistics associated with access to the buffer in the hybrid system running under the initial buffer management method; analyzing the captured statistics; identifying a second buffer management method based on the analyzed captured statistics; determining whether the second buffer management method is more optimal than the first buffer management method; in response to determining that the second buffer management method is more optimal than the first buffer management method, invoking the second buffer management method; and repeating the capturing, the analyzing, the identifying and the determining.

Abstract: The present invention extends to methods, systems, and computer program products for memory pinning through buffer encapsulation. Within a managed execution environment, a wrapper object encapsulates a memory buffer that is to be shared with a native routine executing in a native execution environment. The wrapper object manages operation of a memory manager on a memory heap corresponding to the memory buffer. The wrapper object includes a first function which sets a pin on the memory buffer and returns a pointer identifying the memory buffer. Setting the pin causes the memory manager to cease moving the memory buffer within the memory heap. The wrapper object also includes a second function which releases the pin on the memory buffer.

Abstract: An information handling system includes a multi-core processor that processes variable-length code (VLC) bitstream data. The bitstream data includes multiple codewords that the processor organizes into functionally common subsets. The processor includes a general purpose processor (GPU) and one or more special purpose processor (SPUs). An SPU of the processor may includes two SPU buffers. The processor first transfers bitstream data into GPU buffer memory and then populates the SPU buffers one after another with bitstream data. The SPU buffers may each include an overlap region that the SPU populates with the same bitstream data. The SPU parses the bitstream data in the SPU buffers in alternating fashion. The SPU may shift parsing from the one SPU buffer to the other SPU buffer when parsing reaches a subset boundary within an overlap region.

Abstract: Systems and techniques include, in some implementations, a computer implemented method storing a portion of data elements present in a first buffer in a second buffer in response to detecting an overflow condition of the first buffer, wherein the data elements in the first buffer are sorted according to a predetermined order, and inserting a proxy data element in the first buffer to represent the portion of data elements stored to the second buffer.

Abstract: A tape drive, tape drive recording system, and method are provided for improving tape speed selection during data transfer. The tape drive includes a buffer, a tape for recording the data to be temporarily stored in the buffer, and a read head. The tape drive further includes a reading controller that initially sets a tape speed such that a drive transfer rate matches a host transfer rate as closely as possible and that drives the tape at the tape speed. To address backhitching caused by one or more host transfer halts, the reading controller subsequently adjusts the tape speed such that the drive transfer rate is lower than the host transfer rate by recalculating the host transfer rate in consideration of the host transfer and the host transfer halt and setting the tape speed such that the drive transfer rate matches the recalculated host transfer rate as closely as possible.

Abstract: An input/output processor for speeding the input/output and memory access operations for a processor is presented. The key idea of an input/output processor is to functionally divide input/output and memory access operations tasks into a compute intensive part that is handled by the processor and an I/O or memory intensive part that is then handled by the input/output processor. An input/output processor is designed by analyzing common input/output and memory access patterns and implementing methods tailored to efficiently handle those commonly occurring patterns. One technique that an input/output processor may use is to divide memory tasks into high frequency or high-availability components and low frequency or low-availability components.