Abstract: A memory allocation method and terminal for supporting Direct Memory Access (DMA) are provided. The terminal includes a memory for storing data used for operations of the terminal, a plurality of devices for executing applications for specific functions, a control unit for defining, when the terminal boots up, a virtual zone dedicated for the DMA in the memory, and a DMA unit for controlling the DMA of the devices.

Abstract: An apparatus, method and computer program in a distributed cluster storage network comprises storage control nodes to write data to storage on request from a host; a forwarding layer at a first node to forward data to a second node; a buffer controller at each node to allocate buffers for data to be written; and a communication link between the buffer controller and the forwarding layer at each node to communicate a constrained or unconstrained status indicator of the buffer resource to the forwarding layer. A mode selector selects a constrained mode of operation requiring allocation of buffer resource at the second node and communication of the allocation before the first node can allocate buffers and forward data, or an unconstrained mode of operation granting use of a predetermined resource credit provided by the second to the first node and permitting forwarding of a write request with data.

Abstract: A method for measuring latencies caused by processing performed within a common resource is provided. A current latency value representing a time of residency of an IO request in a queue prior to receipt of acknowledgment from the common resource of completion of the IO request is received from a device comprising the queue, which maintains entries for IO requests that have been dispatched to and are pending at the common resource. An average latency value is calculated based in part on the current latency value. An adjusted capacity size for the queue is calculated based in part on the average latency value and the queue's capacity is set to the adjusted capacity size. IO requests are held in a buffer if the queue's capacity is full to reduce the effect of an amount of work transmitted to the common resource on current latency values provided by the device.

Abstract: An embodiment of the present invention is disclosed to include a SATA Switch allowing for access by two hosts to a single port SATA device Further disclosed are embodiments for reducing the delay and complexity of the SATA Switch.

Abstract: A dynamic A-MSDU enabling method is disclosed. The method enables the recipient of an aggregate MAC service data unit (A-MSDU) under a block ACK agreement to reject the A-MSDU. The method thus distinguishes between A-MSDU outside of the block ACK agreement, which is mandatory, from A-MSDU under the block ACK agreement, which is optional. The method thus complies with the 802.11n specification while enabling the recipient to intelligently allocate memory during block ACK operations.

Abstract: A network device may include an off-chip memory to store a free-list of buffer pointers. The network device may further include an on-chip controller that includes a prefetch buffer. The prefetch buffer may store unallocated buffer pointers that point to available memory locations in a different off-chip memory. The on-chip controller may receive an unallocated buffer pointer, determine, in response to receiving the unallocated buffer pointer, whether the prefetch buffer is full, store the unallocated buffer pointer in the prefetch buffer when the prefetch buffer is determined not to be full, and store the unallocated buffer pointer in the free-list, in the off-chip memory, when the prefetch buffer is determined to be full.

Abstract: A serial communication device has: a MAC (Media Access Control), a mask circuit and a buffer. The MAC conforms to Serial Media Independent Interface specification and outputs an identical segment data for plural times within a unit period. The mask circuit is configured to mask a predetermined segment data out of the plurality of identical segment data and to output the other segment data out of the plurality of identical segment data. The buffer is configured to receive the segment data output from the mask circuit and to output the received segment data to a physical layer device in synchronization with a clock signal.

Abstract: A data storage device is provided, including a first data storage device electrically storing write data, a second data storage device magnetically storing write data, and a controller partitioning write data into first and second write data portions. The first write data portion is programmed to the first data storage device and the second write data portion if magnetically written to the second data storage device at the same time.

Abstract: In embodiments of extensions for USB driver interface functions, a set of USB driver interfaces are exposed by a USB core driver stack, and the USB driver interfaces include USB driver interface functions to interface with USB client function drivers that correspond to client USB devices. A composite device driver registers itself and requests a function handle for each function of a client USB device. The USB client function drivers are enumerated and the function handles generated for each function of the client USB device. A check first protocol is enforced that directs a USB client function driver to check for availability of a USB driver interface function before interfacing with the USB core driver stack via the USB driver interfaces. A contract version identifier is received that indicates a set of operation rules by which a USB client function driver interfaces with the USB core driver stack.

Abstract: A method and system are provided for transferring data in a networked system between a local memory in a local system and a remote memory in a remote system. A RDMA request is received and a first buffer region is associated with a first transfer operation. The system determines whether a size of the first buffer region exceeds a maximum transfer size of the networked system. Portions of the second buffer region may be associated with the first transfer operation based on the determination of the size of the first buffer region. The system subsequently performs the first transfer operation.

Abstract: A hybrid serial peripheral interface (SPI) data transmission architecture adapted in a network device for connecting a host and a network is provided. The architecture comprises a RX buffer and RX SPI for maintaining a data receiving process, a TX buffer and TX SPI for maintaining a data transmission process, a configuration and status register and a hybrid SPI processing module. The hybrid SPI processing module makes the RX SPI performs the data transmission process as well when the RX SPI idles and the data transmission process proceeds at the same time and makes the TX SPI to performs the data receiving process as well when the TX SPI idles and the data receiving process proceeds at the same time. A hybrid SPI data transmission method is disclosed herein as well.

Abstract: Various embodiments writing data are provided. In one embodiment, the data arranged in a plurality of write intervals is loaded into a plurality of buffers, the totality of the plurality of buffers configured as a sliding write window mechanism adapted for movement to accommodate the write intervals. The data may reach the storage system out of a sequential order, and by loading it appropriately into the said buffers the data is ordered sequentially before it is written to the storage media. When a commencing section of the sliding write window is filled up with written data, this section is flushed to the storage media, and the window slides forward, to accommodate further data written by the writers. The writers are synchronized with the interval reflected by the current position of the sliding write window, and they send data to be written only where this data fits into the current interval of the window.

Abstract: A method for maximizing I/O requests to a target port is provided. The method includes a storage controller obtaining an initiator allowed queue depth, receiving an I/O request and a current sequence identifier from an initiator logged into the target port, and determining if the initiator allowed queue depth is equal to a first queue depth corresponding to the initiator. If the initiator allowed queue depth is equal to the first queue depth then returning a queue full indication and a maximum sequence identifier equal to the current sequence identifier to the initiator. If the initiator allowed queue depth is not equal to the first queue depth then placing the I/O request on a queue, incrementing the first queue depth, and adjusting the maximum sequence identifier. Adjusting the maximum sequence identifier includes adding the current sequence identifier to the initiator allowed queue depth and subtracting the first queue depth.

Abstract: Disclosed are a method, upstream processing node, and computer readable medium for dynamically stabilizing a stream processing system. The method includes receiving at least one computing resource allocation target. The method further includes determining that an input data flow rate of at least one upstream processing element varies. The computing resource is dynamically allocated to the upstream processing element in response to the input rate of the upstream processing element varying. Data flow is dynamically controlled between the upstream processing element and at least one downstream processing element.

Abstract: An integrated circuit for a smart card includes a plurality of data buffers and a processor. In particular, the processor selectively allocates data buffers from the plurality thereof and exchanges data therewith based upon different types of data. As such, the processor advantageously changes the allocation of the buffers for different data types based upon various bandwidth constraints in a particular smart card environment to enhance bandwidth utilization.

Abstract: The present invention relates to a method for data transfer between a host and a device as well as to respective apparatus. A host is seen as a communication apparatus which organizes data traffic. A device is seen as dependent on the host. In a tiered-star topology there are usually multiple devices connected to one host. A method for data transfer between a host and a device through pipes is presented. The available memory in the host is divided into multiple segments. The assignment of segments is changed between pipes in dependence on the pipe traffic.

Abstract: Systems and methods, including computer software stored on a machine-readable medium for performing operations, can be implemented for allocating memory. Multiple channels are defined on a mobile device. Each channel can be adapted to receive a predetermined type of content for access on the mobile device. An amount of memory allocated to each channel for storing data is defined. Data identifying a new amount of memory allocated to one of the channels is received, and the amount of memory allocated to the channel is adjusted based on the data identifying the new amount of memory.

Abstract: A transmission apparatus includes a memory adapted to store data to be transmitted, a transmission unit adapted to transmit, via a network, the data to be transmitted to a destination apparatus connected to the network, and a first rate controller adapted to control a first rate such that when the data to be transmitted having a size greater than the capacity of a transmission buffer of the transmission unit is transferred from the memory to the transmission buffer, the first rate at which the data is transferred from the memory to the transmission buffer is controlled to restrict the amount of data to be transmitted stored in the transmission buffer.

Abstract: A peripheral interface and process for data transfer, especially for laser scanning microscopes. The peripheral interface permits a gap-free transfer of data with high transmission speed using a non-real-time-enabled operating system of the control computer. A peripheral connection for a peripheral device and a control unit serving for one-way transmission of a predetermined amount of data from the control computer to the peripheral device and/or vice versa accesses via a system bus of a control computer, a work memory region of the control computer serves as buffers preassigned to it, where the control unit prepares for the control computer a progress report of the transfer for retrieval and the control unit of the control computer is informed of the progress of the processing of the buffer independently of the transfer.

Abstract: An embodiment of the present invention is disclosed to include a SATA Switch allowing for access by two hosts to a single port SATA device Further disclosed are embodiments for reducing the delay and complexity of the SATA Switch.

Abstract: A memory buffer allocation device for allocating a memory buffer in a virtual computer system in which a plurality of virtual operating systems operate in time-sharing on one CPU having the memory buffer, includes a memory buffer division unit which divides the memory buffer into a number (n) of areas and reserves a division unit number (m) of areas out of the n areas as a dedicated memory buffer and the other areas except for the number n of the areas as a shared memory buffer. The device also includes a memory buffer allocation unit which allocates each area of the dedicated memory buffer to a number m of domains and each area of the shared memory buffer to other n-m domains except for the number m of domains, wherein the domains are of the virtual operating systems that are operating in the virtual computer system.

Abstract: Architecture that allows programmatic association of devices to sessions and redirects input to the desired session. When the solution is active, input from the devices is not realized by the standard operating system input stack, thereby allowing even reserved key sequences such as Ctrl-Alt-Del to be intercepted and redirected to a desired session. Moreover, in addition to redirecting input to a specific session, the architecture facilitates the filtering of input from unwanted/unmapped devices, the interception and filtering or redirection of reserved key sequences such as Ctrl-Alt-Del, and the maintenance of input state for each session.

Abstract: A system and a process for deploying a computer file involves a client computer applying the computer file concurrently with downloading the computer file from a file server. The concurrent operations can be performed even when the data of the computer file is downloaded out of order. The computer file includes a plurality of file segments. The client computer obtains information defining the file segments and monitors the received data of the computer file during downloading. When downloading of a file segment is complete, the client computer applies the completed segment concurrently with receiving other segments of the computer file from the file server. The process can be used when the computer file is downloaded using a multicast protocol, but is not limited to use with multicast protocols. The client computer can request only needed segments of the computer file.

Abstract: A signal processing system comprising buffer control logic arranged to allocate a plurality of buffers for the storage of information fetched from at least one memory element. Upon receipt of fetched information to be buffered, the buffer control logic is arranged to categorise the information to be buffered according to at least one of: a first category associated with sequential flow and a second category associated with change of flow, and to prioritise respective buffers from the plurality of buffers storing information relating to the first category associated with sequential flow ahead of buffers storing information relating to the second category associated with change of flow when allocating a buffer for the storage of the fetched information to be buffered.

Abstract: A buffer pool for a database application is maintained in a volatile main memory component. A control portion that corresponds to a block of application data residing on a non-volatile, asymmetric memory component and that includes a reference to a location of the block of application data on the non-volatile, asymmetric memory component is added to the buffer pool maintained in the volatile main memory component. The control portion from the buffer pool maintained in the volatile main memory component that corresponds to the block of application data is accessed and the location of the block of application data on the non-volatile, asymmetric memory component is identified. Based on identifying the location of the block of application data on the non-volatile, asymmetric memory component, the database application is enabled to access the block of application data directly from the non-volatile, asymmetric memory component.

Abstract: A buffer management mechanism in a multi-core processor for use on a modem in a telecommunications network is described herein. The buffer management mechanism includes a buffer module that provides buffer management services for one or more Layer 2 applications, wherein the buffer module at least provides a user space application interface to application software running in user space. The buffer management mechanism also includes a buffer manager that manages a plurality of separate pools of tokens, wherein the tokens comprise pointers to memory areas in external memory. In addition, the buffer management mechanism includes a custom driver that manages Data Path Acceleration Architecture (DPAA) resources including buffer pools and frame queues to be used for user plane data distributing.

Abstract: The USB interface data transmission device comprises a USB interface controller unit, a dynamic data transmission unit, a central controller unit, a transmission mode configuration unit, a driver program memory and a data transmission interface. In them: The dynamic data transmission unit includes a data input node and a data output node, wherein the data input node supports the data downloading and the data output node support the data uploading, while when necessary the data input node and the data output node support each other's functions by changing their respective data uploading and downloading functions. In a download mode both the data input node and the data output node support the data downloading operation and in an upload mode both support the data uploading operation.

Abstract: Method and system for efficient buffer management for layer 2 through layer 5 network interface controller applications are provided. Aspects of the method may comprise determining whether an active NIC connection is an L2 type, an L4 type, or an L5 type. At least one buffer descriptor may be cached locally on a network interface controller (NIC) managed by a NIC application. The buffer descriptor is associated with the determined type of the active NIC connection. If the at least one active NIC connection is of the L2 or L4 type, the buffer descriptor may comprise at least one of a receive (RX) buffer descriptor and a transmit (TX) buffer descriptor. If the NIC connection is of the L5 type, the buffer descriptor may comprise at least one of a upper translation page table (TPT) entry and a lower TPT entry.

Abstract: A hybrid serial peripheral interface (SPI) data transmission architecture adapted in a network device for connecting a host and a network is provided. The architecture comprises a RX buffer and RX SPI for maintaining a data receiving process, a TX buffer and TX SPI for maintaining a data transmission process, a configuration and status register and a hybrid SPI processing module. The hybrid SPI processing module makes the RX SPI performs the data transmission process as well when the RX SPI idles and the data transmission process proceeds at the same time and makes the TX SPI to performs the data receiving process as well when the TX SPI idles and the data receiving process proceeds at the same time. A hybrid SPI data transmission method is disclosed herein as well.

Abstract: An embodiment of the present invention is disclosed to include a hard disk drive allowing for access by two hosts to a device. Further disclosed are embodiments for reducing the delay and complexity of the SATA disk drive.

Abstract: Disclosed herein is a memory control apparatus including: a plurality of buffers configured to store data; a plurality of input ports configured to input the data to be written into the buffers; a plurality of output ports configured to output the data read from the buffers; a write control circuit configured to write the data inputted via each of the input ports into an unused one of the buffers; and a read control circuit configured to read the data written into the unused buffer, and supply the read data to a particular one of the output ports corresponding to a destination of the data.

Abstract: A storage subsystem includes a variable-size write buffer that temporarily stores write data received from a host system. The storage subsystem is capable of adjusting the size of the write buffer so as to vary both the performance (e.g., sustained write speed) of the storage subsystem and a risk of data loss. In one embodiment, the storage subsystem implements a command set that enables the host system to directly control the size of the write buffer. The storage subsystem may additionally or alternatively be capable of adjusting the size of the write buffer based on monitored operating conditions, such as the temperature, the stability/consistency of a power signal received from the host system, and/or the elapsed time since the storage subsystem was last powered up.

Abstract: For an information retrieval system coupled to a buffer pool maintaining a plurality of pages of recently accessed information for subsequent re-access, a technique for starting the buffer pool is provided. The technique facilitates a quicker start to the buffer pool by deferring allocation of page storing portions, for example, until they are needed. The technique makes the buffer pool available for storing pages while deferring allocation of a page storing portion of the buffer pool and allocates the page storing portion of the buffer pool in response to a demand to store pages to the buffer pool. The technique may be used to re-start a buffer pool with pages stored to a memory coupled to the information retrieval system where the pages where stored upon a buffer pool shutdown. Further, buffer pool readers or prefetchers may be configured to read pages for storing to the buffer pool and allocate the page storing portions of the buffer pool in response to instructions to read particular pages.

Abstract: A storage device includes a controller that is configured to execute safe deletion operations so as to free up storage space on the device in response to triggering events. The safe deletion operations ensure that the data states of a host device making use of the storage device and the storage device itself are synchronized so as to prevent deletion of data from the storage device before it is offloaded to another storage platform.

Abstract: Disclosed is a technique for flow control. It is detected that a work request is being transferred to an in-memory structure. A maximum limit is compared with a number of work requests stored in the in-memory structure. If the number of work requests stored in the in-memory structure equals the maximum limit, a notification is sent that indicates that additional work requests are not to be sent.

Abstract: A system, method, and computer readable article of manufacture for sharing buffer management. The system includes: a predictor module to predict at runtime a transaction data size of a transaction according to history information of the transaction; and a resource management module to allocate sharing buffer resources for the transaction according to the predicted transaction data size in response to beginning of the transaction, to record an actual sharing buffer size occupied by the transaction in response to the successful commitment of the transaction, and to update the history information of the transaction.

Abstract: A method and system for providing quality of service to a plurality of hosts accessing a common resource is described. According to one embodiment, a plurality of IO requests is received from clients executing as software entities on one of the hosts. An IO request queue for each client is separately managed, and an issue queue is populated based on contents of the IO request queues. When a host issue queue is not full, a new IO request is entered into the host issue queue and is issued to the common resource. A current average latency observed at the host is calculated, and an adjusted window size is calculated at least in part based on the current average latency. The window size of the issue queue is adjusted according to the calculated window size.

Abstract: An efficient low latency buffer, and method of operation, is described. The efficient low latency buffer may be used as a bi-directional memory buffer in an audio playback device to buffer both output and input data. An application processor coupled to the bi-directional memory buffer is responsive to an indication to write data to the bi-directional memory buffer reads a defined size of input data from the bi-directional memory buffer. The input data read from the bi-directional memory buffer is replaced with output data of the defined size. In response to a mode-change signal, the defined size of data is changed that is read and written from and to the bi-directional memory buffer. The buffer may allow the application processor to enter a low-powered sleep mode more frequently.

Abstract: An apparatus, computer program and method for packet buffer management in an IP network system. The apparatus includes at least one link queue buffer, a shared buffer, a buffer state detector, and a buffer manager. The at least one link queue buffer is allocated a buffer of a packet stored in a memory. The shared buffer is excessively allocated when exceeding a minimum buffer threshold value. The buffer state detector determines whether a buffer value stored in a link queue buffer of a corresponding link exceeds a preset minimum buffer threshold value. The buffer manager sets the shared buffer to be included in the link queue buffer if the stored buffer value exceeds the preset minimum buffer threshold value.

Abstract: A file to be read or written is designated and accessed from an access device side to a nonvolatile memory device. In an initialization after start-up of the power source, an empty capacity detector detects empty capacity parameters of a nonvolatile memory with dividing the memory into a plurality of regions. An empty capacity parameter notification part notifies the access device of the empty capacity parameters in a stepwise fashion whenever the empty capacity detector detects an empty capacity. With this, at the time when the empty capacity becomes not less than a capacity required to write file data, the data can be written to the nonvolatile memory without waiting for completion of the initialization, resulting in improvement of a response in the recording.

Abstract: A device and method of allocating pointers in a network switch includes allocating the first predetermined number of free pointers from a free list to a first in first out memory, allocating the second predetermined number of pointers to a linked list after the first predetermined number of pointers for the first in first out memory has been allocated, receiving a frame in the network switch, forwarding at least one pointer from the first in first out memory to an ingress module to buffer the frame, and forwarding pointers from the linked list to the first in first out memory to an ingress module to buffer the frame.

Abstract: A method and an apparatus for accessing data of a message memory of a communication module by inputting or outputting data into or from the message memory, the message memory being connected to a buffer memory assemblage and the data being transferred to the message memory or from the message memory, the buffer memory assemblage having an input buffer memory in the first transfer direction and an output buffer memory in the second transfer direction; and the input buffer memory and the output buffer memory each being divided into a partial buffer memory and a shadow memory, the following steps being performed in each transfer direction: inputting data into the respective partial buffer memory, and transposing access to the partial buffer memory and shadow memory, so that subsequent data can be inputted into the shadow memory while the previously inputted data are already being outputted from the partial buffer memory in the stipulated transfer direction.

Abstract: In an embodiment, an apparatus comprises a buffer, a plurality of processors, and a processor control module. The processor control module is to manage how many of the plurality of processors are used to process data from the buffer based at least in part on an amount of the data stored in the buffer.

Abstract: Dynamic allocation of cache buffer slots includes receiving a request to perform an operation that requires a storage buffer slot, the storage buffer slot residing in a level of storage. The dynamic allocation of cache buffer slots also includes determining availability of the storage buffer slot for the cache index as specified by the request. Upon determining the storage buffer slot is not available, the dynamic allocation of cache buffer slots includes evicting data stored in the storage buffer slot, and reserving the storage buffer slot for data associated with the request.

Abstract: A computer implemented method, data processing system, and computer program product for detecting circular buffer overflow. When an entry in the circular buffer is read, a valid mark bit in the entry is set to an inactive state and the location of the entry is stored as an entry previously processed. A valid mark bit of a next entry and the valid mark bit in the entry previously processed are read. Responsive to determining that the valid mark bit in the entry previously processed is in the inactive state and the valid mark bit in the next entry is in an active state, the next entry is read, the valid mark bit in the next entry is set to an incactive state, and the location of the next entry is stored as the entry previously processed. Responsive to determining that the valid mark bit in the entry previously processed is in the active state, a determination is made that a circular buffer overflow has occurred.

Abstract: Illustrated is a system and method for identifying a memory page that is accessible via a common physical address, the common physical address simultaneously accessed by a hypervisor remapping the physical address to a machine address, and the physical address used as part of a DMA operation generated by an I/O device that is programmed by a VM. It also includes transmitting data associated with the memory page as part of a memory disaggregation regime, the memory disaggregation regime to include an allocation of an additional memory page, on a remote memory device, to which the data will be written. It further includes updating a P2M translation table associated with the hypervisor, and an IOMMU translation table associated with the I/O device, to reflect a mapping from the physical address to a machine address associated with the remote memory device and used to identify the additional memory page.

Abstract: A method for maximizing I/O requests to a target port is provided. The method includes a storage controller obtaining an initiator allowed queue depth, receiving an I/O request and a current sequence identifier from an initiator logged into the target port, and determining if the initiator allowed queue depth is equal to a first queue depth corresponding to the initiator. If the initiator allowed queue depth is equal to the first queue depth then returning a queue full indication and a maximum sequence identifier equal to the current sequence identifier to the initiator. If the initiator allowed queue depth is not equal to the first queue depth then placing the I/O request on a queue, incrementing the first queue depth, and adjusting the maximum sequence identifier. Adjusting the maximum sequence identifier includes adding the current sequence identifier to the initiator allowed queue depth and subtracting the first queue depth.

Abstract: An efficient low latency buffer, and method of operation, is described. The efficient low latency buffer may be used as a bi-directional buffer in an audio playback device to buffer both output and input data. The audio buffer includes two modes of operation. The first mode replaces large segments of data at a first rate, and the second mode replaces smaller segments of data at a second rate, higher than the first rate. The first mode may make efficient use of the buffer for the output, data while the second mode may provide low latency for the buffering of the input data.

Abstract: Some of the embodiments of the present disclosure provide a method comprising managing a plurality of buffer addresses in a system-on-chip (SOC); and if a number of available buffer addresses in the SOC falls below a low threshold value, obtaining one or more buffer addresses from a memory, which is external to the SOC, to the SOC. Other embodiments are also described and claimed.

Abstract: System and methods for printing are provided. One such method includes determining a storage capacity available for use as a rasterizer buffer, and implementing a rasterizer buffer having a storage capacity that is responsive to the storage capacity determined to be available for use as a rasterizer buffer.