Abstract: A method for indicating an overload condition of a data storage system, comprises the steps of: defining one or more load indexes, wherein each of the load indexes has an overload threshold; and if one of the load indexes has met its respective overload threshold, providing an indicator of the overload condition of the storage system, else, monitoring the load indexes.

Abstract: Systems and methods are provided to enable a near-end receiver to control the far-end transmitter's data transmission such that the near-end receiver's TC data buffers do not overflow. In an embodiment, a high waterline and low waterline implemented into a near-end receiver are used to determine when the near-end receiver's TC data buffers are near maximum capacity. In an embodiment, the near-end receiver transmits a Packet Transfer Mode (PTM) All Idle Out Of Sync (AIOOS) codeword to the far-end transmitter when the high waterline is reached, and the near-end receiver stops transmitting the AIOOS codeword when the low waterline is reached.

Abstract: A computer program product is provided for performing an input/output (I/O) operation at a host computer system configured for communication with a control unit. The computer program product is configured to perform: sending a transport mode command message from a channel subsystem to the control unit, the command message including a command for data to be transferred to an I/O device controlled by the control unit; and sending a data transfer message to the control unit, the data transfer message having an amount of the data to be transferred, the amount of the data being less than or equal to a maximum amount of data, the maximum amount of data corresponding to a number of buffers associated with the control unit and a size of each of the number of buffers, the number and the size indicated by a value maintained in the host computer system.

Abstract: A transactional memory (TM) includes a control circuit pipeline and an associated memory unit. The memory unit stores a plurality of rings. The pipeline maintains, for each ring, a head pointer and a tail pointer. A ring operation stage of the pipeline maintains the pointers as values are put onto and are taken off the rings. A put command causes the TM to put a value into a ring, provided the ring is not full. A get command causes the TM to take a value off a ring, provided the ring is not empty. A put with low priority command causes the TM to put a value into a ring, provided the ring has at least a predetermined amount of free buffer space. A get from a set of rings command causes the TM to get a value from the highest priority non-empty ring (of a specified set of rings).

Abstract: An information memory system in which data received is divided into pieces of data, which are stored in memories in parallel, includes controller configured to storing a number of the divided pieces of data and monitoring a read request and a buffer full notice, in a case where the number of read requests does not reach the number of valid memory units and the buffer full notice continues in all buffers except for one buffer which does not output the read request, performing a read control corresponding to the buffers which output the buffer full notice, and performing control of the integration of a piece of data reconstructed, after being read from the memory unit corresponding to the buffer which does not output the read request and the pieces of data read from the memory units corresponding to the buffers which output the buffer full notice.

Abstract: A dynamic priority controller monitors a level of data in a display engine buffer and compares the level of data in the display engine buffer to a plurality of thresholds including a first threshold and a second threshold. When the level of data in the display engine buffer is less than or equal to the first threshold, the dynamic priority controller increases a priority for processing display engine data in a communication channel. When the level of data in the display engine buffer is greater than or equal to the second threshold, the dynamic priority controller decreases the priority for processing the display engine data in the communication channel.

Abstract: A dynamic priority controller monitors a level of data in a display engine buffer and compares the level of data in the display engine buffer to a plurality of thresholds including a first threshold and a second threshold. When the level of data in the display engine buffer is less than or equal to the first threshold, the dynamic priority controller increases a priority for processing display engine data in a communication channel. When the level of data in the display engine buffer is greater than or equal to the second threshold, the dynamic priority controller decreases the priority for processing the display engine data in the communication channel.

Abstract: Buffer memory reservation techniques for use with NAND flash memory include dynamically reserving regions of the buffer memory, responsive to a read/write request. Where the read/write request includes a plurality of data transfer requests, following completion of a data transfer request, the reserved buffer space may be recycled for use in a further data transfer request or for other purposes. During fulfillment of a read request, a buffer region is reserved from a larger buffer pool for a time period significantly smaller than the time required to execute a sense operation associated with the read request. The reserved buffer region may be reused for unrelated processes during execution of the sense operation.

Abstract: Data is written from a first domain to a FIFO memory buffer in a second domain. The first domain uses a first clock signal, the second domain uses a second clock signal and the memory buffer uses the first clock signal that is delivered alongside the data. The data is read from the memory buffer using the second clock signal. A read pointer is adjusted and synchronised with the delivered first clock signal. A token is generated using the delivered first clock signal, based on the read pointer. The token represents a capacity of the memory buffer having been made available. The token is passed to the first domain and synchronised with the first clock signal. The writing of data to the memory buffer is controlled based on a comparison between the synchronised token and a previously received token.

Abstract: Systems and methods are provided for a first-in-first-out buffer. A buffer includes a first sub-buffer configured to store data received from a buffer input, and a second sub-buffer. The second sub-buffer is configured to store data received from either the buffer input or the first sub-buffer and to output data to a buffer output in a same order as that data is received at the buffer input. Buffer control logic is configured to selectively route data from the buffer input or the first sub-buffer to the second sub-buffer so that data received at the buffer input is available to be output from the second sub-buffer in a first-in-first-out manner.

Abstract: A shared counter resource, such as a register, is disclosed in the hardware, where the register representing how much free space there is in the command queue is accessible to one or more processing elements. When a processing element reads the “reservation” register, the hardware automatically decrements the available free space by a preconfigured amount (e.g., 1) and returns the value of the free space immediately prior to the read/reservation. If the read returns 0 (or a number less than the preconfigured amount), there was insufficient free space to satisfy the request. In the event there was insufficient space to satisfy the request the reservation register may be configured to reserve however much space was available or to not reserve any space at all. Any number of processing elements may read these registers and various scenarios are described where the input and output queues are accessible via various processing elements.

Abstract: A technique for uplink data throttling includes buffer status report (BSR) scaling. A target data flow rate may be determined based on at least on condition of a wireless device. The buffer status report may be adjusted to cause the target flow rate and transmitted by the wireless device. The wireless device may then receive a flow control command based on the buffer status report.

Abstract: A method, apparatus and computer program product are provided herein to enable buffer initialization and/or clearance to occur on, for example, a mobile terminal. In some example embodiments, a method is provided that comprises receiving an indication that a buffer has been initialized by a host. The method of this embodiment may also include receiving source code from the host. In some example embodiments, the source code is received from a program running on the host and is configured to cause the buffer that has been initialized by the host to be cleared. The method of this embodiment may also include executing the source code such that the buffer that has been initialized by the host is cleared.

Abstract: One embodiment sets forth a technique for dynamically allocating memory during multi-threaded program execution for a coprocessor that does not support dynamic memory allocation, memory paging, or memory swapping. The coprocessor allocates an amount of memory to a program as a put buffer before execution of the program begins. If, during execution of the program by the coprocessor, a request presented by a thread to store data in the put buffer cannot be satisfied because the put buffer is full, the thread notifies a worker thread. The worker thread processes a notification generated by the thread by dynamically allocating a swap buffer within a memory that cannot be accessed by the coprocessor. The worker thread then pages the put buffer into the swap buffer during execution of the program to empty the put buffer, thereby enabling threads executing on the coprocessor to dynamically receive memory allocations during execution of the program.

Abstract: A data processing apparatus may include a buffer unit, a data write control unit, a data read control unit, and a buffer area determination unit. The data write control unit may write the input data to the storage area determined by the buffer area determination unit, and output a data write completion signal indicating that the writing of the data is completed when the writing of the input data is completed. The data read control unit may read the data from the storage area determined by the buffer area determination unit, and output a data read completion signal indicating that the reading of the data is completed when the output of the output data generated based on the read data is completed.

Abstract: An adaptive multi-thread buffer supports multiple writer process and reader processes simultaneously without blocking. Writer processes are assigned a reserved write slot using a writer index that is incremented for each write request. When a reserved write slot is not null, the buffer is resized to make room for new data. Reader processes are assigned a reserved read slot using a reader index that is incremented for each read request. When data is read out to the reader process, the read slot content is set to null. When a writer process attempts to write null data to a write slot, the buffer replaces the null write data with an empty value object so that content of the buffer is null only for empty slots. When an empty value object is read from a slot, the buffer replaces the content with null data to send to the reader process.

Abstract: A method and system of a host device hosting multiple workloads for controlling flows of I/O requests directed to a storage device is disclosed. In one embodiment, a type of a response from the storage device reacting to an I/O request issued by an I/O stack layer of the host device is determined. Then, a workload associated with the I/O request is identified among the multiple workloads based on the response to the I/O request. Further, a maximum queue depth assigned to the workload is adjusted based on the type of the response, where the maximum queue depth is a maximum number of I/O requests from the workload which are concurrently issuable by the I/O stack layer.

Abstract: A method, computer program product, and computing system for associating a first I/O scheduling queue with a first process accessing a storage network. The first I/O scheduling queue is configured to receive a plurality of first process I/O requests. A second I/O scheduling queue is associated with a second process accessing the storage network. The second I/O scheduling queue is configured to receive a plurality of second process I/O requests.

Abstract: An assembly where a number of receivers receiving packets for storing in queues in a storage and a means for de-queuing data from the storage. A controller determines addresses for the storage, the address being determined on the basis of at least a fill level of the queue(s), where information relating to de-queues addresses is only read-out when the fill-level(s) exceed a limit so as to not spend bandwidth on this information before it is required.

Abstract: Configurations providing a configurable buffer for storing incoming event tracking data communications in a lossy manner are described. In one aspect, a server can utilize the configurable buffer for storing the incoming event tracking data communications. When the buffer becomes full, the server can transmit the accumulated tracking data communications in the configuration buffer as a batch transmission. The server can discard any new incoming requests once the buffer becomes full. Further, the server can replace data in the buffer with new incoming requests based on one or more criterion if the buffer is full. In some implementations, the server transmits the batch of the accumulated tracking data communications in the configurable buffer after a predetermined time has elapsed.

Abstract: There are disclosed systems and methods for reducing the average delay and the average delay variation of network communication data in a buffer. The buffer comprises a plurality of memory entries, and associated with the buffer is a read point and a write pointer. The buffer has a depth defined as the number of memory entries in the buffer between the memory entry pointed to by the read pointer and the memory entry pointed to by the write pointer. In one embodiment, at least one of the read pointer and the write pointer is initially set to establish the depth of the buffer to be a first value. The variation of the depth of the buffer is then monitored for a predetermined period of time as network communication data flows through the buffer. The depth of the buffer is then reduced based upon this monitoring.

Abstract: An embodiment of the present invention provides an apparatus, comprising a network adapter configured for wireless communication using more than one technology using distributed management and wherein the network adapter is configured to share a plurality of shared hardware components by automatically turning all other comms to OFF when one comm is turned to ON.

Abstract: A data processing apparatus includes a shared buffer; an issuing unit that issues a write address for writing incoming data to the shared buffer; a receiving unit that receives a returned read address for the data read from the shared buffer; a monitoring buffer that saves information indicating use status of an address for the shared buffer; and a monitoring unit that monitors write address issuance and returned read address reception, changes the information for the write address, from an unused state to a used state, when the write address is issued, and changes the information for a read address to be returned, from a used state to an unused state when the returned read address is received. The monitoring unit determines the address for the shared buffer is overlapping, when the information for the write address indicates a used state when the write address is issued.

Abstract: A system for increasing the efficiency of data transfer through a serializer-deserializer (SerDes) link, and for reducing data latency caused by differences between arrival times of the data on the SerDes link and the system clock with which the device operates.

Abstract: Systems and methods are provided for a first-in-first-out buffer. A buffer includes a first sub-buffer configured to store data received from a buffer input, and a second sub-buffer. The second sub-buffer is configured to store data received from either the buffer input or the first sub-buffer and to output data to a buffer output in a same order as that data is received at the buffer input. Buffer control logic is configured to selectively route data from the buffer input or the first sub-buffer to the second sub-buffer so that data received at the buffer input is available to be output from the second sub-buffer in a first-in-first-out manner.

Abstract: A system and method for transmitting and presenting streaming digital information signals that optimizes performance in the context of goodput, throughput, delay, receiver buffer requirements and tolerance to loss and jitter. The method provides ordering packets of information based on a priority associated with each of the packets; managing the flow of the packets into and out of a buffer; adjusting the rate at which the packets are provided to a communication medium; and transmitting and retransmitting the packets as needed.

Abstract: First in, first out (FIFO) queues may be used to transfer data between a producer clock domain and a number of consumer clock domains. In one implementation, a control component for the FIFO queues may include a number of counters, corresponding to each of the consumer clock domains, each of the counters maintaining a count value relating to an amount of data read by the corresponding consumer clock domain. The control component may additionally include a credit deduction component coupled to the count values of the counters, the credit deduction component determining whether any of the count values is above a threshold, and in response to the determination that any of the count values is above the threshold, reducing the count value of each of the counters and issuing a write pulse signal to the producer clock domain, the write pulse signal causing the producer clock domain to perform a write operation to the FIFO queues.

Abstract: A first network device including a first port to provide first data traffic to a first storage area network, a second port to provide second data traffic to a local area network, and memory shared between the first port and the second port to temporarily store the first data traffic in N first buffers and the second data traffic in M second buffers. A queue control module allocates a first memory space of the N first buffers to the first port and a second memory space of the M second buffers to the second port. An adjustment module adjusts a first amount of the first memory space and a second amount of the second memory space in response to a congestion event caused by a first data traffic. Up to all of the first memory space and the second memory space is allocated to the N first buffers.

Abstract: A method of operating an electronic system comprises storing information corresponding to an input data stream in a first memory having a first operating rate, detecting an overflow condition of the first memory, generating overflow information in response to the detection of the overflow condition, storing the overflow information in a second memory having a second operating rate slower than the first operating rate, transferring the overflow information from the detector to a third memory at a first transfer rate corresponding to the first operating rate, temporarily storing the overflow information in the third memory, and transferring the stored overflow information to the second memory at a second transfer rate corresponding to the second operating rate, and combining the information stored in the first memory with the overflow information stored in the second memory to produce an output data stream.

Abstract: A gasket of a data processing device controls the number of released storage locations of a buffer where read and write access requests are stored so that more read access requests can be stored without a corresponding increase in the amount of space at the buffer to store write access requests. An interface of the gasket accepts new access requests from one or more requesting modules only when a number of released storage locations at a buffer associated with the interface (referred to as an outbound buffer) is above a threshold number. As long as the number of stored access requests at the outbound buffer are less than a threshold amount, a buffer location can be immediately released. In addition, the gasket is configured to issue read access requests from the outbound buffer without regard to whether the inbound buffer has space available.

Abstract: In one embodiment, a method includes determining whether producer-consumer ordering rules have been met for a first transaction to be sent from a source agent to a target agent via a fabric, and if so a first request for the first transaction is sent from the source agent to the fabric in a first clock cycle. Then a second request can be sent from the source agent to the fabric for a second transaction in a pipelined manner. Other embodiments are described and claimed.

Abstract: Managing commands that have not been executed is simplified while maintaining a state in which real-time commands can be executed. A printer 2 has a write control unit 21A that writes received commands to a receive buffer 31, a command execution unit 21B that executes the written commands, and a real-time command execution unit 21C that executes written commands that are real-time commands. The printer 2 enters a full-buffer mode as needed by the capacity of available storage space in the receive buffer 31, and when in the full-buffer mode the write control unit 21A cyclically writes commands to an auxiliary space created in the receive buffer, and the real-time command execution unit 21C reads and executes real-time commands from the auxiliary space.

Abstract: A modular system for acquiring biometric data includes a plurality of data acquisition modules configured to sample biometric data from at least one respective input channel at a data acquisition rate. A representation of the sampled biometric data is stored in memory of each of the plurality of data acquisition modules. A central control system is in communication with each of the plurality of data acquisition modules through a bus. The central control system is configured to collect data asynchronously, via the bus, from the memory of the plurality of data acquisition modules according to a relative fullness of the memory of the plurality of data acquisition modules.

Abstract: An apparatus consisting of a digital communication channel comprised of a multiplicity of lanes where data is striped across the lanes in a predefined sequence. Each lane has the ability to be powered down or powered up in response to the amount of data being held in a transmit buffer at one end of the communication channel. The method consists of monitoring the amount of data being held in the transmit buffer; making the decision of how many lanes are required based on the amount of data; sending signals to cause the required number of lanes to be powered down or powered up; and performing the required power down or power up action at the particular transmitter and receiver.

Abstract: A system for managing time-stamped events with uncertain events-sequence signalling, including a list of variables of which a change of value must lead to the detection of an event to be time-stamped and to be saved; means, for each variable, for positioning a marker indicating the quality of the time-stamping of said event; a buffer for the storage, before they are read by client software, of said events to be time-stamped and to be saved, associated respectively with a time-stamping time, said time-stamped events read by the client software being erased from the buffer; means for enabling and for disabling means for saving in a history the values of the variables corresponding to said time-stamped events that have been read.

Abstract: A tape drive, tape drive recording system, and method are provided for improving tape speed selection during data transfer. The tape drive includes a buffer, a tape for recording the data to be temporarily stored in the buffer, and a read head. The tape drive further includes a reading controller that initially sets a tape speed such that a drive transfer rate matches a host transfer rate as closely as possible and that drives the tape at the tape speed. To address backhitching caused by one or more host transfer halts, the reading controller subsequently adjusts the tape speed such that the drive transfer rate is lower than the host transfer rate by recalculating the host transfer rate in consideration of the host transfer and the host transfer halt and setting the tape speed such that the drive transfer rate matches the recalculated host transfer rate as closely as possible.

Abstract: Synthesizable code representing first-in-first out (FIFO) memories may be used to produce FIFO memories in a hardware element or system. To more efficiently use a memory element that stores the data in a FIFO, a code generator may generate a wrapper that enables the FIFO to use a memory element with different dimension (i.e., depth and width) than the FIFO's dimensions. For example, the wrapper enables a 128 deep, 1 bit wide FIFO to store data in a memory element with 16 rows that store 8 bits each. To any system communicating with the FIFO, the FIFO behaves like a 128×1 FIFO even though the FIFO is implemented using a 16×8 memory element. To do so, the code generator may generate a wrapper which enables the folded memory element to behave like a memory element that was not folded.

Abstract: A data transfer apparatus includes a virtual channel unit configured to time share a serial bus for a first virtual channel and a second virtual channel and include a buffering control unit configured to receive data via the first virtual channel and the second virtual channel, first and second receive buffers being configured to store the data received via the first virtual channel and the second virtual channel, respectively; and a switching unit configured to control storing the data received via the first virtual channel in the second receive buffer when the buffering control unit receives the data from another data transfer apparatus which is configured to use only the first virtual channel and the capacity of the first receive buffer is smaller than that of the second receive buffer.

Abstract: A method for dynamically enabling and disabling use of XFR_RDY is disclosed herein. In one embodiment of the invention, such a method includes receiving a write command at a target and determining whether XFR_RDY is enabled or disabled for the write command. In the event XFR_RDY is disabled, the method determines whether one or more buffers are available at the target. If at least one buffer is available, the method processes the write command by writing data associated with the write command to the one or more buffers. The method then returns information indicating the number of buffers that are still available at the target after completing the write command. A corresponding apparatus and computer program product are also disclosed and claimed herein.

Abstract: A method, computer program product, and computing system for associating a first I/O scheduling queue with a first process accessing a storage network. The first I/O scheduling queue is configured to receive a plurality of first process I/O requests. A second I/O scheduling queue is associated with a second process accessing the storage network. The second I/O scheduling queue is configured to receive a plurality of second process I/O requests.

Abstract: A method and system are disclosed for network adaptor optimization and interrupt reduction. The method may also build an outbound buffer list based on outgoing data and add the outgoing data to an outbound buffer queue. Furthermore, the method may set a buffer state from an empty state to a primed state to indicate that the outgoing data is prepared for transmitting and signal a network adaptor with a notification signal.

Abstract: First in, first out (FIFO) queues may be used to transfer data between a producer clock domain and a number of consumer clock domains. In one implementation, a control component for the FIFO queues may include a number of counters, corresponding to each of the consumer clock domains, each of the counters maintaining a count value relating to an amount of data read by the corresponding consumer clock domain. The control component may additionally include a credit deduction component coupled to the count values of the counters, the credit deduction component determining whether any of the count values is above a threshold, and in response to the determination that any of the count values is above the threshold, reducing the count value of each of the counters and issuing a write pulse signal to the producer clock domain, the write pulse signal causing the producer clock domain to perform a write operation to the FIFO queues.

Abstract: A queue number acquiring unit acquires a command queuing number that is the upper limit of the number of process-waiting instructions that can be stored in each of storages that make up a virtual disk for each storage. A minimum queue number selecting unit selects the minimum value of the command queuing numbers of the storages that make up the virtual disk as a minimum queue number. A queue number setting unit sets the selected minimum queue number as the command queuing number of the virtual disk that includes the storage device of which the command queuing number is selected as the minimum queue number for each virtual disk.

Abstract: In an information-processing apparatus including a plurality of modules and a first arbiter which arbitrates bus-access requests of the plurality of modules, at least one of the plurality of modules includes a plurality of submodules and a second arbiter which arbitrates bus-access requests of the plurality of submodules and transmits at least one of the bus-access requests of the plurality of submodules to the first arbiter.

Abstract: An integrated circuit comprises a shared resource for providing data to a buffer. The buffer is coupled to a buffer level monitor and a filling circuit. An access-requesting circuit is coupled to the shared resource for receiving the data from the shared resource when the access-requesting circuit has access to the shared resource. An arbiter is coupled to the shared resource, the filling circuit, and the access-requesting circuit, for receiving access requests from the filling circuit and from the access-requesting circuit, and for granting to a selected one thereof access to the shared resource. A controller is coupled to the buffer level monitor and to the access-requesting circuit, for causing the access-requesting circuit to reduce a rate of access requests sent to the arbiter when a condition involving the monitored level of data in the buffer indicates an anticipated violation of a timing constraint.

Abstract: A method for enhancing data transmission efficiency in a data transmission system having a host, a subsystem and a transmission interface, utilized for the host to transmit and receive a data from a memory of the subsystem via the transmission interface includes steps of the host outputting a query command to the subsystem via the transmission interface for querying available memory utilization of the subsystem; the subsystem outputting a return message to the host via the transmission interface for indicating the available memory utilization according to the query command; and controlling data transmission from the host to the subsystem according to the return message.

Abstract: This disclosure proposes techniques for demand paging for an IO device (e.g., a GPU) that utilize pre-fetch and pre-back notification event signaling to reduce latency associated with demand paging. Page faults are limited by performing the demand paging operations prior to the IO device actually requesting unbacked memory.

Abstract: Techniques are described for reducing write operations in memory. In use, write operations to be performed on data stored in memory are identified. A difference is then determined between results of the write operations and the data stored in the memory. Difference information is stored in coalescing memory buffers. To this end, the write operations may be reduced, utilizing the difference information.

Abstract: A method for power management is disclosed. The method may include monitoring requests for access to a memory of a memory subsystem by one or more processor cores; and monitoring requests for access to the memory conveyed by an input/output (I/O) unit. The method may further include determining if at least a first amount of time has elapsed since any one of the processor cores has asserted a memory access request and determining if at least a second amount of time has elapsed since the I/O unit has conveyed a memory access request. A first signal may be asserted if the first and second amounts of time have elapsed. A memory subsystem may be transitioned from operating in a full power state to a first low power state responsive to assertion of the first signal.

Abstract: An input/output processor for speeding the input/output and memory access operations for a processor is presented. The key idea of an input/output processor is to functionally divide input/output and memory access operations tasks into a compute intensive part that is handled by the processor and an I/O or memory intensive part that is then handled by the input/output processor. An input/output processor is designed by analyzing common input/output and memory access patterns and implementing methods tailored to efficiently handle those commonly occurring patterns. One technique that an input/output processor may use is to divide memory tasks into high frequency or high-availability components and low frequency or low-availability components.