Abstract: A tape drive, tape drive recording system, and method are provided for improving tape speed selection during data transfer. The tape drive comprises a buffer, a tape for recording the data to be temporarily stored in the buffer, and a read head. The tape drive further comprises a reading controller that initially sets a tape speed such that a drive transfer rate matches a host transfer rate as closely as possible and that drives the tape at the tape speed. To address backhitching caused by one or more host transfer halts, the reading controller subsequently adjusts the tape speed such that the drive transfer rate is lower than the host transfer rate by recalculating the host transfer rate in consideration of the host transfer and the host transfer halt and setting the tape speed such that the drive transfer rate matches the recalculated host transfer rate as closely as possible.

Abstract: A first network device includes a first port to provide first data traffic to a first storage area network, a second port to provide second data traffic to a local area network, and memory shared between the first port and the second port to temporarily store the first data traffic in N first buffers and the second data traffic in M second buffers. A queue control module allocates a first memory space of the N first buffers to the first port and a second memory space of the M second buffers to the second port. An adjustment module adjusts a first amount of the first memory space and a second amount of the second memory space in response to a congestion event is caused by a first data traffic. Up to all of the first memory space and the second memory space is allocated to the N first buffers.

Abstract: A method for operating a storage system, including storing data redundantly in the system and measuring respective queue lengths of input/output requests to operational elements of the system. The queue lengths are compared to an average queue length to determine respective performances of the operational elements of the storage system. In response to the average queue lengths and a permitted deviation from the average an under-performing operational element among the operational elements is identified. An indication of the under-performing operational element is provided to host interfaces in the storage system. One of the host interfaces receives requests for specified items of the data directed to the under-performing element, and in response to the indication, some of the requests are diverted from the under-performing operational element to one or more other operational elements of the storage system that are configured to provide the specified items of the data.

Abstract: A data transfer device includes a data buffer, an odd number flag, and a control unit. The data buffer holds an even number of data blocks from a data transfer controller. The odd number flag is set when the number of data blocks to be transferred to a receiving device is odd. The control unit transfers an even number of data blocks to the receiving device for each data transfer cycle with respect to the receiving device, and transfers one data block to the receiving device in a last transfer cycle when the odd number flag is set. Thus, also when the data transfer controller which transfers data in a unit of an even number of data blocks is used, not only an even number of data blocks but an odd number of data blocks may be transferred to the receiving device.

Abstract: A computer implemented method for writing to a software bound ring buffer. A network adapter may determine that data is available to write to the software bound ring buffer. The network adapter determines that a read index is not equal to a write index, responsive to a determination that data is available to write to the software bound ring buffer. The network adapter writes the data to memory referenced by the hardware write index, wherein memory referenced by the write index is offset according to an offset, and the memory contents comprise a data portion and a valid bit. The network adapter writes an epoch value of the write index to the valid bit. The network adapter increments the write index, responsive to writing the data to memory referenced by the write index. Further disclosed is method to access a hardware bound ring buffer.

Abstract: A system and method are provided that involve a host computing machine and an SR IOV storage adapter in which the host machine hosts a virtual machine having a guest operating system (guest) coupled for direct passthrough IOV data path and also hosts a virtualization intermediary; a guest operating system (guest) and a virtualization intermediary exchange information concerning IO completions through a shared memory space; the guest writes information to a shared memory space that is indicative of whether an IO completion queue has reached a fill level since the most recently dispatched interrupt at which it is unsafe to coalesce an interrupt; the virtualization intermediary writes information to the shared memory space that is indicative of the interrupt most recently delivered to the guest; the virtualization intermediary reads the information written by the guest to the shared memory space that is indicative of whether an IO completion queue has reached a fill level since the most recently dispatched inter

Abstract: Methods and apparatus for improved performance in communications between a SAS/STP initiator device and a plurality of SATA storage devices coupled with the initiator through an enhanced switching device. The switching device is enhanced in accordance with features and aspects hereof to receive a DMA SETUP FIS from a SATA storage device and to transmit multiple modified DMA SETUP FISs to the initiator where each modified DMA SETUP FIS comprises a subcount less than the maximum count in the received DMA SETUP FIS.

Abstract: A memory device and a method of managing a memory are provided. The memory device includes a command queue configured to receive a first command from a host to store the first command, and to read and transmit the first command, a controller configured to read, from a storage device, data corresponding to the first command transmitted from the command queue, and to store the data in a buffer memory, and a first memory configured to store a data list of data stored in the buffer memory, wherein, in response to the command queue receiving the first command from the host, the controller updates the data list of data stored in the first memory.

Abstract: A double data rate bus system includes a host-network interface card configuration wherein the host is configured to recognize the network interface card to establish a double data rate bus between the host and the network interface card. The host is configured to generate a plurality of generic data frame queues. Each of the generic data frame queues is configured to receive and to transmit generic data frames via the double data rate bus. The network interface card is configured to transmit a plurality of dynamic memory access read requests to the host via the double data rate bus. The host is configured to allow each of the plurality of dynamic memory access read requests to remain pending prior to responding to any one of the plurality of dynamic memory access read requests.

Abstract: A management apparatus and method that manage a storage system, in which an access node and a storage node, with which the management apparatus is in communication via the network. The management apparatus includes a logical volume judging unit that acquires a plurality of processing requests to each of the plurality of storage areas, references a logical volume allocation information storage unit that stores a correspondence relationship between the plurality of storage areas and the plurality of logical volumes in the storage node, and judges a logical volume corresponding to a storage area to become a processing object of each processing request, and a processing request breakdown calculating unit that counts an acquisition count of each processing request for each logical volume based on a judgment result by the logical volume judgment unit, and calculates a proportion of each acquisition count to a total of respective acquisition counts.

Abstract: A FIFO memory has integrated error management to react to different errors according to the current state of operation of the input and output as well as internal conditions such as buffer memory status. The FIFO memory completes or aborts current operations according to state and leaves the FIFO memory in known condition following error handling. Thus, data sent to a host avoids data gaps or data overlaps because the FIFO memory leaves operations in a known state before reporting the error to a controller.

Abstract: A network device may include an off-chip memory to store a free-list of buffer pointers. The network device may further include an on-chip controller that includes a prefetch buffer. The prefetch buffer may store unallocated buffer pointers that point to available memory locations in a different off-chip memory. The on-chip controller may receive an unallocated buffer pointer, determine, in response to receiving the unallocated buffer pointer, whether the prefetch buffer is full, store the unallocated buffer pointer in the prefetch buffer when the prefetch buffer is determined not to be full, and store the unallocated buffer pointer in the free-list, in the off-chip memory, when the prefetch buffer is determined to be full.

Abstract: An integrated circuit and a method for reducing violations of a timing constraint. The integrated circuit comprises a shared resource for providing data and a buffer for storing data. A buffer level monitor is coupled to the buffer, for monitoring a monitored level of data in the buffer. A retrieving circuit is coupled to the buffer, for retrieving the data from the buffer, according to a timing constraint. A filling circuit is coupled to the buffer for writing the data to the buffer and coupled to the shared resource for receiving the data from the shared resource when the filling circuit has access to the shared resource. An access-requesting circuit is coupled to the shared resource for receiving the data from the shared resource when the access-requesting circuit has access to the shared resource.

Abstract: A data storage device is provided, including a first data storage device electrically storing write data, a second data storage device magnetically storing write data, and a controller partitioning write data into first and second write data portions. The first write data portion is programmed to the first data storage device and the second write data portion if magnetically written to the second data storage device at the same time.

Abstract: Disclosed are a method, upstream processing node, and computer readable medium for dynamically stabilizing a stream processing system. The method includes receiving at least one computing resource allocation target. The method further includes determining that an input data flow rate of at least one upstream processing element varies. The computing resource is dynamically allocated to the upstream processing element in response to the input rate of the upstream processing element varying. Data flow is dynamically controlled between the upstream processing element and at least one downstream processing element.

Abstract: A playing state presentation system has a contents server for supplying consecutive contents data, and a contents playing device for obtaining and playing the contents data. The contents playing device includes: a reception unit for receiving the contents data from the contents server by wireless communication; a supplying unit for supplying the contents data to a playing unit which successively plays the contents data received by the reception unit, with the contents data being supplied at a supply speed unique to the contents data; a playing state prediction unit for predicting whether or not the contents data can be continuously played at the playing unit, as a playing state; and a presentation unit for presenting the predicted playing state.

Abstract: A system for managing a circular buffer memory includes a number of data writers, a number of data readers, a circular buffer memory; and logic configured to form a number of counters, form a number of temporary variables from the counters, and allow the data writers and the data readers to simultaneously access locations in the circular buffer memory determined by the temporary variables.

Abstract: A peripheral interface and process for data transfer, especially for laser scanning microscopes. The peripheral interface permits a gap-free transfer of data with high transmission speed using a non-real-time-enabled operating system of the control computer. A peripheral connection for a peripheral device and a control unit serving for one-way transmission of a predetermined amount of data from the control computer to the peripheral device and/or vice versa accesses via a system bus of a control computer, a work memory region of the control computer serves as buffers preassigned to it, where the control unit prepares for the control computer a progress report of the transfer for retrieval and the control unit of the control computer is informed of the progress of the processing of the buffer independently of the transfer.

Abstract: An optical disc drive is provided, mainly comprising a buffer, a processor and a driving module for accessing an optical disc. The optical disc drive receives a plurality of write commands. Each write command comprises a data block and a destination address. The buffer buffers data blocks to be recorded to the optical disc with corresponding write commands in either a random mode or a sequential mode. The processor schedules a recording operation based on the write commands, and selectively switches the buffer to the random mode or to the sequential mode based on arrangements of data blocks buffered in the buffer. The driving module is controlled by the processor to perform the recording operation, whereby the data blocks are recorded to the optical disc when a start recording condition is met. Specifically, the start recording condition varies with the random or sequential modes.

Abstract: A device and method for transferring data is disclosed that facilitates data transfers between devices having different clock domains. The data transfer from one device to another occurs through a First In First Out memory (FIFO). The relative number of FIFO access cycles to the FIFO is controlled to maintain a desired FIFO fullness. Setting the desired FIFO fullness to a desired value allows control of data transfer latency between devices.

Abstract: A data processing apparatus may include a buffer unit, a data write control unit, a data read control unit, and a buffer area determination unit. The data write control unit may write the input data to the storage area determined by the buffer area determination unit, and output a data write completion signal indicating that the writing of the data is completed when the writing of the input data is completed. The data read control unit may read the data from the storage area determined by the buffer area determination unit, and output a data read completion signal indicating that the reading of the data is completed when the output of the output data generated based on the read data is completed.

Abstract: In one embodiment, payload of multiple threads between intellectual property (IP) cores of an integrated circuit are transferred, by buffering the payload using a number of order queues. Each of the queues is guaranteed access to a minimum number of buffer entries that make up the queue. Each queue is assigned to a respective thread. A number of buffer entries that make up any queue is increased, above the minimum, by borrowing from a shared pool of unused buffer entries on a first-come, first-served basis. In another embodiment, an interconnect implements a content addressable memory (CAM) structure that is shared storage for a number of logical, multi-thread ordered queues that buffer requests and/or responses that are being routed between data processing elements coupled to the interconnect. Other embodiments are also described and claimed.

Abstract: Systems and methods are provided for a first-in-first-out buffer. A buffer includes a first sub-buffer configured to store data received from a buffer input, and a second sub-buffer. The second sub-buffer is configured to store data received from either the buffer input or the first sub-buffer and to output data to a buffer output in a same order as that data is received at the buffer input. Buffer control logic is configured to selectively route data from the buffer input or the first sub-buffer to the second sub-buffer so that data received at the buffer input is available to be output from the second sub-buffer in a first-in-first-out manner.

Abstract: Disclosed is a technique for flow control. It is detected that a work request is being transferred to an in-memory structure. A maximum limit is compared with a number of work requests stored in the in-memory structure. If the number of work requests stored in the in-memory structure equals the maximum limit, a notification is sent that indicates that additional work requests are not to be sent.

Abstract: A storage device includes a controller that is configured to execute safe deletion operations so as to free up storage space on the device in response to triggering events. The safe deletion operations ensure that the data states of a host device making use of the storage device and the storage device itself are synchronized so as to prevent deletion of data from the storage device before it is offloaded to another storage platform.

Abstract: An interface system is disclosed. In one embodiment, the system includes a buffer that receives data from a source in a first clock domain and stores the data to be read by a destination in a second clock domain, wherein the buffer functions in both the first clock domain and the second clock domain; a write pointer that points to data written by the source; and a read pointer that points to data read by the destination. According to the system and method disclosed herein, the write pointer and the read pointer are utilized to enable the data to be transmitted from the first clock domain to the second clock domain asynchronously.

Abstract: Devices and methods for power management during media playback are provided. For example, an electronic device according to an embodiment may include storage, a decoder, an output buffer, and data processing circuitry. The storage may store compressed media data that may be decoded by the decoder. The output buffer may store the decoded media data before the decoded media data is played out. The data processing circuitry configured may measure a fullness of the output buffer and may set an operating frequency of the storage, the decoder, the output buffer, or the data processing circuitry, or a combination thereof, depending on a format of the compressed media data and the fullness of the output buffer.

Abstract: An apparatus, method, and system for implementing a hardware transactional memory (HTM) system with multiple levels of transactional buffers. The apparatus comprises a data cache configured to buffer data in a shared (by a plurality of processing cores) memory accessed by speculative memory access operations and to retain the data during at least a portion of an attempt to execute the atomic memory transaction. The apparatus also comprises an overflow detection circuit configured to detect an overflow condition upon determining that the data cache has insufficient capacity to buffer a portion of data accessed as part of the atomic memory transaction, as well as a buffering circuit configured to respond to the detection of the overflow condition by preventing the portion of data from being buffered in the data cache and buffering the portion of data in a secondary buffer separate from the data cache.

Abstract: A method and system for providing quality of service to a plurality of hosts accessing a common resource is described. According to one embodiment, a plurality of IO requests is received from clients executing as software entities on one of the hosts. An IO request queue for each client is separately managed, and an issue queue is populated based on contents of the IO request queues. When a host issue queue is not full, a new IO request is entered into the host issue queue and is issued to the common resource. A current average latency observed at the host is calculated, and an adjusted window size is calculated at least in part based on the current average latency. The window size of the issue queue is adjusted according to the calculated window size.

Abstract: In an embodiment, a combining write buffer is configured to maintain one or more flush metrics to determine when to transmit write operations from buffer entries. The combining write buffer may be configured to dynamically modify the flush metrics in response to activity in the write buffer, modifying the conditions under which write operations are transmitted from the write buffer to the next lower level of memory. For example, in one implementation, the flush metrics may include categorizing write buffer entries as “collapsed.” A collapsed write buffer entry, and the collapsed write operations therein, may include at least one write operation that has overwritten data that was written by a previous write operation in the buffer entry. In another implementation, the combining write buffer may maintain the threshold of buffer fullness as a flush metric and may adjust it over time based on the actual buffer fullness.

Abstract: A method and a system for implementing concurrent producer-consumer buffers are provided. The method and system in one aspect uses separate locks, one for putter and another for taker threads operating on a concurrent producer-consumer buffer. The locks operate independently of a notify-wait process.

Abstract: In a wireless network, the decision of when and whether to send unsolicited polls to a particular mobile wireless device may be made by monitoring communications conditions affecting the ability of the particular device to gain channel access, and sending unsolicited polls if the ability to gain channel access is below a threshold value. Such conditions may include one or more of channel load, device transmission load, collision rate, and number of mobile wireless devices contending for access.

Abstract: Buffering techniques for power management are described. A method may comprise modifying a power state for a communications sub-system and a computing sub-system from a higher power state to a lower power state, storing packets of information in a buffer for the communications sub-system during a communications idle duration period, generating a variable receive threshold value for the buffer, and transferring the stored packets of information from the buffer to the computing sub-system based on a variable receive threshold value. Other embodiments are described and claimed.

Abstract: In an embodiment, an apparatus comprises a buffer, a plurality of processors, and a processor control module. The processor control module is to manage how many of the plurality of processors are used to process data from the buffer based at least in part on an amount of the data stored in the buffer.

Abstract: The exemplary embodiment of the present invention provides a storage buffer management scheme for I/O store buffers. Specifically, the storage buffer management system as described within the exemplary embodiment of the present invention is configured to comprise storage buffers that have the capability to efficiently support 128 byte or 256 byte I/O data transmission lines. The presently implemented storage buffer management scheme enables for a limited number of store buffers to be associated with a fixed number of storage state machines (i.e., queue positions) and thereafter the allowing for the matched pairs to be allocated in order to achieve maximum store throughput for varying combinations of store sizes of 128 and 256 bytes.

Abstract: In an information-processing apparatus including a plurality of modules and a first arbiter which arbitrates bus-access requests of the plurality of modules, at least one of the plurality of modules includes a plurality of submodules and a second arbiter which arbitrates bus-access requests of the plurality of submodules and transmits at least one of the bus-access requests of the plurality of submodules to the first arbiter. The first arbiter gives priority to the module which transmits many bus-access requests, or the module which made a previous bus access, and limits the number of consecutive accesses made by the same module, so as to control the priority of accessing the bus by the plurality of modules. The second arbiter controls priority of accessing the bus by the plurality of submodules according to the free state of a buffer of each submodule, or the access type, whereby the bus-access requests made by the plurality of modules can be arbitrated, thus increasing bus-use efficiency.

Abstract: In a communication apparatus, a write controller writes received data in a temporary memory which serves as short-time storage. A read controller reads data out of the temporary memory. A discard controller controls discard operation of the data read out of the temporary memory.

Abstract: An integrated circuit includes a plurality of processing modules coupled by a network. A first processing module communicates with a second processing module based on transactions. A first wrapper means associated to the second processing module buffers data from the second processing module to be transferred over the network until a first amount of data is buffered and then transfers the first amount of buffered data to the first processing module.

Abstract: A computer implemented method, data processing system, and computer program product for detecting circular buffer overflow. When an entry in the circular buffer is read, a valid mark bit in the entry is set to an inactive state and the location of the entry is stored as an entry previously processed. A valid mark bit of a next entry and the valid mark bit in the entry previously processed are read. Responsive to determining that the valid mark bit in the entry previously processed is in the inactive state and the valid mark bit in the next entry is in an active state, the next entry is read, the valid mark bit in the next entry is set to an incactive state, and the location of the next entry is stored as the entry previously processed. Responsive to determining that the valid mark bit in the entry previously processed is in the active state, a determination is made that a circular buffer overflow has occurred.

Abstract: A method of managing a temporary memory includes: receiving a request to transfer data from a source location to a destination location, the data transfer request associated with an operation to be performed, the operation selected from an input into an intermediate temporary memory and an output; checking a two-state indicator associated with the temporary memory, the two-state indicator having a first state indicating that an immediately preceding operation on the temporary memory was an input to the temporary memory and a second state indicating that the immediately preceding operation was an output from the temporary memory; and performing the operation responsive to one of: the operation being an input operation and the two-state indicator being in the second state, indicating that the immediately preceding operation was an output; and the operation being an output operation and the two-state indicator being in the first state, indicating that the immediately preceding operation was an input.

Abstract: A data transfer device includes a data buffer, an odd number flag, and a control unit. The data buffer holds an even number of data blocks from a data transfer controller. The odd number flag is set when the number of data blocks to be transferred to a receiving device is odd. The control unit transfers an even number of data blocks to the receiving device for each data transfer cycle with respect to the receiving device, and transfers one data block to the receiving device in a last transfer cycle when the odd number flag is set. Thus, also when the data transfer controller which transfers data in a unit of an even number of data blocks is used, not only an even number of data blocks but an odd number of data blocks may be transferred to the receiving device.

Abstract: A method for minimizing delays in web conference switches between presenters and applications may include receiving a key frame of content selected by a user for sharing in response to the user being a presenter and having content to share. The method may also include storing the key frame of the selected content in a buffer in response to the user not being a current presenter. The method may additionally include sharing the key frame of the content with participants of the web conference, by the processing device, in response to an indication that a previous presenter has completed his presentation and the user being a next presenter in a presenter queue.

Abstract: Asynchronous network interface and method of synchronisation between two applications on different computers is provided. The network interface contains snooping hardware which can be programmed to contain triggering values comprising either addresses, address ranges or other data which are to be matched. These data are termed “trip wires”. Once programmed, the interface monitors the data stream, including address data, passing through the interface for addresses and data which match the trip wires which have been set. On a match, the snooping hardware can generate interrupts, increment event counters, or perform some other application-specified action. This snooping hardware is preferably based upon Content-Addressable Memory. The invention thus provides in-band synchronisation by using synchronisation primitives which are programmable by user level applications, while still delivering high bandwidth and low latency.

Abstract: An efficient low latency buffer, and method of operation, is described. The efficient low latency buffer may be used as a bi-directional buffer in an audio playback device to buffer both output and input data. The audio buffer includes two modes of operation. The first mode replaces large segments of data at a first rate, and the second mode replaces smaller segments of data at a second rate, higher than the first rate. The first mode may make efficient use of the buffer for the output, data while the second mode may provide low latency for the buffering of the input data.

Abstract: A technique for uplink data throttling includes buffer status report (BSR) scaling. A target data flow rate may be determined based on at least on condition of a wireless device. The buffer status report may be adjusted to cause the target flow rate and transmitted by the wireless device. The wireless device may then receive a flow control command based on the buffer status report.

Abstract: Provided are a relocation system and a relocation method capable of relocating a virtual volume that is formed based on thin provisioning while ensuring security against exhaustion of pools. A database stores attribute information for pools and virtual volumes for thin provisioning that exist in a storage device as well as parameters for predicting time period till exhaustion of the pools. When a virtual volume is to be relocated between a plurality of pools, a relocation control section predicts time periods till exhaustion of the pools before and after relocation based on information in the database and determines the relocation is possible or not based on the result of prediction or determines an appropriate relocation plan. This enables control of relocation of virtual volumes.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for detecting malicious system calls. In one aspect, a method includes monitoring a function vulnerable to a buffer overflow attack; receiving a call to the function, the call associated with a call stack, the call stack including one or more base pointers, and a destination buffer associated with the function; identifying a first critical memory address vulnerable to the buffer overflow attack comprising: determining the first critical memory address based on a base pointer of the one or more base pointers, wherein the base pointer address is greater than an address of the destination buffer; identifying a first address based on the base pointer of the one or more base pointers; and determining that the first address is a critical memory address in response to the first memory address is greater than the address of the destination buffer.

Abstract: An apparatus, system and method for increasing buffer status reporting efficiency and adapting buffer status reporting according to uplink capacity. User equipment is configured a monitor a usage of a plurality of buffers, detect one of a plurality of pre-selected conditions corresponding to at least one of the plurality of buffers, designate one of a plurality of buffer status reporting formats depending on the pre-selected condition detected, communicate a buffer status report to a network device in accordance with the buffer status reporting format designated. The buffer status reporting format is configured to minimize buffer status reporting overhead created by the communicating of the buffer status report.

Abstract: A method of processing a data stream through a buffer is performed in accordance with a write clock and a read clock. The buffer has a plurality of sequentially numbered storage cells. The method includes the steps of selecting an initial preload value, with the selecting step including determining a product of the maximum frequency offset between the write and read clocks, and a maximum time between arbitrary symbols in the data stream. The storage cells then receive data units in response to a write pointer. Data units are then provided from the storage cells in response to a read pointer.

Abstract: A method for maintaining flow control in a buffer memory coupled to a storage controller is provided. The storage controller includes, first and second counters that are used to monitor when data is read from a buffer memory and when data is transferred from the buffer memory to the host. The method includes, incrementing first and second counter values when data is placed in the buffer memory; decrementing a first counter value when data is read from the buffer memory; and decrementing the second counter value when data is sent to a host. The method further includes, pausing a first channel logic between a transport module and a storage disk when there is no data in the buffer memory; and pausing a second channel logic between a disk and the buffer if there is no space in the buffer memory.