Abstract: Systems, methods, and apparatus related to a memory system that manages an interface for a volatile memory device and a non-volatile memory device to control memory system power. In one approach, a controller evaluates a demand on memory performance. If the demand of a current computation task needed by the host is high, a DRAM device is powered-up to meet the demand. Otherwise, if the non-volatile memory device is adequate to meet the demand, the DRAM memory is partially or fully-powered down to save power. In another approach, a task performed for a host device uses one or more resources of a first memory device (e.g., DRAM). A performance capability of a second memory device (e.g., NVRAM) is determined. A controller of the memory system determines whether the performance capability of the second memory device is adequate to service the task.

Abstract: A method may include detecting, by a computing device based on a problem signature, that a system has experienced a problem that is associated with the problem signature, wherein the problem signature comprises a specification of a pattern of events indicative of the particular problem experienced by at least one other system; determining that the particular problem violates an operational policy of the system; and deploying, without user intervention, one or more corrective measures that modify the system to resolve the problem.

Abstract: A system and method that allows for information relating to data and communication resource usage to be gathered and analyzed such that particular data transactions and usage can be classified based on purpose and/or type. Further, the system and method provide reporting based on amount of usage and/or purpose or type of usage so that associated costs and usage can be calculated applied and allocated to particular accounts, divisions, groups or individuals within and outside of a company or entity. Further, the system may restrict data usage of devices to data usage that can be allocated to particular accounts based on purpose, source, destination or other.

Abstract: The invention introduces an apparatus for segmenting a data stream, installed in a physical layer, to include a host interface, a data register and a boundary detector. The data register is arranged to operably store data received from the host side through the host interface. The boundary detector is arranged to operably detect the content of a data register. When the data register includes a special symbol, the boundary detector outputs a starting address that the special symbol is stored in the data register to an offset register to update a value stored in the offset register, thereby enabling a stream splitter to divide data bits of the data register according to the updated value of the offset register.

Abstract: Embodiments of systems and methods for high-availability (HA) management networks for High Performance Computing (HPC) platforms are described. In some embodiments, an HPC platform may include a first Baseboard Management Controller (BMC) having a first network port; and a hardware accelerator comprising a second BMC having a second network port, where at least one of: (a) the first BMC is configured to share the first network port with the second BMC in response to a determination that the second network port has failed or has insufficient bandwidth, or (b) the second BMC is configured to share the second network port with the first BMC in response to a determination that the first network port has failed or has insufficient bandwidth.

Abstract: A memory is accessed based on memory access requests that has different data read sizes. A memory access method includes outputting each of read commands corresponding to the plurality of memory access requests to a memory at a timing that avoids conflict of read data output from the memory; generating an output start timing of the data read from the memory to an outside; retaining the data read from the memory in each of buffers, and causing any of the plurality of buffers to output data based on the output start timing; and delaying, in a case of receiving a subsequent memory access request during execution of memory access corresponding to a preceding memory access request, the output start timing of data from the buffer corresponding to the subsequent memory access request from the output start timing of data from the buffer corresponding to the preceding memory access request.

Abstract: A method that includes operating a bus monitoring system having at least one interface configured to be coupled to at least one communication bus and receive bus traffic transmitted over the communication bus(es). The method also includes, using a device authentication system of the bus monitoring system, analyzing the bus traffic received via the at least one interface. Analyzing the bus traffic includes obtaining a message in the bus traffic (where the message identifies a source), identifying a support vector machine that corresponds to the source of the message, applying a wave transform to a waveform of the received message in order to generate a transformed waveform, inputting the transformed waveform to the identified support vector machine, and taking action in response to the identified support vector machine determining that the transformed waveform or the associated information does not correspond to the source.

Abstract: A computing system initialization system includes a BIOS processing system coupled to a computing device via a first I/O access connection, to a BIOS memory system via a second I/O access connection that is a relatively higher speed I/O access connection than the first I/O connection, and to a BIOS module. The BIOS processing system retrieves device data from the computing device via the first I/O access connection, stores the device data in the BIOS memory system via the second I/O access connection, and performs initialization operations subsequent to storing the device data in the BIOS memory system. During the initialization operations, the BIOS processing determines that the BIOS module requires the device data and, in response, retrieves the device data from the BIOS memory system via the second I/O access connection, and provides the device data that was retrieved from the BIOS memory system to the BIOS module.

Abstract: In a modular memory system, a memory control component, first and second memory sockets and data buffer components are all mounted to the printed circuit board. The first and second memory sockets have electrical contacts to electrically engage counterpart electrical contacts of memory modules to be inserted therein, and each of the data buffer components includes a primary data interface electrically coupled to the memory control component, and first and second secondary data interfaces electrically coupled to subsets of the electrical contacts within the first and second memory sockets, respectively.

Abstract: Various surgical systems are disclosed. A surgical system can include a surgical robot and a surgical hub. The surgical robot can include a control unit in signal communication with a control console and a robotic tool. The surgical hub can include a display. The surgical hub can be in signal communication with the control unit. A facility can include a plurality of surgical hubs that communicate data from the surgical robots to a primary server. To alleviate bandwidth competition among the surgical hubs, the surgical hubs can include prioritization protocols for collecting, storing, and/or communicating data to the primary server.

Abstract: A display driver integrated circuit (IC) includes a logic module sequentially issuing read commands including a first read command, a second read command succeeding the first read command, and a third read command succeeding the second read command, and memory modules connected in series with each other. A first memory module is connected to the logic module and is the closest memory module to the logic module. The first memory module receives the read commands, provide the first read command to a first memory of the first memory module, read first image data from the first memory in response to the first read command, and provide the first image data and first remaining read commands among the read commands to a second memory module which is connected to the first memory module and farther than the first memory module from the logic module.

Abstract: Methods, systems, and devices for one or more clock domain crossing queues are described. A queue can receive, from a first clock domain, a first command to store data in the queue. The queue can store the data at a first location indicated by a first pointer. The queue can receive, from the first clock domain, a second command to cause the second clock domain to retrieve the data from the queue. The queue can generate, based on receiving the second command, a third command synchronized with a clock of the second clock domain and to cause the second clock domain to retrieve the data. The queue can retrieve the data from the first location in the queue indicated by a second pointer associated with retrieving data based at least in part on generating the third command. The queue can transmit, to the second clock domain, the data.

Abstract: Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.

Abstract: In one example, a method comprises: receiving, by a hardware data processor and from a network adapter, a transfer complete message indicating that the network adapter has initiated a transfer of data received from a network to the hardware data processor, the transfer being performed over an interconnect coupled between the hardware data processor and the network adapter; based on receiving the transfer complete message, performing, by the hardware data processor, a flush operation to fetch any remaining portion of the data buffered in the interconnect to a local memory of the hardware data processor; based on determining that flush operation is complete, storing, by the data hardware processor, the transfer complete message at the local memory; and based on determining that the transfer complete message is stored at the local memory, starting the computation operation of the data at the hardware data processor or preforming an error handling operation.

Abstract: A control unit that controls a transport apparatus executes selection control to select one accommodation portion as a selected accommodation portion, movement control to control the transport apparatus so as to move a transport support portion to a corresponding position, determination control to determine whether or not a detection target portion is detected by a detecting portion, transfer control to control the transport apparatus so as to transfer an article from the transport support portion to an accommodation support member, and update setting control to set the selected accommodation portion and related accommodation portions as prohibited accommodation portions if it is determined, in the determination control, that the detection target portion is not detected, and after the update setting control, the control unit again executes the selection control to newly select a selected accommodation portion, and executes the movement control so as to move the transport support portion to a corresponding pos

Abstract: To prevent a bank conflict in a memory with respect to an access address interval of a wide range. In a plurality of memory modules, an address is provided in a circulation manner for each word. A plurality of access ports is input/output ports for accessing the plurality of memory modules. A plurality of address converting sections converts the address to rearrange an arrangement of the words in the plurality of memory modules by a transposing process for a square matrix of a predetermined size. A connecting section connects the plurality of memory modules and the plurality of access ports in accordance with a result of the address conversion.

Abstract: An integrated circuit in a physical layer of a receiver is provided. The integrated circuit includes a multi-lane interface, a lane selection circuit and N sampling circuits. The multi-lane interface has N lanes. N is an integer greater than one. The lane selection circuit, coupled to the multi-lane interface, is configured to select M of the N lanes as M clock lanes, and output M signals on the M clock lanes respectively. M is a positive integer less than N. Remaining (N?M) lanes serve as (N?M) data lanes. The N sampling circuits are coupled to the multi-lane interface and the lane selection circuit. (N?M) of the N sampling circuits are coupled to the (N?M) data lanes respectively. Each of the (N?M) sampling circuits is configured to sample a signal on one of the (N?M) data lanes according to one of the M signals on the M clock lanes.

Abstract: An adaptable connector, a non-standard PCIe module, and a computer readable medium are disclosed. The adaptable connector for a PCIe interface allows for multiple standard PCIe modules and non-standard PCIe modules at different times An external I/O port has a set of non-PCIe I/O signal lanes coupled to the adaptable connector in lieu of a set of root port host PCIe signal lanes when a non-standard PCIe module is mated to the adaptable connector.

Abstract: Disclosed are systems, methods and computer readable mediums for optimized throughput of an object based storage system. The systems, methods and computer readable mediums including receiving an I/O request to the storage system, determining a busy ratio based on a number of blocks available in a local cache and a queue size, determining an I/O speed to the storage system, the I/O speed based at least in part on the busy ratio and an upload speed, wherein the I/O speed does not exceed a current speed of the storage system, and executing the I/O request to the storage system at the I/O speed.

Abstract: The present technique relates to a data processing apparatus, and a data processing method each of which enables a valid address to be more reliably produced in interleave. In a data processing apparatus, a frequency interleaver for carrying out frequency interleave calculates a first bit stream produced by a first pseudo random number generating portion configured to produce a random bit stream, a second bit stream produced by a second pseudo random number generating portion configured to produce a random bit stream, and an additional bit produced by a bit producing portion configured to alternately produce a bit as 0 and a bit as 1. As a result, in producing a write address or a read address including a random bit stream, the bit as 0 and the bit as 1 are alternately repeated as the most, significant bit in the random bit stream. The present technique, for example, can be applied to a frequency interleaver for carrying out frequency interleave.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. A memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A map structure associates logical addresses of user data blocks with physical addresses in the NVM at which the user data blocks are stored. A controller circuit arranges the user data blocks into map units (MUs), and directs the MME circuit to write the MUs to a selected page of the NVM. The controller circuit updates the map structure to list only a single occurrence of a physical address for all of the MUs written to the selected page. The map structure is further updated to list an MU offset and an MU length for each of the MUs written to the selected page.

Abstract: According to one embodiment, A data buffer is described. The data buffer comprises a first input/output circuit configured to receive and provide a first signal encoded according to a first communications protocol, a second input/output circuit configured to receive and provide a second signal encoded according to a second communications protocol, and a conversion circuit coupled to the first and second input/output circuits and configured to convert the first signal to the second signal and to convert the second signal to the first signal.

Abstract: The disclosure relates to bus interface systems. In one embodiment, the bus interface system includes a bus line along with a master bus controller and a slave bus controller coupled to the bus line. In order to start a data frame, the master bus controller is configured to generate a sequence of data pulses along the bus line such that the sequence of data pulses is provided in accordance to a start of sequence (SOS) pulse pattern. The slave bus controller is configured to recognize that the sequence of data transmitted along the bus line by the master bus controller has been provided in accordance with the SOS pulse pattern. In this manner, the slave bus controller can detect when the master bus controller has started a new data frame. As such, the exchange of information through data frames can be synchronized along the bus line with requiring an additional bus line for a clock signal.

Abstract: Embodiments of a bus interface system are disclosed. In one embodiment, the bus interface system includes a master bus controller and a slave bus controller coupled to a bus line. The master bus controller is configured to generate a first set of data pulses along the bus line representing a payload segment. The slave bus controller is configured to decode the first set of data pulses representing the payload segment into a decoded payload segment. The slave bus controller is then configured to perform a first error check on the decoded payload segment. Furthermore, the slave bus controller is configured to generate an acknowledgment signal along the bus line so that the acknowledgement signal indicates that the decoded payload segment passed the first error check. In this manner, the master bus controller can determine that the slave bus controller received an accurate copy of the payload segment.

Abstract: Embodiments of bus interface systems are disclosed. In one embodiment, a bus interface system includes a master bus controller and a slave bus controller coupled along a bus line. The master bus controller is configured to generate an input data signal that is received by the slave bus controller along the bus line. The slave bus controller includes power conversion circuitry configured to convert the input data signal from the master bus controller into a supply voltage. By providing the power conversion circuitry, the slave bus controller is powered using the input data signal and without requiring an additional bus line to transfer a supply voltage to the slave bus controller.

Abstract: A system for communication using a register management array circuit is disclosed, including a processor, including a processing core, the processing core including a local core register, a register management array circuit coupled to the local core register, and a remote circuit coupled to the register management array circuit, the remote circuit including a remote register. The register management array circuit includes circuitry to cause the data in the local core register to match the data in the remote register. Methods and circuits are also disclosed.

Abstract: A memory system for use in a system-in-package device (SiP) is disclosed. The memory system includes two cache memories. The first cache memory is on a first die of the SiP and the second cache memory is on a second die of the SiP. Both cache memories include tag random access memories (RAMs) corresponding to data stored in the corresponding cache memories. The second cache memory is of a different cache level from the first cache memories. Also, the first cache memory is on a first die of the SiP, and the second cache memory includes a first portion on the first die of the SiP, and a second portion on a second die of the SiP. Both cache memories can be checked concurrently for data availability by a single physical address.

Abstract: A system, methods, and apparatus for using hypervisor trapping for protection against interrupts in virtual machine functions are disclosed. A system includes memory, one or more physical processors, a virtual machine executing on the one or more physical processors, and a hypervisor executing on the one or more physical processors. The hypervisor reads an interrupt data structure on the virtual machine. The hypervisor determines whether the interrupt data structure points to an alternate page view. Responsive to determining that the interrupt data structure points to an alternate page view, the hypervisor disables a virtual machine function.

Abstract: An electronic apparatus that is capable of checking connection between the electronic apparatus body and accessories without performing communication between the electronic apparatus body and accessories. The electronic apparatus is capable of communicating with an accessory device connected. A detection unit detects whether the accessory device supports both a first communication method and a second communication method of which communication speed is higher than communication speed of the first communication method. A setting unit sets the second communication method during communication when the detection unit detects that the accessory device supports both the first communication method and the second communication method, and to set the first communication method except communicating.

Abstract: In one embodiment, a method includes measuring a first parameter associated with copying a storage entity to a first backup site, measuring a second parameter associated with copying the storage entity to a second backup site and determining a replication mode to copy the storage entity to the first backup site and a replication mode to copy the storage entity to the second backup site in response to a replication policy and the first and second parameters measured.

Abstract: A method for managing compute and I/O tasks in a data processing system includes: providing a thread pool including a plurality of thread groups, each thread group including one or more threads; providing a CPU pool including a plurality of CPU groups, each CPU group including one or more CPU cores; receiving a plurality of tasks comprising I/O tasks and compute tasks; mapping each of the plurality of tasks to at least one thread group in the thread pool; and mapping each of the plurality of thread groups in the thread pool to at least one CPU group in the CPU pool. The mappings between the plurality of tasks and the plurality of thread groups and between the plurality of thread groups and the plurality of CPU groups dynamically change based on performance variables.

Abstract: A host controller with suppressed data jitter is shown, which uses a logical physical layer (LPHY) to provide groups of low-speed data, uses a clock-domain-crossing transmitter (TXCDC) to transmit the groups of the low-speed data to the corresponding electrical physical layers (EPHYs), uses the EPHYs to convert the groups of the low-speed data to high-speed data and transmit the high-speed data to the corresponding external devices, and further has a multiplexer. Each EPHY corresponds to one clock signal and operates accordingly. The multiplexer receives the clock signals of the EPHYs to output a common clock signal for the LPHY to provide the groups of low-speed data and for the TXCDC to retrieve the groups of low-speed data. With respect to each of the external devices, the TXCDC uses the clock signal corresponding to the corresponding EPHY to output the corresponding group of low-speed data to the corresponding EPHY.

Abstract: Techniques for controlling PCIe direct attached non-volatile memory storage system are disclosed. In one particular embodiment, the techniques may be realized as a method including monitoring a temperature of a memory attached via the PCIe interface, determining whether an operation implemented on the attached memory has caused the temperature of the memory to exceed a preset threshold, and controlling an I/O rate of the attached memory based on the determination such that the I/O rate is greater than zero.

Abstract: A single high-speed bus accommodates both low-rate and high-rate bi-directional signal traffic by interleaving the traffic at the two rates sequentially so that all the data in the bus at any given time is either high-rate or low-rate. The interleaving is executed by a statistical aggregator according to a policy tailored to the traffic expected in the particular bus. The policy may be static and predetermined, or it may be dynamic and adaptive. Adaptive policies are continually updated with predictions of future traffic based on the statistics of past and/or present traffic. The technique may be implemented in both on-chip and system-level bus interfaces.

Abstract: A host device can download a firmware update to a peripheral device having previously enumerated with the host device. The host device can perform link training with the peripheral device in response to a re-enumeration indication received from the peripheral device. The link training can include switching a Link Training and Status State Machine (LTSSM) in the host device from an active state (U0) to an RX.Detect state and synchronizing with the peripheral device in the RX.Detect state. The host device can re-enumerate with the peripheral device utilizing the firmware update after the host device completes link training with the peripheral device.

Abstract: A host device can download a firmware update to a peripheral device having previously enumerated with the host device. The host device can perform link training with the peripheral device in response to a re-enumeration indication received from the peripheral device. The link training can include switching a Link Training and Status State Machine (LTSSM) in the host device from an active state (U0) to an RX.Detect state and synchronizing with the peripheral device in the RX.Detect state. The host device can re-enumerate with the peripheral device utilizing the firmware update after the host device completes link training with the peripheral device.

Abstract: The embodiments disclosed herein provide a computing device that includes an upstream buffer and downstream data processing circuit that establish a data processing path where the data stored by upstream buffer is received and processed by the downstream data processing circuit. Using a buffer utilization characteristic of the upstream buffer such as its current availability (e.g., the buffer is 50% full) or an input data rate, the computing device adjusts the clock signal used to drive the downstream data processing circuit. For example, if the utilization of the upstream buffer is low, the number of clock edges in the clock signal may be reduced thereby reducing power consumption of the computing device. However, as the utilization of the buffer begins to increase, the computing device may increase the number of clock edges to prevent a buffer overflow.

Abstract: A packet processing system having a control path memory of a control path subsystem and a datapath memory of a datapath subsystem. The datapath subsystem stores packet data of incoming packets and the control path subsystem performs matches of a subset of packet data, or a hash of the packet data, against the contents of a the control path memory in order to process the packets. The packet processing system enabling a portion of the datapath memory to be used by the control subsystem if needed or a portion of the control path memory to be used by the datapath subsystem if needed.

Abstract: A method, system and a computer program product. The method may include: allocating or receiving allocated bit rates to a plurality of streaming media flows, each streaming media flow comprises a plurality of chunks and is expected to flow over a last mile channel that is bandwidth limited; receiving a plurality of chunk requests from clients that are hosted on user devices, each chunk request indicates a requested bit rate for streaming a media chunk that belongs to the streaming media flow; changing at least one chunk request to comply with an allocated bit rate, if the requested bit rate does not comply with the allocated bit rate, to provide at least one new chunk request; and sending the at least one new chunk request to a media streamer that is expected to stream the streaming media flow to the user device.

Abstract: A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated from the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.

Abstract: A packet processing system having a control path memory of a control path subsystem and a datapath memory of a datapath subsystem. The datapath subsystem stores packet data of incoming packets and the control path subsystem performs matches of a subset of packet data, or a hash of the packet data, against the contents of a the control path memory in order to process the packets. The packet processing system enabling a portion of the datapath memory to be used by the control subsystem if needed or a portion of the control path memory to be used by the datapath subsystem if needed.

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

Abstract: A packet processing system having a control path memory of a control path subsystem and a datapath memory of a datapath subsystem. The datapath subsystem stores packet data of incoming packets and the control path subsystem performs matches of a subset of packet data, or a hash of the packet data, against the contents of a the control path memory in order to process the packets. The packet processing system enabling a portion of the datapath memory to be used by the control subsystem if needed or a portion of the control path memory to be used by the datapath subsystem if needed.

Abstract: A system for resolving write pressure includes a primary storage unit, a backup storage unit, and a processor. The primary storage unit comprises a primary storage unit input buffer and a volume storage unit. The backup storage unit comprises a backup storage unit input buffer and a volume backup storage unit. The processor is to: store a first set of input data in the backup storage unit input buffer in the event that the primary storage unit input buffer is unable to store the first set of input data and transfer the first set of input data to the primary storage unit input buffer as space is available after storing data from the primary storage unit input buffer in the volume storage unit.

Abstract: A method and apparatus of a device that manages a thermal profile of a device by selectively throttling input/output operations of the device is described. In an exemplary embodiment, the device monitors the thermal profile of the device, where the device executes a plurality of processes that utilize storage of the device. In addition, the plurality of processes include a high priority process and a low priority process. If the thermal profile of the device exceeds a thermal threshold, the device decreases a first bandwidth range for the low priority process and maintains a second bandwidth range for the high priority process. The device further processes a storage request of the low priority process using the first bandwidth range and processing a storage request of the high priority process using the second bandwidth range.

Abstract: A content reproducing method and system for performing seamless playback of contents between devices is provided. The contents reproducing system includes a portable device which, when a short distance communication with a remote control which is configured to control an electronic device occurs during reproducing of contents, generates data required by the electronic device for reproducing the contents that are being reproduced, and which transmits the generated data to the remote control; the remote control which receives the data from the portable device and which transmits the received data to the electronic device, in conjunction with the occurrence of the short distance communication with the portable device; and the electronic device for receiving the contents from a contents provider and reproducing the contents.

Abstract: In at least some embodiments, an electronic device includes a data sink and a buffer coupled to the data sink. The buffer is configured to receive streaming data in transit to the data sink. The electronic device also includes a clock drift compensation controller coupled to the buffer, wherein the clock drift compensation controller is configured to apply either of two predetermined clock drift compensation values to a clock rate for the buffer whenever a buffer fullness status value is offset from a predetermined threshold.

Abstract: A storage system manages a pool to which multiple VVOLs (virtual logical volumes conforming to thin provisioning) are associated, assigns a real area (RA) from any tier in an available tier pattern associated with a write-destination VVOL to a write-destination virtual area (VA), and carries out a reassignment process for migrating data inside this RA to an RA of a different tier than the tier having this RA based on the access status of the RA assigned to the VA. A management system assumes that a specified tier has been removed from the available tier pattern of a target VVOL, predicts the performance of the target VVOL and all the other VVOL associated with the pool to which the target VVOL is associated, determines whether or not there is a VVOL for which the predicted performance is lower than a required performance, and when such a VVOL does not exist, instructs the storage system to remove the specified tier from the available tier pattern of the target VVOL.

Abstract: A method in accordance with one embodiment of the invention may include receiving a first encryption key. A second encryption key may be generated, and a first data packet containing the second encryption key may be generated and at least part of the first data packet encrypted using the first encryption key. A second data packet may be generated and at least part of the second data packet encrypted using the second encryption key.

Abstract: According to one embodiment, the host controller includes a register set to issue command, and a direct memory access (DMA) unit and accesses a system memory and a device. First, second, third and fourth descriptors are stored in the system memory. The first descriptor includes a set of a plurality of pointers indicating a plurality of second descriptors. Each of the second descriptors comprises the third descriptor and fourth descriptor. The third descriptor includes a command number, etc. The fourth descriptor includes information indicating addresses and sizes of a plurality of data arranged in the system memory. The DMA unit sets, in the register set, the contents of the third descriptor forming the second descriptor, from the head of the first descriptor as a start point, and transfers data between the system memory and the host controller in accordance with the contents of the fourth descriptor.