Abstract: Systems and methods for providing spatial audio are disclosed herein. In one example, the method includes receiving a first position of a first playback device relative to a user in a listening environment; receiving a second position of a second playback device relative to the user in the listening environment; transmitting, to a media content provider, location data corresponding to the first and second positions; receiving, from the media content provider, virtual media audio content associated with a virtual environment, the virtual media audio content comprising first and second audio signals generated based on the transmitted location data, wherein the generated first and second audio signals include one or more audio cues configured to enable the user to spatially perceive a location of a virtual object within the listening environment; and playing back the first audio signal via the first playback device in synchrony with playing back the second audio signal via the second playback device.

Abstract: A peripheral device implements a plurality of queue sets each including a submission queue and a completion queue. Changes to the queues are monitored and arbitration parameters are adjusted, the arbitration parameters defining how submission queues are selected for retrieval of a command. An arbitration burst for a submission queue may be increased in response to tail movement for the submission queue being larger than for another submission queue. Priorities used for weighted round robin arbitration may also be adjusted based on tail movement. Arbitration burst quantities and priorities of groups of queues may also be adjusted. Head movement of the completion queues is monitored and may be used to lower priority, enable interrupt coalescing, or pause command retrieval where head movement does not meet a threshold condition.

Abstract: System and methods for selectively or automatically migrating resources between storage operation cells are provided. In accordance with one aspect of the invention, a management component within the storage operation system may monitor system operation and migrate components from storage operation cell to another to facilitate failover recovery, promote load balancing within the system and improve overall system performance as further described herein. Another aspect of the invention may involve performing certain predictive analyses on system operation to reveal trends and tendencies within the system. Such information may be used as the basis for potentially migrating components from one storage operation cell to another to improve system performance and reduce or eliminate resource exhaustion or congestion conditions.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

Abstract: The present technology includes a memory system and a method of operating the memory system. The memory system includes a memory device including an interface circuit, the interface circuit storing first system data, and a semiconductor memory; and a controller configured to output a read enable signal and a first read command for the first system data to the memory device. The semiconductor memory transfers a data strobe signal to the interface circuit in response to the read enable signal, the interface circuit reads the first system data in response to the first read command and transmits the read first system data to the controller in synchronization with the data strobe signal.

Abstract: A computer system identifies that a user activity on a user device during a first time period corresponds to a first user activity profile. The computer system monitors user activity on a user device during a second time period. The computer system determines that the user activity associated with the second time period does not correspond to the first user activity profile. In response to the determining that the user activity associated with the second time period corresponds to the second user activity profile, the computer system implements one or more security measures.

Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. For example, implicit classes may be used to generate clock crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.

Abstract: Systems and techniques for synchronizing transactions between processing devices on an interconnection network are provided. Upon receiving a stream of posted transactions followed by a flush transaction from a source processing device connected to the interconnection network, the flush transaction is trapped before it enters the interconnecting network. Subsequently, based on monitoring for responses received from a destination processing device for transactions corresponding to the posted transactions, a flush response is generated and returned to the source processing device. The described techniques enable efficient synchronizing posted writes, posted atomics and the like over complex interconnection fabrics such that a first GPU can write data to a second GPU so that a third GPU can safely consume the data written to the second GPU.

Abstract: A method for dynamically scheduling a data-processing workload includes recognizing minimum and maximum execution slice sizes and predicting an execution slice size for a current job of a collection of jobs. If the predicted execution slice size exceeds the maximum slice size or if the job involves date-dependent records in the future of the current date, the job is split into a working slice and a remainder slice, the remainder slice is added to the collection of jobs and the working slice is executed. Otherwise, if the predicted execution slice size is between the minimum and maximum execution slice sizes, the current job is executed.

Abstract: Management of a store queue based on a restoration operation. A determination is made as to whether a restoration operation to perform a bulk restore of a set of architected registers has completed. Based on determining that the restoration operation has completed, one or more store queue entries corresponding to the restoration operation are invalidated.

Abstract: Management of a store queue based on a restoration operation. A determination is made as to whether a restoration operation to perform a bulk restore of a set of architected registers has completed. Based on determining that the restoration operation has completed, one or more store queue entries corresponding to the restoration operation are invalidated.

Abstract: A peripheral interface circuit and method is disclosed for dealing with round trip delay with serial memory. In some implementations, a finite state machine is configured to introduce a delay state prior to a read data state to absorb round trip delay associated with a memory read operation. A clock module is coupled to the finite state machine and configured to delay start of a pad return clock for the read operation until completion of the delay state. A first synchronous logic is coupled to receive the pad return clock and is configured to sample and hold data from a data bus during the read data state of the memory read operation based on the pad return clock. A second synchronous logic is coupled to receive a system clock and is configured to sample the held data based on the system clock.

Abstract: This disclosure relates generally to digital bus interfaces. In one embodiment, a bus interface system includes a master bus controller and a slave bus controller coupled along a bus line. The master bus controller is configured to generate an input data signal that is received by the slave bus controller along the bus line. The slave bus controller includes power conversion circuitry that includes a power converter configured to convert the input data signal from the master bus controller into a supply voltage. The power conversion circuitry is also configured to generate a charge current from the input data signal. In this manner, the charge current can be used to regulate the supply voltage and maintain the appropriate charge.

Abstract: A computer program comprising a sequence of instructions for execution on a processing unit having instruction storage for holding the computer program, an execution unit for executing the computer program and data storage for holding data, the computer program comprising: a switch control instruction which when executed causes the processing unit to control switching circuitry to connect a set of connection wires of the processing unit to a switching fabric to receive a data packet at a predetermined received time, the switch control instruction comprising a delay control field which holds a value defining a delay between issuance of the instruction in the sequence of instructions and its execution by the execution unit.

Abstract: The embodiments relate to a computer system, computer program product and method for managing a garbage collection process. Processing control is obtained based on execution of a load instruction and a determination that an object pointer to be loaded indicates a location within a selected portion of memory undergoing a garbage collection process. The determination includes identifying a base address and size of a first memory block subject to the garbage collection, and assigning a binary value to each first memory block section. An image of the load instruction is obtained and a pointer address is calculated from the image. It is determined whether the object pointer is to be modified. The object pointer is modified and stored in a selected location.

Abstract: A method includes receiving a first progress request from a first state machine associated with execution of a first thread on a processor. The method includes updating a current state of a temporal relationship state machine based on the current state, the first progress request, and a predetermined temporal relationship between progress of the first state machine to a first state machine state and progress to a second state. The predetermined temporal relationship may require the first state machine to progress to the first state machine state before the progress to the second state. The current state of the temporal relationship state machine may be one of a first temporal relationship state and a second temporal relationship state. The second state may be a second state machine state of the first state machine. The second state may be a second state machine state of a second state machine.

Abstract: The use of a skip element when redoing transactions, so as to avoid tracking dependencies between transactions assigned to different threads for parallel processing. When the second thread comes to a second task in the course of redoing a second transaction, if a first task that is mooted by the second task is not already performed, the second thread inserts a skip element associated with the object to be operated upon by the particular task, instead of actually performing the particular task upon the object. When the first thread later comes to the first task in the course of redoing a first transaction, the first thread encounters the skip element associated with the object. Accordingly, instead of performing the dependee task, the first thread skips the dependee task and perhaps removes the skip element. The result is the same regardless of whether the first or second task is redone first.

Abstract: A method and a circuit for exciting a crystal oscillation circuit are disclosed herein. The crystal oscillation circuit comprising: charging, with a charging circuit, a voltage-controlled oscillator; providing, with the voltage-controlled oscillator, an exciting signal; blocking, with a direct current blocking capacitor, direct current from the voltage-controlled oscillator to the crystal oscillation circuit; and exciting, with the exciting signal, the crystal oscillation circuit. The circuit for exciting a crystal oscillation circuit, comprising: a charging circuit; a voltage-controlled oscillator coupled to the charging circuit and configured to provide an exciting signal to the crystal oscillation circuit; and a direct current blocking capacitor connected between the voltage-controlled oscillator and the crystal oscillation circuit and configured to block direct current from the voltage-controlled oscillator.

Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.

Abstract: A Local Timer Engine (LTE) is disclosed. For an initiator in a computing system, the LTE measures a respective time delay for each of a plurality of routes between the initiator and a plurality of destinations. For each of the plurality of routes, the LTE determines a respective timeout value based on the measured respective time delay for the route and determines a unique memory mapped address identifying the route. The initiator sends a request to the LTE for a timeout value. The LTE determines a proper timeout value and provides the proper timeout value to the initiator.

Abstract: This invention discloses a memory control circuit and a method thereof. The memory control method includes the steps of: transmitting a first clock to a serial peripheral interface (SPI) NOR flash memory; transmitting a read instruction to the SPI NOR flash memory; waiting for a read waiting time period, which is associated with a specification of the SPI NOR flash memory and a cycle of the first clock; waiting for a delay time period, which is associated with a delay setting value and a cycle of a second clock different from the first clock; receiving read data returned from the SPI NOR flash memory; and adjusting the delay time period according to whether the read data are correct or not. This invention improves the stability of read operation of the SPI NOR flash memory and has advantages of simple circuit and flexible adjustment.

Abstract: Techniques for low bit rate parametric encoding of haptic-tactile signals. The techniques encompass a parametric encoding method. The parametric encoding method includes the steps of: for at least one frame of a plurality of frames of a source haptic-tactile signal, representing the source haptic-tactile signal in the frame as a set of parameters and according to a functional representation; and including the set of parameters in a bit stream that encodes the source haptic-tactile signal. The functional representation is based on one of a set of orthogonal functionals, or polynomial approximation. For example, the functional representation can be based on one of Chebyshev functionals of the first kind through order n, Chebyshev functionals of the second kind through order n, or k-th order polynomial approximation.

Abstract: A system and method are disclosed that include a bridge that translates non-coherent transactions, which are received from a non-coherent subsystem, into one or more coherent transactions to be issued to a coherent subsystem. The bridge also buffers data coherently in an internal cache, also known as a proxy cache, based on certain attributes of the non-coherent transaction. The invention may be applied to any cache, which receives read and write transactions that become coherent transactions.

Abstract: System and methods for selectively or automatically migrating resources between storage operation cells are provided. In accordance with one aspect of the invention, a management component within the storage operation system may monitor system operation and migrate components from storage operation cell to another to facilitate failover recovery, promote load balancing within the system and improve overall system performance as further described herein. Another aspect of the invention may involve performing certain predictive analyses on system operation to reveal trends and tendencies within the system. Such information may be used as the basis for potentially migrating components from one storage operation cell to another to improve system performance and reduce or eliminate resource exhaustion or congestion conditions.

Abstract: A simulation environment is provided for running a process simulation used to validate an industrial control program. The simulation environment exposes the I/O module configurations defined in the control program and retrieves module configuration information therefrom. This I/O module configuration information is combined with generic, module-specific I/O module profiles to create a pool of available controller I/O points, which can be selectively associated with I/O points in the simulation to create an I/O point mapping. During control program validation, simulated I/O data is exchanged between the process simulation and the I/O module instances in the controller in accordance with the I/O point mapping. A variation of these techniques for use with cloud-based emulations is also described.

Abstract: A system can include a host device and a remote terminal. The host device can include a host terminal, the host terminal including a host configuration manager to allocate a data lane to an I/O protocol and a protocol multiplexer to carry out allocation of the data lane based on the allocation of the configuration manager. The remote terminal can include a remote configuration manager. The remote configuration manager is to communicate with the remote configuration manager via a control bus to detect connection of an I/O device to an I/O port and to allocate the data lane to the I/O protocol.

Abstract: A simulation environment for running a process simulation used to validate an industrial control program. The simulation environment exposes the I/O module configurations defined in the control program and retrieves module configuration information therefrom. This I/O module configuration information is combined with generic, module-specific I/O module profiles to create a pool of available controller I/O points, which can be selectively associated with I/O points in the simulation to create an I/O point mapping. During control program validation, simulated I/O data is exchanged between the process simulation and the I/O module instances in the controller in accordance with the I/O point mapping.

Abstract: System and methods for selectively or automatically migrating resources between storage operation cells are provided. In accordance with one aspect of the invention, a management component within the storage operation system may monitor system operation and migrate components from storage operation cell to another to facilitate failover recovery, promote load balancing within the system and improve overall system performance as further described herein. Another aspect of the invention may involve performing certain predictive analyzes on system operation to reveal trends and tendencies within the system. Such information may be used as the basis for potentially migrating components from one storage operation cell to another to improve system performance and reduce or eliminate resource exhaustion or congestion conditions.

Abstract: In one aspect, a method implemented by a first sync controller includes receiving sync information, wherein the sync information (i) identifies a first sync process, (ii) indicates that the first sync controller is not a master controller of the first sync process, and (iii) identifies a group of components executing the first sync process, the group comprising a first processing device; receiving a first sync indication from the first processing device; storing an indication, associated with the first sync process, that the first sync indication was received from the first processing device; determining that a sync indication has been received from all components of the first group of components; and transmitting a second sync indication to a second sync controller.

Abstract: A processor executes a plurality of tasks by switching a timeslot and iterating a plurality of timeslots. The processor includes a table in which tasks are defined in correspondence with timeslots. In the table, the number of timeslots to be held in one iteration is defined, for each of the timeslots a total time period during the predetermined number of iterations is designated, and a plurality of tasks are defined in correspondence with at least one of the timeslots. A timeslot is switched every time a predetermined period elapses. One task is selected and executed by referring to the table in correspondence with switching of timeslot.

Abstract: An example implementation may involve a computing system receiving a request from a first media playback system for access to a queue of media items, and a request from a second media playback system for access to the queue of media items. The computing system may grant a first type of access to the first media playback system and a second type of access to the second media playback system. The first type of access and the second type of access may authorize a first set of operations and a second set of operations on the queue of media items, respectively. The computing system may provide an indication that the first media playback system may access the queue as authorized by the first type of access, and an indication that the second media playback system may access the queue as authorized by the second type of access.

Abstract: A translation lookaside buffer (TLB) configured for use in a multiple operating system environment includes a plurality of storage locations, each storage location being configured to store a page translation entry configured to relate a virtual address range to a physical address range, each page translation entry having an address space identifier (ASID) associated with an operating system. The TLB also includes flush logic configured to receive a TLB flush request from an operating system having an operating system ASID and flush only TLB page translation entries having a stored ASID that matches the operating system ASID.

Abstract: System and methods for selectively or automatically migrating resources between storage operation cells are provided. In accordance with one aspect of the invention, a management component within the storage operation system may monitor system operation and migrate components from storage operation cell to another to facilitate failover recovery, promote load balancing within the system and improve overall system performance as further described herein. Another aspect of the invention may involve performing certain predictive analyzes on system operation to reveal trends and tendencies within the system. Such information may be used as the basis for potentially migrating components from one storage operation cell to another to improve system performance and reduce or eliminate resource exhaustion or congestion conditions.

Abstract: A method for reducing virtual machine preemption in a virtualized environment is provided. The method includes dispatching a virtual central processing unit (CPU) to run in an emulation mode on a real CPU until the real CPU exits the emulation mode, determining whether the virtual CPU has loaded a wait state, determining whether a remaining time slice of the virtual CPU as a result of the dispatching is below a predefined threshold in an event that the virtual CPU has loaded the wait state and rescheduling the virtual CPU with a full time slice in an event the remaining time slice of the virtual CPU is below the predefined threshold.

Abstract: In a memory system in which a system clock signal is forwarded from the memory controller to multiple memory devices, the phase of the system clock signal forwarded to the slower memory device is advanced relative to the system clock signal forwarded to the faster memory device by a phase corresponding to the skew on the data links corresponding to the memory devices. This causes the state machine of the slower memory device to change states and advance earlier than the state machine in the faster memory device, and as a result, the data read from both the slower memory device and the faster memory device are unskewed on the data links between the memory controller and the memory devices.

Abstract: A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.

Abstract: A building-facility information storage stores data sizes of process data to be collected from building-side communicating devices. A schedule generating unit generates a collection schedule of the process data from the building-side communicating devices so that, in a collection period including a plurality of unit periods continuous in terms of time, a first communication load representing a total data volume received from the building-side communicating devices per unit period and second communication loads each representing a data volume transmitted from each of the building-side communicating devices per unit period are balanced among the unit periods. A network communicating unit collects the process data from the building-side communicating devices in accordance with the collection schedule.

Abstract: A method of handling signaling congestion for a machine type communication (MTC) device and/or a MTC server in a wireless communication system is disclosed. The method comprises receiving system information from a network; and stopping a triggering operation in a communication window according to the system information, wherein the system information indicates occurrence of a signaling congestion situation in the network.

Abstract: In processing devices, in particular in measuring, test or control units for the drivetrain or components thereof, it is often necessary to combine signals or data of different synchronization sources with one another or to process them whilst maintaining the original temporal relation. In order to achieve this, the signals or data have hitherto often been synchronized to a specific clock source, but this is frequently not possible. Therefore, a method and a device are specified which enable the processing of data or signals with different synchronization sources in a processing device by virtue of the fact that a dedicated time level is introduced for each synchronization source in the processing device, the temporal reference of the associated data and signals being retained in the time levels. The signals and data are processed in the time levels with the temporal original reference being maintained.

Abstract: Selective enablement of operating modes or features of a storage system via host transfer rate detection enables, in some situations, enhanced performance. For example, a Solid-State Disk (SSD) having a serial interface compatible with a particular serial interface standard selectively enables coalescing of status information for return to a host based on detecting a particular host transfer rate capability. Some hosts are not fully compliant with the particular standard, being unable to properly process the coalesced status information. The selective enablement disables status coalescing for a non-compliant host and enables status coalescing for at least some compliant hosts, without the SSD having prior knowledge of coupling to a noncompliant/compliant host. The SSD conservatively determines the host is non-compliant/compliant based on a negotiated speed of the serial interface, and selectively disables/enables status coalescing in response to the negotiated speed.

Abstract: An Extended Input/output (I/O) measurement word facility is provided. Provision is made for emulation of the Extended I/O measurement word facility. The facility provides for storing measurement data associated with a single I/O operation in an extended measurement word associated with an I/O response block. In a further aspect, the stored data may have a resolution of approximately one-half microsecond.

Abstract: A method is described that involves detecting the presence of a pairing partner. Prior to establishing a paired relationship with the pairing partner, a user is prompted to verify himself/herself. In response to the user properly verifying himself/herself, the paring partner is paired with. The pairing includes invoking a remote storage protocol that contemplates a network between the partners to establish on a first of the partners access to non volatile storage resources for general use. The non volatile storage resources are located on a second of the partners. The second of the partners is a handheld device that provides wireless cell phone service, wireless Internet service and music playback service.

Abstract: A system and method for finding the sources of increased interrupt latencies. An interrupt controller includes monitoring logic for measuring and storing latencies for servicing interrupt requests. The interrupt controller determines a measured latency is greater than an associated threshold and in response sends an indication of a long latency. The interrupt controller may send the indication to firmware, a device driver, or other software. The interrupt controller stores associated information with the measured latency for debug purposes. Additionally, the monitoring logic may perform statistical analysis in place of, or in addition to, software.

Abstract: A system for enhancing universal serial bus (USB) applications comprises an upstream processor, a downstream processor and a main controller. The upstream processor accepts standard USB signals from a USB host and independently provides responses required by USB specification within the required time frame. The upstream processor also contains storage for descriptors for a device associated with this upstream processor. The main controller obtains the descriptors by commanding the downstream processor, and passes them to the upstream processor. The downstream processor connectable to USB-compliant devices accepts the USB signals from the USB-compliant devices and provides responses required by USB specification within the required time frame. The main controller interconnects the upstream and downstream processors, and provides timing independence between upstream and downstream timing. The main controller also commands the downstream processor to obtain device descriptors independent of the USB host.

Abstract: An electronic device executes a certain process when first data for instructing the electronic device to begin the certain process has been received from an external apparatus, and stops the certain process when the external apparatus has not been detected as a certain apparatus and when a first time has elapsed since the certain process was executed, even if second data for instructing the electronic device to stop the certain process has not been received.

Abstract: Some of the embodiments of the present disclosure provide a method comprising categorizing each data packet of a plurality of data packets into one of at least two priority groups of data packets; and controlling transmission of data packets of a first priority group of data packets during a first off-time period such that during the first off-time period, data packets of the first priority group of data packets are prevented from being transmitted to a switching module from one or more server blades. Other embodiments are also described and claimed.

Abstract: An I/O processing control apparatus integrates, from among a plurality of unprocessed I/O requests, two or more I/O requests, which are for the same type of I/O process and have two or more noncontiguous areas as I/O destinations, into one I/O request targeted at one continuous area comprising the above-mentioned two or more noncontiguous areas, and executes I/O processing in relation to the storage device on the basis of the integrated I/O request.

Abstract: According to one embodiment, a video sender comprises: a video processor and a communication module. The video processor creates video. The communication module is configured to communicate with a video receiver. The communication module comprises: a receiver and a transmitter. The receiver receives, from the video receiver, specific information specifying which one of a color signal and a frame rate takes precedence over the other one in transmission. The transmitter converts the video created by the video processor into video in which one of the color signal and the frame rate takes precedence over the other one in accordance with the specific information, and transmit the video thus converted to the video receiver.

Abstract: The defined architecture allows for format-efficient data storage on bit-patterned media, while allowing for typical variations in the drive, such as reader to writer gap variations. The defined BPM architecture relaxes some timing requirements on real-time signaling from the formatter to the channel, while enabling bit-accurate alignment between data accesses and the media.

Abstract: Disclosed herein is a data reception circuit including a clock generation block configured to divide a first clock based on clock information, the first clock being the clock of a transmission stream targeted to transmit video data between apparatuses, the clock information indicating a cyclical relationship between the first clock and a second clock serving as the clock of predetermined data, the clock generation block further outputting the divided clock as the second clock.