Hierarchical Memories Patents (Class 711/117)
- Multiple caches (Class 711/119)
- Instruction data cache (Class 711/125)
- User data cache (Class 711/126)
- Interleaved (Class 711/127)
- Associative (Class 711/128)
- Partitioned cache (Class 711/129)
- Shared cache (Class 711/130)
- Multiport cache (Class 711/131)
- Stack cache (Class 711/132)
- Entry replacement strategy (Class 711/133)
- Look-ahead (Class 711/137)
- Cache bypassing (Class 711/138)
- Cache pipelining (Class 711/140)
- Coherency (Class 711/141)
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Patent number: 9740565Abstract: A request is received to determine a consistent point of data stored in a file system of a storage system having storage units. In response to the request, a prime dependency list is retrieved from a first prime segment stored in a first storage unit, the prime dependency list including information identifying at least a second prime segment stored in a second storage unit. The first and second prime segments are identified by a first prime segment identifier (ID) and a second prime segment ID, respectively, which collectively identify a prime representing a first consistent view of the file system. The consistent point of data is determined based the prime segments listed in the prime dependency list, where the consistent point of data represents a file system state at a point in time for restoration of the file system back to a prior known state.Type: GrantFiled: July 10, 2015Date of Patent: August 22, 2017Assignee: EMC IP Holding Company LLCInventors: Soumyadeb Mitra, Windsor W. Hsu
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Patent number: 9728080Abstract: A personal digital key (e.g., which can be carried by a human) contains a memory having different service blocks. Each service block is accessible by a corresponding service block access key. As the personal digital key (PDK) moves around, it is detected by sensors. The sensors report position data, thus enabling location tracking of the PDK. The sensors also provide a data path to various applications. An application that has access to a service block access key can therefore access the corresponding service block on the PDK. The sensors themselves may also contain service block access keys.Type: GrantFiled: February 20, 2014Date of Patent: August 8, 2017Assignee: Proxense, LLCInventors: David L. Brown, John J. Giobbi
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Patent number: 9728270Abstract: A semiconductor device comprises a bit determination circuit to count the number of bits at a first level in an input address signal formed of a plurality of bits and to output a result indicating whether or not a value of the count exceeds a predetermined determination threshold value, as a bit determination result signal, and a selection control circuit to select a non-volatile program element to be cut off, based on the bit determination result signal and the address signal. Additional apparatus and methods are described.Type: GrantFiled: May 13, 2016Date of Patent: August 8, 2017Assignee: Micron Technology, Inc.Inventor: Susumu Takahashi
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Patent number: 9727263Abstract: A system and method for managing the storage of data in non-volatile memory is described. In an aspect, the data may be described by metadata and a transaction log file that are checkpointed from a volatile memory into the non-volatile memory. Actions that take place between the last checkpointing of a metadata segment and log file segment are discovered by scanning the non-volatile memory blocks, taking account of a record of the highest sector in each block that is known to have been recorded. Any later transactions are discovered and used to update the recovered metadata so that the metadata correctly represents the stored data.Type: GrantFiled: February 17, 2016Date of Patent: August 8, 2017Assignee: VIOLIN MEMORY, INC.Inventor: Jon C. R. Bennett
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Patent number: 9720739Abstract: Improving the performance of multitasking processors are provided. For example, a subset of M processors within a system with N processors is dedicated for a desired task. The M (where M>0) of the N processors are dedicate to a task, thus, leaving N?M (N minus M) processors for running normal operating system (OS). The processors dedicated to the task may have their interrupt mechanism disabled to avoid interrupt handler switching overhead. Therefore, these processors run in an independent context and can communicate with the normal OS and cooperation with the normal OS to achieve higher performance.Type: GrantFiled: December 28, 2015Date of Patent: August 1, 2017Assignee: Fortinet, Inc.Inventor: Jianzu Ding
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Patent number: 9720831Abstract: A method for maintaining the coherency of a store coalescing cache and a load cache is disclosed. As a part of the method, responsive to a write-back of an entry from a level one store coalescing cache to a level two cache, the entry is written into the level two cache and into the level one load cache. The writing of the entry into the level two cache and into the level one load cache is executed at the speed of access of the level two cache.Type: GrantFiled: October 23, 2015Date of Patent: August 1, 2017Assignee: INTEL CORPORATIONInventors: Karthikeyan Avudaiyappan, Mohammad Abdallah
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Patent number: 9716755Abstract: Locally providing cloud storage array services for a storage array of a data center when the storage array is not connected to a remote cloud-based storage array services provider includes initiating, by a primary storage array, one or more cloud storage array services and locally providing the cloud storage array services. Such local providing of the cloud storage array services also includes generating, by the cloud storage array services, metadata describing one or more real-time storage array characteristics and presenting the metadata to a user through a local area network.Type: GrantFiled: May 26, 2015Date of Patent: July 25, 2017Assignee: Pure Storage, Inc.Inventors: Benjamin P. Borowiec, Terence W. Noonan
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Patent number: 9703717Abstract: A computer system according to the present invention is composed of a server 200 having a flash memory drive 204 for cache, a storage system 260 having storage tiers composed of an SSD 267 and an HDD 268, and a management server having a page tier determination program 503 for determining the storage tier to which data is to be stored. The page tier determination program 503 migrates data having a high read access rate out of the pages having a high cache rate to the flash memory drive 204 to a storage tier of the HDD 268, and confirms so that data is not stored in a duplicated manner to the flash memory drive 204 and the SSD 267. Further, the data having a relatively high write access rate is migrated to the storage tier of the SSD 267 so as to prevent deterioration of write process performance.Type: GrantFiled: July 29, 2013Date of Patent: July 11, 2017Assignee: Hitachi, Ltd.Inventors: Shinichi Hayashi, Yusuke Funaya
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Patent number: 9678676Abstract: A solid state drive (SSD) includes an SSD control module configured to determine frequencies corresponding to how often data stored in respective logical addresses associated with the SSD is updated and form groups of the logical addresses according to the frequencies, and a memory control module configured to rewrite the data to physical addresses in blocks of an SSD storage region based on the groups.Type: GrantFiled: May 2, 2012Date of Patent: June 13, 2017Assignee: Marvell World Trade Ltd.Inventors: Lau Nguyen, Perry Neos, Luan Ton-That
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Patent number: 9632760Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for using tiered arrays to represent aggregated software dependencies. One of the methods includes receiving a request to generate a range of contiguous indexes having non-default values represented by a tiered array, wherein each non-default element of each tier is a reference to a catalog at a lower tier except for a bottom-most tier of the tiered array that stores non-default values. After descending one or more tiers to identify a first index that (i) is greater than or equal to the start index and (ii) has a non-default value, a system ascends one or more tiers in the tiered array and subsequently descends again to identify a second index that is a last index in a contiguous sequence of indexes having non-default values from the first index up to and including the second index.Type: GrantFiled: May 2, 2016Date of Patent: April 25, 2017Assignee: Semmle LimitedInventor: Joshua George Hale
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Patent number: 9620181Abstract: According to an example, a method for adaptive-granularity row buffer (AG-RB) caching may include determining whether to cache data to a RB cache, and adjusting, by a processor or a memory side logic, an amount of the data to cache to the RB cache for different memory accesses, such as dynamic random-access memory (DRAM) accesses. According to another example, an AG-RB cache apparatus may include a 3D stacked DRAM including a plurality of DRAM dies including one or more DRAM banks, and a logic die including a RB cache. The AG-RB cache apparatus may further include a processor die including a memory controller including a predictor module to determine whether to cache data to the RB cache, and to adjust an amount of the data to cache to the RB cache for different DRAM accesses.Type: GrantFiled: January 31, 2013Date of Patent: April 11, 2017Assignee: Hewlett Packard Enterprise Development LPInventors: Sheng Li, Norman Paul Jouppi, Naveen Muralimanohar
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Patent number: 9619750Abstract: An apparatus and method for store dependence prediction is described. For example, one embodiment of the invention includes a processor comprising a store buffer for buffering store operations prior to completion, the store operations to store data to a memory hierarchy; and a store dependence predictor to predict whether load operations should be permitted to speculatively skip over each store operation and responsively setting an indication within an entry associated with each store operation in the store buffer; wherein a load operation checks the indication in the store buffer to determine whether to speculatively execute ahead of each store operation.Type: GrantFiled: June 29, 2013Date of Patent: April 11, 2017Assignee: INTEL CORPORATIONInventors: Ho-Seop Kim, Robert S. Chappell, Choon Yip Soo
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Patent number: 9619338Abstract: A method and/or computer program product recovers files that are generated by an application running on a client-server system that comprises a back-up client with a client back-up tool and a server with a server back-up tool. Application files are backed up on the server, and then restored to a back-up client based on file usage behavior of the application and their priority, and file stubs are created for remaining files. File usage behavior of the application performing data recovery and regular data processing after said restore process are monitored and analyzed, and files in different types of priority classes are classified based on file usage behavior. Existing file stubs at the back-up client are replaced with corresponding file content from the back-up server during runtime of the application based on predetermined criteria.Type: GrantFiled: September 22, 2014Date of Patent: April 11, 2017Assignee: International Business Machines CorporationInventors: Felix Hamborg, Alexander Neef
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Patent number: 9619169Abstract: A method is used in managing data activity information for data migration in data storage systems. Slice activity data for slices stored in a data storage system is identified. The slice activity data is divided into multiple subsets of slice activity data. A subset of slice activity data may be obtained and stored in working memory. The slice activity data may be updated to correspond to changes slice activity. After a determined time, the updated slice activity data is copied to a disk drive and the method is repeated with the next subset of slice activity data.Type: GrantFiled: September 30, 2012Date of Patent: April 11, 2017Assignee: EMC IP Holding Company LLCInventors: Dean D. Throop, Dennis T. Duprey
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Patent number: 9619400Abstract: A computer-implemented method for managing memory operations includes reading a first memory page from a storage device responsive to a request for the first memory page. The first memory page is stored to a system memory. Based on a pre-established set of association rules, one or more associated memory pages are identified that are related to the first memory page. The associated memory pages are read from the storage device and compressed to generate corresponding compressed associated memory pages. The compressed associated memory pages are also stored to the system memory to enable memory access to the associated memory pages during processing of the first memory page. The compressed associated memory pages are individually decompressed in response to the particular page being required for use during processing.Type: GrantFiled: February 28, 2013Date of Patent: April 11, 2017Assignee: International Business Machines CorporationInventors: Saravanan Devendran, Kiran Grover
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Patent number: 9600417Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for caching data not frequently accessed. One of the methods includes receiving a request for data from a component of a device, determining that the data satisfies an infrequency condition, in response to determining that the data satisfies the infrequency condition: determining a target cache level which defines a cache level within a cache level hierarchy of a particular cache at which to store infrequently accessed data, the target cache level being lower than a highest cache level in the cache level hierarchy, requesting and receiving the data from a memory that is not a cache of the device, and storing the data in a level of the particular cache that is at or below the target cache level in the cache level hierarchy, and providing the data to the component.Type: GrantFiled: April 29, 2015Date of Patent: March 21, 2017Assignee: Google Inc.Inventors: Richard Yoo, Liqun Cheng, Benjamin C. Serebrin, Parthasarathy Ranganathan, Rama Krishna Govindaraju
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Patent number: 9594561Abstract: A method and apparatus for tracing instruction streams for a multi-threaded processor are disclosed herein. In one embodiment, the apparatus includes a last thread register configured to store a thread index that indicates a last executed thread, a tracing memory configured to store, within each of a plurality of storage locations, state information corresponding to a dispatch cycle for a multi-threaded processor, and a tracing control module configured to provide the state information to the tracing memory. The state information includes instruction information and a previous thread index. The state information may also include a flip bit that is used to determine a current insertion point within the tracing memory.Type: GrantFiled: December 29, 2015Date of Patent: March 14, 2017Assignee: International Business Machines CorporationInventors: Lee E. Eisen, Lisa C. Heller, Michael T. Huffer, Eric M. Schwarz
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Patent number: 9594595Abstract: A system and methods embodying some aspects of the present embodiments for efficient load balancing using predication flags are provided. The load balancing system includes a first processing unit, a second processing unit, and a shared queue. The first processing unit is in communication with a first queue. The second processing unit is in communication with a second queue. The first and second queues are each configured to hold a packet. The shared queue is configured to maintain a work assignment, wherein the work assignment is to be processed by either the first or second processing unit.Type: GrantFiled: May 17, 2013Date of Patent: March 14, 2017Assignee: Advanced Micro Devices, Inc.Inventors: Vinod Tipparaju, Lee W. Howes, Thomas Scogland
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Patent number: 9582210Abstract: Raw data is accessed from a storage device. A sample survey technique is used on the raw data to select a sample data. A data science technique is used on the sample data to determine a sample data category. The raw data is classified at least in part by considering the sample data category. A tier of storage is identified for the raw data on the storage device based on the classification.Type: GrantFiled: June 24, 2015Date of Patent: February 28, 2017Assignee: EMC IP Holding Company LLCInventor: Kenneth J. Taylor
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Patent number: 9582427Abstract: A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element.Type: GrantFiled: August 31, 2015Date of Patent: February 28, 2017Assignee: International Business Machines CorporationInventors: Philip Heidelberger, Hillery C. Hunter, James A. Kahle, Ravi Nair
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Patent number: 9569385Abstract: Embodiments are disclosed relating to methods of ordering transactions across a bus of a computing device. One embodiment of a method includes determining a current target memory channel for an incoming transaction request, and passing the incoming transaction request downstream if the current target memory channel matches an outstanding target memory channel indicated by a direction bit of a counter or the counter equals zero. The method further includes holding the incoming transaction request if the counter is greater than zero and the current target memory channel does not match the outstanding target memory channel.Type: GrantFiled: September 9, 2013Date of Patent: February 14, 2017Assignee: Nvidia CorporationInventors: Sagheer Ahmad, Dick Reohr
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Patent number: 9569517Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for handling faults in a distributed key-value storage system. One of the methods includes receiving an indication that a machine storing a primary replica of a first replication chain is inactive, in response to receiving the indication, generating a concatenated replica comprising a first replica of the first replication chain and a second replica of a second replication chain, the second replication chain comprising replicas of a second key segment, the second key segment being adjacent to the first key segment in the multiple key segments of the plurality of keys, and providing, to another machine in the ordered sequence of machines, a notification of availability of the concatenated replica.Type: GrantFiled: December 20, 2013Date of Patent: February 14, 2017Assignee: Google Inc.Inventors: Alexander Johannes Smola, Amr Ahmed, Eugene Jon Shekita, Bor-yiing Su, Mu Li
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Patent number: 9563359Abstract: A system is provided for transforming an in-use RAID array from a first array configuration having a first parameter to a second array configuration having a second parameter while preserving a logical data structure of the RAID array. The system includes an extent reservation component, and a data migration component for reading unmigrated data from an area of an array arranged according to the first array configuration and writing the data to an area of the array arranged according to the second array configuration using reserved extents to store migrated data. The system also includes a first I/O component for performing I/O according to the first array configuration on unmigrated data prior to its reading by the data migration component, and a second I/O component for performing I/O according to the second array configuration on the migrated data after writing the migrated data.Type: GrantFiled: October 19, 2015Date of Patent: February 7, 2017Assignee: International Business Machines CorporationInventors: Joanna K. Brown, Matthew J. Fairhurst, William J. Scales, Mark B. Thomas
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Patent number: 9557923Abstract: An apparatus for migrating data in a tiered storage architecture includes one or more processors and one or more memory devices coupled to the processors and storing instructions for execution by the processors. The instructions cause the one or more processors to: track temperature (i.e., frequency of access) of data blocks in a tiered storage architecture; generate heat maps indicating the temperature of the data blocks across different time intervals; process the heat maps using an image processing algorithm; compress the heat maps to reduce the size of the heat maps; compare the heat maps from the time intervals to identify temperature patterns occurring over time; predict, from the temperature patterns, when selected data blocks will change in temperature; and migrate the selected data blocks between tiers of the tiered storage architecture in anticipation of their changes in temperature.Type: GrantFiled: February 11, 2016Date of Patent: January 31, 2017Assignee: International Business Machines CorporationInventors: Thomas W. Bish, Gregory E. McBride, David C. Reed, Richard A. Welp
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Patent number: 9529544Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.Type: GrantFiled: January 26, 2016Date of Patent: December 27, 2016Assignee: Apple Inc.Inventors: James Wang, Zongjian Chen, James B. Keller, Timothy J. Millet
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Patent number: 9513920Abstract: A computer processor is operably coupled to a memory system. The memory system is configured to store instruction blocks, wherein each instruction block is associated with an entry address and multiple distinct instruction streams within the instruction block. The multiple distinct instruction streams include at least a first instruction stream and a second instruction stream. The first instruction stream has an instruction order that logically extends in a direction of increasing memory space relative to the entry address of the instruction block. The second instruction stream has an instruction order that logically extends in a direction of decreasing memory space relative to the entry address of the instruction block. The computer processor includes a number of multi-stage instruction processing components corresponding to the multiple distinct instruction streams within each instruction block.Type: GrantFiled: May 29, 2014Date of Patent: December 6, 2016Assignee: MILL COMPUTING, INC.Inventors: Roger Rawson Godard, Arthur David Kahlich, David Arthur Yost
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Patent number: 9489305Abstract: Various embodiments of methods and systems for managing write transaction volume from a master component to a long term memory component in a system on a chip (“SoC”) are disclosed. Because power consumption and bus bandwidth are unnecessarily consumed when ephemeral data is written back to long term memory (such as a double data rate “DDR” memory) from a closely coupled memory component (such as a low level cache “LLC” memory) of a data generating master component, embodiments of the solutions seek to identify write transactions that contain ephemeral data and prevent the ephemeral data from being written to DDR.Type: GrantFiled: December 16, 2014Date of Patent: November 8, 2016Assignee: QUALCOMM INCORPORATEDInventors: George Patsilaras, Bohuslav Rychlik, Andrew Edmund Turner, Kris Tiri, Jeong-Ho Woo, Anwar Rohillah, Feng Wang, Moinul Khan, Subbarao Palacharla
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Patent number: 9471437Abstract: Systems and methods are described for backing up files and directories using a common backup format. The files and directories may be represented by objects within a data stream constructed using the common backup format. The data streams may be traversed and updated using a size tree such that modifications are made to individual objects within the data streams without complete traversal. This process results in efficient management of storage systems as read and write operations are not dependent on exhaustive traversal of data streams.Type: GrantFiled: July 10, 2015Date of Patent: October 18, 2016Assignee: EMC CorporationInventors: Junxu Li, Windsor W. Hsu
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Patent number: 9459809Abstract: A technique is used for optimizing data location in data storage arrays. A primary storage array is associated with a secondary storage array, the primary storage array and secondary storage array including auto-tiering functionality, where the secondary storage array is configured as a backup storage array for the primary storage array. Tiering metadata is derived for a storage object stored on the primary storage array. The tiering metadata is transmitted to the secondary storage array. Auto-tiering is initiated at the secondary storage array, where the received tiering metadata is provided as input to the secondary storage array's auto-tiering function when auto-tiering replicated storage object associated with the tiering metadata.Type: GrantFiled: June 30, 2014Date of Patent: October 4, 2016Assignee: EMC CorporationInventors: Xiangping Chen, Miles A. de Forest, Dennis T. Duprey, Karl M. Owen, Jean-Pierre Bono, Walter A. O'Brien, III
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Patent number: 9454533Abstract: Systems and methods for reducing metadata in a write-anywhere storage system are disclosed herein. The system includes a plurality of clients coupled with a plurality of storage nodes, each storage node having a plurality of primary storage devices coupled thereto. A memory management unit including cache memory is included in the client. The memory management unit serves as a cache for data produced by the clients before the data is stored in the primary storage. The cache includes an extent cache, an extent index, a commit cache and a commit index. The movement of data and metadata is by an interval tree. Methods for reducing data in the interval tree increase data storage and data retrieval performance of the system.Type: GrantFiled: August 12, 2015Date of Patent: September 27, 2016Assignee: DataDirect Networks, Inc.Inventors: Jason M. Cope, Paul J. Nowoczynski, Pavan Kumar Kumar Uppu, Donald J. Molaro, Michael J. Piszczek, John G. Manning
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Patent number: 9418109Abstract: A method, article of manufacture, and apparatus for processing queries, comprising analyzing a query tree, determining at least one operator based on the query tree analysis, assigning a memory allocation for each of the at least one operator, and storing the assignment in a storage device. In some embodiments, a memory classification for each of the at least one operator is determined. In some embodiments, assigning a memory allocation for each of the at least one operator includes assigning a memory allocation based on the memory classification.Type: GrantFiled: March 18, 2011Date of Patent: August 16, 2016Assignee: EMC CorporationInventors: Sivaramakrishnan Narayanan, Florian Michael Waas, Joy Jie Kent
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Patent number: 9396131Abstract: A system for dynamically utilizing data storage comprises a processor and a memory. The processor is configured to determine whether a data storage criterion is satisfied; and, in the event that the data storage criterion is satisfied: determine a new archiving threshold based on a target data storage usage level; and set the archiving threshold. The memory is coupled to the processor and is configured to provide the processor with instructions.Type: GrantFiled: February 8, 2013Date of Patent: July 19, 2016Assignee: Workday, Inc.Inventors: Peter George Hendry, Jonathan David Ruggiero
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Patent number: 9335944Abstract: Methods and apparatus related to in-place change between transient and persistent state for data structures on non-volatile memory are described. In one embodiment, controller logic causes a change in a state of a first portion of one or more non-volatile memory devices between a persistent state and a transient state and without moving data stored in the first portion of the one or more non-volatile memory devices. Other embodiments are also disclosed and claimed.Type: GrantFiled: July 31, 2015Date of Patent: May 10, 2016Assignee: Intel CorporationInventors: Matthias Gries, Marcelo Cintra, Thomas Lehnig, Sebastian Steibl, Tor Lund-Larsen
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Patent number: 9336102Abstract: In accordance with embodiments of the present disclosure, a method may include receiving from a plurality of data nodes of a distributed file system an indication of whether a fault condition exists with respect to a storage resource of the respective data node. The method may also include receiving an input/output request for a storage resource of a particular data node from a host information handling system communicatively coupled to the distributed file system. The method may further include, responsive to the input/output request, directing the input/output request to the particular data node if no fault condition exists with respect to storage resources of the particular data node and directing the input/output request to another data node of the distributed file system if a fault condition exists with respect to one or more storage resources of the particular data node.Type: GrantFiled: April 21, 2014Date of Patent: May 10, 2016Assignee: Dell Products L.P.Inventor: Xin Chen
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Patent number: 9304998Abstract: The present invention extends to methods, systems, and computer program products for main-memory database checkpointing. Embodiments of the invention use a transaction log as an interface between online threads and a checkpoint subsystem. Using the transaction log as an interface reduces synchronization overhead between threads and the checkpoint subsystem. Transactions can be assigned to files and storage space can be reserved in a lock free manner to reduce overhead of checkpointing online transactions. Meta-data independent data files and delta files can be collapsed and merged to reduce storage overhead. Checkpoints can be updated incrementally such that changes made since the last checkpoint (and not all data) are flushed to disk. Checkpoint I/O is sequential, helping ensure higher performance of physical I/O layers. During recovery checkpoint files can be loaded into memory in parallel for multiple devices.Type: GrantFiled: December 19, 2012Date of Patent: April 5, 2016Assignee: Microsoft Technology Licensing, LLCInventors: Cristian C. Diaconu, Ryan L. Stonecipher, Michael James Zwilling, Marcel Van Der Holst
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Patent number: 9292434Abstract: A method and apparatus configured to restore a flash translation layer (“FTL”) in a non-volatile (“NV”) storage device are disclosed. After reactivating the NV storage device from an unintended system crash, a process of recovering FTL, in one embodiment, receives a request for restoring at least a portion of the FTL or FTL database. After identifying sequence numbers (“SNs”) associated with flash memory blocks (“FMBs”) which are generated during write cycle(s), the SNs are retrieved from the information storage locations such as state information in the FMBs. A portion of the FTL database is subsequently reconstructed in a random access memory (“RAM”) according to the SNs. In an alternative embodiment, logical block addresses (“LBAs”), LBA lists, and/or index tables can also be used to restore the FTL database or table.Type: GrantFiled: August 22, 2014Date of Patent: March 22, 2016Assignee: CNEXLabs, Inc.Inventor: Yiren Ronnie Huang
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Patent number: 9288109Abstract: Embodiments of the present invention relate to methods and apparatuses for enabling cluster scaling. Specifically, there is disclosed a method of recording a context of configuration for an initial node of a cluster, comprising: retrieving at least one file to be used for configuring the initial node; and recording a context while configuring the initial node using the at least one file, the recorded context being information on the configuration of the initial node and to be used for enabling addition of a new node into the cluster. There is also disclosed a method of enabling addition of a new node into a cluster. Corresponding apparatuses are also disclosed. According to embodiments of the present invention, the efficiency of improving cluster scaling may be effectively improved.Type: GrantFiled: September 12, 2012Date of Patent: March 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Li Rong Jian, Jie Qiu, Jie Y. Yang, Tao Yu, Xiao Zhong
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Patent number: 9274953Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.Type: GrantFiled: February 2, 2015Date of Patent: March 1, 2016Assignee: Apple Inc.Inventors: James Wang, Zongjian Chen, James B. Keller, Timothy J. Millet
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Patent number: 9274942Abstract: According to one embodiment, a memory system includes a nonvolatile storage device and an information processing apparatus. The information processing apparatus includes a first control circuit configured to send a delete notification to the nonvolatile storage device to invalidate data in a first logical address area when read data corresponding to the first logical address area is the same as data expressed by a first function. The nonvolatile storage device include a nonvolatile storage medium, a management table configured to associate a logical address corresponding to valid data for the nonvolatile storage device with a physical address, and a second control circuit configured to update the management table to invalidate a logical address designated by the delete notification, and to send the data expressed by the first function to the information processing apparatus when a logical address included in a read instruction received from the information processing apparatus is invalid.Type: GrantFiled: September 18, 2011Date of Patent: March 1, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Daisuke Hashimoto
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Patent number: 9264309Abstract: Embodiments of the present invention relate to methods and apparatuses for enabling cluster scaling. Specifically, there is disclosed a method of recording a context of configuration for an initial node of a cluster, comprising: retrieving at least one file to be used for configuring the initial node; and recording a context while configuring the initial node using the at least one file, the recorded context being information on the configuration of the initial node and to be used for enabling addition of a new node into the cluster. There is also disclosed a method of enabling addition of a new node into a cluster. Corresponding apparatuses are also disclosed. According to embodiments of the present invention, the efficiency of improving cluster scaling may be effectively improved.Type: GrantFiled: July 17, 2012Date of Patent: February 16, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Li Rong Jian, Jie Qiu, Jie Y. Yang, Tao Yu, Xiao Zhong
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Patent number: 9256541Abstract: An apparatus for prefetching data for a processor is presented. The apparatus may include a memory, a first counter, a second counter, and a control circuit. The memory may include a table with at least one entry in which the at least one entry may include an expected address of a next memory access and a next address from which to fetch data, wherein the next address is an offset value different from the expected address. The at least one entry may also include a maximum limit for the offset value. The first counter may increment responsive to an address of a memory access matching the expected address. The second counter may increment responsive to the address of the memory access resulting in a cache miss. The control circuitry may be configured to increment the maximum value of the offset value dependent upon a value of the second counter.Type: GrantFiled: June 4, 2014Date of Patent: February 9, 2016Assignee: Oracle International CorporationInventors: Vijay Sathish, Yuan Chou
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Patent number: 9258364Abstract: A storage management method for use in a storage area network is provided. The storage area network comprises a plurality of host data processors coupled to a virtualization engine, which is coupled to a plurality of physical storage media. Each physical storage media is assigned a tier level. The method comprises storing a threshold storage access value associated with each tier level, presenting virtual disk(s) to a host data processor and receiving I/O requests to the virtual disk from the host data processor. Additionally, metadata is stored which identifies the tier level of the physical storage to which the block corresponds, mappings between the block and blocks of a virtual disk, and an access rate to the data. The access value is periodically compared to at least one threshold rate associated with its tier level. Depending on the result, storage block(s) may be marked for migration to another tier level.Type: GrantFiled: May 2, 2011Date of Patent: February 9, 2016Assignee: International Business Machines CorporationInventors: David John Carr, Barry Douglas Whyte
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Patent number: 9229993Abstract: In one embodiment, the present invention includes a computer-implemented method comprising monitoring a first condition of an in-memory database. An in-memory data store stores an in-memory database. The method further comprises determining whether the first condition of the in-memory database meets a first defined criterion. If the first condition of the in-memory database meets the first defined criterion, the in-memory database is stored in a persistent data store as a storage based database. If a received query is a query of the storage based database, the query is executed using the storage based database. Metadata of the in-memory database is mapped into a metadata repository if the in-memory database is stored in the in-memory data store. Metadata of the in-memory database is remapped in the metadata repository if the in-memory database is stored in the persistent data store as the storage based database.Type: GrantFiled: December 19, 2012Date of Patent: January 5, 2016Assignee: SAP SEInventors: Jens Odenheimer, Markus Boehm
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Patent number: 9209968Abstract: Speed-up of a cryptographic process by software (program) is realized. A data processing unit which executes a data process according to a program defining a cryptographic process sequence is included, and the data processing unit, according to the program, generates a bit slice expression data based on a plurality of plain text data items which are encryption process targets and a bit slice expression key based on a cryptographic key of each plain text data item, generates a round key based on the bit slice expression key, executes the cryptographic process including operation and movement processes of a block unit of the bit slice expression data, and an operation using the round key, and generates the plurality of encrypted data items corresponding to the plurality of plain text data items by the reverse conversion of the data with respect to the cryptographic process results.Type: GrantFiled: February 7, 2013Date of Patent: December 8, 2015Assignee: Sony CorporationInventors: Seiichi Matsuda, Shiho Moriai
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Patent number: 9164692Abstract: System and methods for storing electronic data is provided, where the system comprises a storage manager component and a management module associated with the storage manager component. The management module is configured to receive information related to storage activities associated with one or more storage operation components within the storage operation system under the direction of the storage manager component. The management module is adapted to predict storage operation resource allocations based on the received information related to the storage activities.Type: GrantFiled: May 5, 2014Date of Patent: October 20, 2015Assignee: Commvault Systems, Inc.Inventor: Srinivas Kavuri
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Patent number: 9158460Abstract: Provided are a method and a server for selecting data nodes for storing an object and replicas thereof in a cloud storage system having a plurality of data nodes grouped in a plurality of storage areas. The method may include selecting at least one storage area for storing the object and the replicas thereof sequentially with a locality policy, a low-cost policy, a load-balancing policy, and a space-balancing policy and selecting at least one data node from the selected at least one storage area sequentially using a load-balancing policy and a space-balancing policy.Type: GrantFiled: April 25, 2012Date of Patent: October 13, 2015Assignee: KT CORPORATIONInventors: Chang-Sik Park, Eo-Hyung Lee, Jin-Kyung Hwang
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Patent number: 9158461Abstract: A combination of a host system and data storage system that enables accurate performance testing of the storage subsystem is disclosed. In one embodiment, a driver of a host system receives a command message from a host system application. The command message enables the driver to generate and communicate one or more storage access commands to the data storage system. The driver then receives one or more execution results from the data storage system and determines and communicates the total execution time of the one or more storage access commands to the host system application. When the host system application determines performance of the data storage system the undesirable impact of the communication overhead between the host system application and the driver is minimized. Accordingly, accurate performance measurements of data storage systems are obtained.Type: GrantFiled: January 18, 2012Date of Patent: October 13, 2015Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventor: Brian K. Lee
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Patent number: 9141288Abstract: Systems, computer readable media, and methods are provided. An example method can include classifying a plurality of storage mapping systems as a plurality of storage tiers in a datacenter, assigning a chargeback level to each of the plurality of storage tiers, analyzing a plurality of storage volumes of a plurality of servers in the datacenter to obtain characteristics of each of the plurality of storage volumes where the characteristics include one of the plurality of storage mapping systems, assigning the chargeback level to each of the plurality of storage volumes based on the storage mapping system for each of the plurality of storage volumes, and determining a storage recommendation for a number of configuration item (CIs) based on a criticality of the number of CIs where the criticality corresponds to at least one of the chargeback levels assigned to each of the plurality of storage tiers.Type: GrantFiled: July 26, 2012Date of Patent: September 22, 2015Assignee: Hewlett-Packard Development Company, L.P.Inventors: Sagi Vasavi, Rajashekar Dasari
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Patent number: 9128824Abstract: Methods and apparatus related to in-place change between transient and persistent state for data structures on non-volatile memory are described. In one embodiment, controller logic causes a change in a state of a first portion of one or more non-volatile memory devices between a persistent state and a transient state and without moving data stored in the first portion of the one or more non-volatile memory devices. Other embodiments are also disclosed and claimed.Type: GrantFiled: December 24, 2012Date of Patent: September 8, 2015Assignee: Intel CorporationInventors: Matthias Gries, Marcelo Cintra, Thomas Lehnig, Sebastian Steibl, Tor Lund-Larsen
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Patent number: 9110702Abstract: Techniques for migrating a virtual machine from a source computer system to a target computer system are disclosed. In an exemplary embodiment, a group of pages can be mapped writable in response to determining that the guest operating system attempted to change a specific page. In the same, or other embodiments, pages can be compressed prior to sending such that throughput of a communication channel is maximized. In the same, or other embodiments, storage IO jobs can be canceled on a source computer system and reissued by a target computer system.Type: GrantFiled: June 2, 2010Date of Patent: August 18, 2015Assignee: Microsoft Technology Licensing, LLCInventors: Lars Reuther, Dustin L. Green, John A. Starks