Storage Accessing And Control Patents (Class 711/100)
  • Patent number: 11968267
    Abstract: A virtualization server may include a memory and a processor cooperating therewith to operate a virtual session controller configured to assign virtual sessions to a plurality of different client devices. Each virtual session may be running on a virtual machine from among a plurality of different virtual machines and having a respective user profile associated therewith stored at a cloud computing service, and the cloud computing service may be distributed over a plurality of different geographic locations and configured to store the user profiles and backups thereof at different geographic locations. The controller may further receive the user profiles from the cloud computing service and, as client devices are assigned virtual sessions on different virtual machines, roam the user profiles to the different virtual machines, and synchronize local profile changes during the virtual sessions on different virtual machines back to the user profiles stored at the cloud computing service.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: April 23, 2024
    Assignee: Citrix Systems, Inc.
    Inventors: Leo C Singleton, IV, Avijit Gahtori
  • Patent number: 11967396
    Abstract: A multi-rank system includes multiple circuit ranks communicating over a common data line to multiple data receivers, each corresponding to one or more of the ranks and each having a corresponding reference voltage generator and clock timing adjustment circuit, such that a rank to communicate on the shared data line is switched without reconfiguring outputs of either the reference voltage generators or the clock timing adjustment circuits.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: April 23, 2024
    Assignee: NVIDIA CORP.
    Inventors: Wen-Hung Lo, Michael Ivan Halfen, Abhishek Dhir, Jaewon Lee
  • Patent number: 11966632
    Abstract: Methods, systems, and devices are described to indicate, in an entry of logical to physical (L2P) mapping information stored at a host system, whether data associated with the entry is sequential to other data associated with a next entry or a previous entry. Each entry may have a third field, which may indicate whether the data is sequential. Based on the third field, the host system may determine whether data to be read from a memory system is sequential. The host system may transmit one read command to the memory system if the data is sequential, where the read command may include at least a portion of an L2P entry associated with the data. Similarly, based on the third field, the memory system may determine whether the data to be read is sequential, and may read additional, sequential data if the memory system determines that the data is sequential.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: April 23, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Roberto Izzi, Nicola Colella, Luca Porzio, Marco Onorato
  • Patent number: 11960933
    Abstract: A method includes receiving, by a producer thread of a plurality of producer threads, an offer request associated with an item. The producer thread increases a sequence and determines (i) a chunk identifier of a memory chunk from a pool of memory chunks and (ii) a first slot position in the memory chunk to offer the item. The producer thread also writes the item into the memory chunk at the first slot position. Then, a first consumer thread of a plurality of consumer threads determines the first slot position of the item and consumes the item at the first slot position. A second consumer thread consumes another item at a second slot position in the memory chunk and recycles the memory chunk.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: April 16, 2024
    Assignee: RED HAT, INC.
    Inventor: Francesco Nigro
  • Patent number: 11960744
    Abstract: A semiconductor device includes a memory partition. The semiconductor device further includes a plurality of registers. A first register of the plurality of registers, when in operation, controls an operation associated with the memory partition. The semiconductor device additionally includes a memory controller. When in operation, the memory controller accesses a first location of the memory partition concurrently with accessing the first register.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: April 16, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Hari Giduturi
  • Patent number: 11960411
    Abstract: A memory system may include: a nonvolatile memory device; and a controller suitable for generating first map information which maps physical addresses of the nonvolatile memory device to logical addresses received from a host, selecting some segments of the first map information as second map information, and outputting the second map information to the host, the controller may determine whether the second map information is updated, and may determine updated map segments as third map information, and the controller may output information to the host indicating the third map information corresponding to a command received from the host.
    Type: Grant
    Filed: May 8, 2023
    Date of Patent: April 16, 2024
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Patent number: 11960767
    Abstract: A method includes receiving, by a data storage device, a read command. The method further includes reading a first set of outer code stored to a magnetic recording medium of the data storage device and storing the first set of outer code to memory. The method further includes receiving a write command to write data to the magnetic recording medium and writing a second set of outer code to the magnetic recording medium in connection with the write command.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: April 16, 2024
    Assignee: Seagate Technology LLC
    Inventors: Ryan P. McCallister, Ara Patapoutian, Mark A. Gaertner, Ian Davies
  • Patent number: 11948009
    Abstract: A method and a device for operating instance resources are provided. The method includes receiving an operation request, acquiring an instance resource associated with the target resource according to an instance arranging property, executing the operation on the instance resource associated with the target resource, and transmitting an operation response. The operation request includes a type of an operation and a target resource.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: April 2, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Junjie Zhao
  • Patent number: 11947688
    Abstract: A computer system with multiple security levels, the system comprising a high-power processing device (130), a low-power processing device (110), and an interface unit (120) comprising functions for moving classified information between the high-power device (130) and the low-power device (110) according to formal rules for confidentiality and/or integrity. Additional security aspects, e.g. availability, may readily be accommodated. A method for implementing multiple levels of security along a number of independent security axes on the system is also disclosed.
    Type: Grant
    Filed: March 7, 2023
    Date of Patent: April 2, 2024
    Assignee: CUPP Computing AS
    Inventor: Omar Nathaniel Ely
  • Patent number: 11938897
    Abstract: An on-vehicle device is mounted on a vehicle, and includes: a processing unit; a determination unit configured to determine whether or not the vehicle is in a predetermined stop state; and a secure area that is accessible from the processing unit when the processing unit has output predetermined information. The secure area has, stored therein, control information that allows an external device to control the on-vehicle device. When the determination unit has made a positive determination, the processing unit accesses the secure area and performs an acquisition process of acquiring the control information from the secure area.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: March 26, 2024
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD.
    Inventors: Akihiro Ogawa, Hirofumi Urayama, Takeshi Hagihara, Yasuhiro Yabuuchi
  • Patent number: 11930112
    Abstract: Multi-path end-to-end encryption in a storage system, includes: receiving, by a storage system through a first path, a first write request for first data to be stored in a dataset, where the first data is encrypted with a first encryption key associated with requests received from the first path; decrypting the first data utilizing the first encryption key; encrypting the first data using a storage system encryption key; storing the first data in the dataset; receiving, by the storage system through a second path, a second write request for second data to be stored in the dataset, where the second data is encrypted with a second encryption key associated with requests received from the second path; decrypting the second data utilizing the second encryption key; encrypting the second data using the storage system encryption key; and storing the second data in the dataset.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: March 12, 2024
    Assignee: PURE STORAGE, INC.
    Inventors: Ronald Karr, Constantine Sapuntzakis, John Colgrove
  • Patent number: 11922033
    Abstract: A method for distributed file deletion or truncation, performed by a storage system, is provided. The method includes determining, by an authority owning an inode of a file, which authorities own data portions to be deleted, responsive to a request for the file deletion or truncation. The method includes recording, by the authority owning the inode, the file deletion or truncation in a first memory, and deleting, in background by the authorities that own the data portions to be deleted, the data portions in one of a first memory or a second memory. A system and computer readable media are also provided.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: March 5, 2024
    Assignee: PURE STORAGE, INC.
    Inventors: Robert Lee, Igor Ostrovsky, Shuyi Shao, Peter Vajgel
  • Patent number: 11914881
    Abstract: A data migration method and an apparatus are provided. The method is as follows: sending, by a first storage system, a location update request to a location server, where the location update request is used to indicate the location server to update location information of a first bucket from being located in a second storage system to being located in the first storage system; migrating data in a first bucket from the second storage system; receiving a data access request, where the data access request is used to access the data in the first bucket; and determining based on a type of the data access request and a migration status of the data, that the first storage system or the second storage system processes the data access request.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: February 27, 2024
    Assignee: Huawei Cloud Computing Technologies Co., Ltd.
    Inventors: Feng Xu, Yu Zhang, Ling Lin, Chen Ling, Lei Huang
  • Patent number: 11916891
    Abstract: The techniques herein are directed generally to a “zero-knowledge” data management network. Users are able to share verifiable proof of data and/or identity information, and businesses are able to request, consume, and act on the data—all without a data storage server or those businesses ever seeing or having access to the raw sensitive information (where server-stored data is viewable only by the intended recipients, which may even be selected after storage). In one embodiment, source data is encrypted with a source encryption key (e.g., source public key), with a rekeying key being an encrypting combination of a source decryption key (e.g., source private key) and a recipient's public key. Without being able to decrypt the data, the storage server can use the rekeying key to re-encrypt the source data with the recipient's public key, to then be decrypted only by the corresponding recipient using its private key, accordingly.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: February 27, 2024
    Assignee: JOURNEY.AI
    Inventors: Brett Shockley, Alexander John Shockley, Michael Joseph Frendo, Shmuel Shaffer, Kenneth Keiter, James M. Behmke
  • Patent number: 11907260
    Abstract: Compare processing using replication log-injected compare records includes receiving compare records from a source system having a source datastore in a replication relationship with a target datastore of a target system, the compare records corresponding to selected source objects of the source datastore, and the compare records being received in compare transaction(s) to be performed by the target system for determining whether data of the target datastore is consistent with the selected source objects, and commencing compare processing to perform the compare transaction(s), the compare processing including processing a compare record of the received compare records, which includes identifying a selected source object identified by the compare record, attempting to locate and read a corresponding target object of the target datastore, and further processing the compare record based on whether the corresponding target object is located and read by the attempting.
    Type: Grant
    Filed: April 19, 2020
    Date of Patent: February 20, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gregg Andrew Upton, Austin Willoughby, Shinji Satoh
  • Patent number: 11899590
    Abstract: A data storage system can employ a read destructive memory configured to fill a first cache with a first data set from a data repository prior to populating a second cache with a second data set describing the first data set with the first and second cache each having non-volatile ferroelectric memory cells. An entirety of the first cache may be read in response to a cache hit in the second cache with the cache hit responsive to a data read command from a host and with the first cache being read without a refresh operation restoring the data of the first cache.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: February 13, 2024
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Jon D. Trantham, Praveen Viraraghavan, John W. Dykes, Ian J. Gilbert, Sangita Shreedharan Kalarickal, Matthew J. Totin, Mohamad El-Batal, Darshana H. Mehta
  • Patent number: 11891776
    Abstract: When an automatic operation is finished, a detection process for detecting a ground contactable range where a work implement can be set is carried out on a basis of terrain profile information acquired by laser scanners, and, when the ground contactable range is detected, an automatic operation command signal for placing the work implement in contact with the ground contactable range is generated, whereas when the ground contactable range is not detected, an automatic operation command signal for placing the work implement in a predetermined standby posture is generated. As a result, a suitable standby posture can be taken according to the surrounding conditions when the automatic operation is finished.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: February 6, 2024
    Assignee: Hitachi Construction Machinery Co., Ltd.
    Inventors: Hiroyuki Yamada, Yoshiyuki Tsuchie, Shiho Izumi
  • Patent number: 11886279
    Abstract: Information corresponding to a health of a memory device or a functional state of the memory device, or both, is written to the memory device. Radio frequency (RF) signaling is used to provide power to certain components of the memory device. Information corresponding to the health of the memory device or the functional state of the memory device, or both, is retrieved from the memory device over-the-air in response to the RF signaling.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: January 30, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Shawn Storm
  • Patent number: 11876864
    Abstract: The condition of SFP transceivers of RDF port pairs is monitored and used to project port pair data transmission rate degradation. Responsive to receipt of a command to migrate data from a source volume to a target volume, ability of port pairs to accommodate the additional load associated with data migration is calculated based on projected data transmission rate and normal load. Only port pairs that are capable of accommodating the additional load in view of the condition of the SFP transceivers are considered as candidates. Utilization of the source volume is monitored and the target volume is created with a size based on projected growth of utilization of the source volume.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: January 16, 2024
    Assignee: Dell Products L.P.
    Inventors: Peniel Charles, Manikandan Sethuraman, Owen Crowley
  • Patent number: 11853807
    Abstract: Generally described, one or more aspects of the present application relate to scaling a cluster of compute capacity used to execute containerized applications or tasks. For example, a waiting area can be maintained, in which tasks that are requested to be executed in a cluster but are not able to be accommodated in the cluster due to the cluster not having sufficient compute capacity usable to execute such tasks are stored. The scaling of the cluster can be performed based on the characteristics of the tasks in the waiting area, such that the cost associated with adding too much compute capacity to the cluster can be reduced, while also reducing the time it takes to reach the desired level of compute capacity that can accommodate all of the requested tasks.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: December 26, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Nicholas Ashton Coult, David Michael Westbrook, Anoop Kapoor
  • Patent number: 11847050
    Abstract: According to one embodiment, a nonvolatile memory includes a memory chip and a command processing unit. The command processing unit stores data read from a first position of the memory chip in a memory when a first command for compaction is received from a controller, transmits validity determination information used for determining whether or not the data read from the first position is valid to the controller, and writes valid data of the data stored in the memory to a second position of the memory chip when a second command for the compaction and validity identification information that identifies the valid data are received from the controller.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: December 19, 2023
    Assignee: Kioxia Corporation
    Inventors: Daisuke Iwai, Toshio Fujisawa, Keigo Hara
  • Patent number: 11836118
    Abstract: An illustrative apparatus is configured to carry out the steps of: comparing one or more performance metrics of a particular storage array in a plurality of storage arrays to one or more corresponding performance metrics of one or more other storage arrays; identifying, based on the comparing, one or more actions for improving one or more conditions of the particular storage array; and presenting one or more projected effects of implementing the one or more actions on the storage array.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: December 5, 2023
    Assignee: Pure Storage, Inc.
    Inventors: Benjamin Borowiec, Terence Noonan
  • Patent number: 11818886
    Abstract: A method of manufacturing a low program voltage flash memory cell with an embedded heater in the control gate creates, on a common device substrate, a conventional flash memory cell in a conventional flash memory area (CFMA), and a neuromorphic computing memory cell in a neuromorphic computing memory area (NCMA). The method comprises providing a flash memory stack in both the CFMA and the NCMA, depositing a heater on top of the flash memory stack in the NCMA without depositing a heater on top of the flash memory stack in the CFMA.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: November 14, 2023
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Nanbo Gong, Bahman Hekmatshoartabari, Alexander Reznicek
  • Patent number: 11816346
    Abstract: A data migration orchestration system includes a data migration orchestration engine, a user interface, and an orchestration configuration database. The user interface provides a menu-based system configured to guide a user through a process of implementing a data migration instance. The orchestration configuration database contains information about the types of data migration technologies available to be used to implement data migration operations between disparate storage systems.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: November 14, 2023
    Assignee: Dell Products, L.P.
    Inventors: Vijesh Shetty, Sivashankari Chandrasekaran
  • Patent number: 11789749
    Abstract: An automatic application configurator method.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: October 17, 2023
    Assignee: SCORPION SECURITY PRODUCTS, INC.
    Inventors: Franklyn W. Gulick, Jr., Grant William Gulick, Benjamin Farmer
  • Patent number: 11782895
    Abstract: A hashing apparatus includes a memory and circuitry. The memory stores (i) multiple hash tables storing associative entries, each including at least one entry key and a respective value, the hash tables are associated with respective different hash functions, and an associative entry is accessible by applying the relevant hash function to a key matching an entry key in the associative entry, and (ii) an affinity table that stores table-selectors for selecting hash tables with which to start a key lookup. The circuitry receives a key, reads from the affinity table, by applying an affinity function to the key, a table-selector that selects a hash table, accesses in the selected hash table an associative entry by applying the hash function associated with the selected hash table to the key, and in response to detecting that the key matches an entry key in the associative entry, outputs the respective value.
    Type: Grant
    Filed: September 7, 2020
    Date of Patent: October 10, 2023
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Aviad Levy, Gil Levy, Pedro Reviriego, Salvatore Pontarelli
  • Patent number: 11769388
    Abstract: A pre-disaster education system may include a system controller including a device processor and a non-transitory computer readable medium including instructions executable by the device processor to perform the following steps: receiving location data from a personal electronic device of a user; receiving forecast data regarding a predicted disaster; receiving data from one or more third parties, wherein the one or more third parties includes a shelter organization and the data from the one or more third parties includes vacancy information from the shelter organization; making a determination of an educational message to be sent to the personal electronic device of the user, based on the location data, the forecast data, and the vacancy information from the shelter organization; and sending the educational message to the personal electronic device of the user at a predetermined time relative to the predicted time of occurrence of the predicted disaster.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: September 26, 2023
    Assignee: United Services Automobile Association (USAA)
    Inventors: Meredith Beveridge, Michael J. Maciolek, Robert Wiseman Simpson, Daniel Christopher Bitsis, Jr., Bobby Lawrence Mohs, Manfred Amann, Emily Margaret Gray, Donnette Moncrief Brown
  • Patent number: 11770449
    Abstract: InfiniBand transport protocol today supports RDMA operations such as read and write with each operation having an opcode defined in the InfiniBand standard. Currently, new RDMA operations require extending the transport protocol by defining a new opcode, its respective header and enhancing InfiniBand implementations to support this new behavior. A more robust way of extending RDMA without requiring an expanding set of opcodes is to register computer code by associating it with a code key similar to a memory key. An InfiniBand channel adapter receiving an RDMA request that includes a code key executes the associated computer code, perhaps compiling it first, in response to receiving the RDMA request. The RDMA response returned to the requester includes an execution result indicating an outcome of executing the executable computer code.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: September 26, 2023
    Assignee: PENSANDO SYSTEMS INC.
    Inventors: Murty Subba Rama Chandra Kotha, Balakrishnan Raman, Harinadh Nagulapalli, Vishwas Danivas, Sanjay Shanbhogue, Raja Rao Tadimeti, Madhava Rao Cheethirala
  • Patent number: 11768613
    Abstract: A solid state drive having a drive aggregator configured to interface with a host system, and a plurality of component solid state drives connected to the drive aggregator. Each of the component solid state drives has a controller capable of processing commands from host systems. The drive aggregator is configured to receive commands from the host system and transmit commands to the component solid state drives to implement the commands received from the host system.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: September 26, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Poorna Kale, Christopher Joseph Bueb, Taufique Murad Ahmed, Sven Lehsten
  • Patent number: 11762568
    Abstract: A method for controlling a redundant storage system is proposed. A write request to a redundant storage system is received (310). A dataset that is to be written into the redundant storage system by the write request is determined (320). A portion of the dataset is logged into the redundant storage system for data recovery in case that a fault occurs in the redundant storage system (330). Thus, only a portion of the dataset is logged and the amount of the logged data may be reduced compared with the conventional redundant storage system. Further, the redundant storage system may be recovered in response to a fault occurring in the redundant storage system.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: September 19, 2023
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Jinglei Ren, Thomas Moscibroda
  • Patent number: 11762798
    Abstract: A solid state drive having a drive aggregator configured with multiple host interfaces for parallel and/or redundant connections to one or more host systems. The solid state drive has a plurality of component solid state drives connected to the drive aggregator. Each of the component solid state drives has a controller capable of processing commands from host systems. The drive aggregator is configured to receive commands in the host interfaces concurrently and implement the commands received from the host system using the plurality of component solid state drives.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: September 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Poorna Kale, Christopher Joseph Bueb
  • Patent number: 11762786
    Abstract: A memory device including memory cells operating according to a first clock signal having a first clock frequency and accessed based on a data access time. The memory device may include a clock shifter circuit for delaying the access commands based on the data access time. The clock shifter circuitry include a shift register circuit and a phase correction circuit. The shift register circuit delays the access commands using a second clock signal having a fraction of the first clock frequency. The phase correction circuit receives the access commands from the shift register circuitry using the fraction of the first clock frequency, delays the access commands based on phase information of the access commands, and outputs the access commands to the memory cells based on the data access time using the first clock frequency.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: September 19, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Vijayakrishna J. Vankayala
  • Patent number: 11755232
    Abstract: An example method includes transferring, for each of a plurality of snapshots of a source virtual storage volume mounted at a first compute node, at least a portion of a plurality of data blocks for each of the snapshots to a target virtual storage volume at a second compute node; and after the data blocks are transferred, resynchronizing the target virtual storage volume with the source virtual storage volume.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: September 12, 2023
    Assignee: Pure Storage, Inc.
    Inventor: Ganesh Sangle
  • Patent number: 11755235
    Abstract: Systems and methods include storing one or more counters in a plurality of locations in Double Data Rate (DDR) Random Access Memory (RAM) such that each counter is stored partially in multiple locations across the DDR RAM; and accessing banks in the DDR RAM sequentially for read operations and write operations associated with the one or more counters. The multiple locations include a location in each bank of the banks in the DDR RAM. A read operation for a counter is performed by reading all of the corresponding multiple locations and combining associated values to return a result for the counter. A write operation for a counter is performed by writing to a location of the multiple locations that is currently in sequence.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: September 12, 2023
    Assignee: Ciena Corporation
    Inventor: Kenneth Edward Neudorf
  • Patent number: 11748000
    Abstract: To selectively use cost, performance, reliability, and security characteristics of storage devices in an appropriate manner. A storage system has a plurality of volumes of which reliability and security levels differ from one another, and a controller of the storage system determines a reliability requirement and a security requirement of a file based on at least one of a type and a content of the file, determines a volume to store the file based on the determination result, and stores the file in the determined volume.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: September 5, 2023
    Assignee: HITACHI, LTD.
    Inventors: Koki Omura, Yuta Nishihara, Arata Hayashi
  • Patent number: 11748256
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory including plural blocks each including plural pages, and a controller. When receiving a write request designating a first logical address and a first block number from the host, the controller determines a first location in a first block having the first block number to which data from the host should be written, and writes the data from the host to the first location in the first block. The controller notifies the host of either an in-block physical address indicative of the first location, or a group of the first logical address, the first block number and the first in-block physical address.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: September 5, 2023
    Assignee: Kioxia Corporation
    Inventors: Hideki Yoshida, Shinichi Kanno
  • Patent number: 11747991
    Abstract: The present disclosure provides a method for data storage, a general service entity device, and a storage medium. The method for data storage includes: by adopting a general service entity, receiving data sent by an application entity; performing a lock setting or an overflow setting; selecting a retention strategy for previously stored data according to the lock setting or the overflow setting in the case of satisfying a data overflow condition; and storing part or all of received data according to the retention strategy.
    Type: Grant
    Filed: November 28, 2019
    Date of Patent: September 5, 2023
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Qian Zhang, Junjie Zhao, Jing Su, Yanqiu Zhao
  • Patent number: 11748180
    Abstract: The present disclosure is directed to seamless access to a common physical disk in an AMP system without an external hypervisor, and includes one or more processors and one or more computer-readable non-transitory storage media comprising instructions that, when executed by the one or more processors, cause one or more components of the system to perform operations including instantiating, by a first instance, a second instance during a system upgrade, creating, in the first instance, a first disk abstraction for a block device of a physical disk, and attaching the block device under the first disk abstraction. The operations further include providing the second instance network-based access to the physical disk using the first disk abstraction of the first instance during the system upgrade.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: September 5, 2023
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Nivin Lawrence, Sandesh K. Rao, Manikandan Veerachamy, Amit Chandra, Tushar Sinha, Manoj Kumar, David W. Duffey
  • Patent number: 11720353
    Abstract: The present disclosure provides a processing device and method. The device includes: an input/output module, a controller module, a computing module, and a storage module. The input/output module is configured to store and transmit input and output data; the controller module is configured to decode a computation instruction into a control signal to control other modules to perform operation; the computing module is configured to perform four arithmetic operation, logical operation, shift operation, and complement operation on data; and the storage module is configured to temporarily store instructions and data. The present disclosure can execute a composite scalar instruction accurately and efficiently.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: August 8, 2023
    Assignee: SHANGHAI CAMBRICON INFORMATION TECHNOLOGY CO., LTD
    Inventors: Shaoli Liu, Yuzhe Luo, Qi Guo, Tianshi Chen
  • Patent number: 11714579
    Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: August 1, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seonkyoo Lee, Jeongdon Ihm, Chiweon Yoon, Byunghoon Jeong
  • Patent number: 11704057
    Abstract: A write request comprising a logical address, a payload, and an indicator reflecting the character of the payload is received from an application. Based on the indicator, a value of a parameter associated with storing the payload on one or more of a plurality of memory devices is identified. The value of the parameter is determined to satisfy a criterion associated with a particular memory device of the plurality of memory devices. The payload is stored on the particular memory device.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: July 18, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Luca Bert
  • Patent number: 11687144
    Abstract: A new approach contemplates systems and methods to support control of power consumption of a memory on a chip by throttling port access requests to the memory via a memory arbiter based on a one or more programmable parameters. The memory arbiter is configured to restrict the number of ports being used to access the memory at the same time to be less than the available ports of the memory, thereby enabling adaptive power control of the chip. Two port throttling schemes are enabled—strict port throttling, which throttles the number of ports granted for memory access to be no more than a user-configured maximum throttle port number, and leaky bucket port throttling, which throttles the number of ports granted for the memory access down to be within a range based on a number of credit tokens maintained in a credit register.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: June 27, 2023
    Assignee: Marvell Asia Pte Ltd
    Inventors: Heeloo Chung, Sowmya Hotha, Saurabh Shrivastava, Chia-Hsin Chen
  • Patent number: 11656589
    Abstract: Various embodiments of the present technology generally relate to power topology discovery in industrial environments. More specifically, some embodiments relate to automatic power topology discovery for factories based on device data that is already recorded for other purposes. Systems and methods described herein may be used to generate an accurate electrical network topology by collecting power data from power devices that may provide real-time or recorded measurements, detecting power change events, and matching power change signatures over power events for the devices in order to calculate the likelihoods of possible topology assumptions. Power change event data is used to recursively update topology probabilities using the Bayesian formula until a system topology can be produced with satisfactory confidence.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: May 23, 2023
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Xiaolong Zhang, Benfeng Tang, Linglai Li, David B. Berman, Phillip R. Bush, Steven T. Haensgen, Michael L. Gasperi, Sean C. Schmelzer, Alex Nicoll
  • Patent number: 11645103
    Abstract: A method for securing the movement of virtual machines (VMs) between hosts. The method includes obtaining a first VM movement request; in response to obtaining the first VM movement request, identifying a first VM of the VMs and a first targeted host of the hosts associated with the first VM movement request using VM metadata and host metadata; making a first determination that the first targeted host is registered; in response to making the first determination, initiating the movement of the first VM to the first targeted host; and initiating, after the movement of the first VM, encryption of communication between the first VM and the first targeted host.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: May 9, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Suren Kumar, Vinod Durairaj, Veena Rao
  • Patent number: 11641276
    Abstract: The present disclosure generally relates to effective key management by properly matching keys used for encryption to data that needs to be decrypted after receiving instructions to change or delete keys. By matching the actual key, rather than just a key index, to a command, each command will use the correct key throughout the entire life-span of the command, even if the key is switched or deleted prior to servicing the command. To implement the key management, a snapshot of the doorbell database is taken. All pending commands that are in the snapshot are then fetched prior to updating a key database with either the change or deletion of the key. After fetching of all pending commands from the snapshot and ensuring the keys are stored in a command context, the key database is updated.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: May 2, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shay Benisty, Amir Segev
  • Patent number: 11599650
    Abstract: A computer system with multiple security levels, the system comprising a high-power processing device (130), a low-power processing device (110), and an interface unit (120) comprising functions for moving classified information between the high-power device (130) and the low-power device (110) according to formal rules for confidentiality and/or integrity. Additional security aspects, e.g. availability, may readily be accommodated. A method for implementing multiple levels of security along a number of independent security axes on the system is also disclosed.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: March 7, 2023
    Assignee: CUPP Computing AS
    Inventor: Omar Nathaniel Ely
  • Patent number: 11587641
    Abstract: A fuse fault repair circuit includes a fuse array, a signal storage module, and a scan repair module. The fuse array includes a redundant fuse array and a non-redundant fuse array. When the fuse array is not faulty, the redundant fuse array has no signal output, and the non-redundant fuse array outputs S first logic signals. Each storage unit in the signal storage module is configured to store a first logic signal sent by one fuse unit connected thereto. The scan repair module is configured to scan the storage units in the signal storage module, determine, when a faulty storage unit is scanned, that a first fuse unit connected to the faulty storage unit is faulty, and replace the first fuse unit with a first redundant fuse unit corresponding to the first fuse unit. The first logic signal corresponding to the first redundant fuse unit is a normal signal.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: February 21, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Kejun Wang
  • Patent number: 11586536
    Abstract: Technologies are described herein for remotely configuring multi-mode dual in-line memory modules (“multi-mode DIMMs”) using a firmware or a baseboard management controller (“BMC”). Technologies are also described for simultaneously initiating multiple commands for configuring multi-mode DIMMs using a BMC and for updating inventory data regarding multi-mode DIMMs stored by a BMC.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: February 21, 2023
    Assignee: AMERICAN MEGATRENDS INTERNATIONAL, LLC
    Inventors: Manish Jha, Harikrishna Doppalapudi, Manickavasakam Karpagavinayagam, Igor Kulchytskyy, Gopinath Sekaran, Altaf Hussain, Manikandan Palaniappan, Shirley Heby Hubert
  • Patent number: 11579777
    Abstract: In a method disclosed for writing data, a device receives data, divides the data into one or more data fragments, obtains a first parity fragment based on the one or more data fragments and a second parity fragment of a written data fragment in a stripe distributed across a plurality of nodes, stores the one or more data fragments and the first parity fragment in the stripe.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: February 14, 2023
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Siwei Luo, Lei Zhang, Feng Wang, Xin Fang
  • Patent number: 11579974
    Abstract: A system and method for offset protection data in a RAID array. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array is configured to store user data in a first page of a first storage device of the plurality of storage devices; generate intra-device protection data corresponding to the user data, and store the intra-device protection data at a first offset within the first page. The controller is further configured to generate inter-device protection data corresponding to the first page, and store the inter-device protection data at a second offset within a second page in a second storage device of the plurality of storage devices, wherein the first offset is different from the second offset.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: February 14, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: John Colgrove, John Hayes, Bo Hong, Ethan Miller