Abstract: Methods and apparatus are disclosed for using a shared page miss handler device to satisfy page miss requests of a plurality of devices in a multi-core system. One embodiment of such a method comprises receiving one or more page miss requests from one or more respective requesting devices of the plurality of devices in the multi-core system, and arbitrating to identify a first page miss requests of the one or more requesting devices A page table walk is performed to generate a physical address responsive to the first page miss request. Then the physical address is sent to the corresponding requesting device, or a fault is signaled to an operating system for the corresponding requesting device responsive to the first page miss request.

Abstract: A data processing system and methods for performing cache eviction are disclosed. An exemplary method includes maintaining a metadata set for each cache unit of a cache device comprising a plurality of cache units, each cache unit having a plurality of segments. In response to determining that a cache eviction is to be performed, a cache unit is evicted based on its metadata set. The exemplary method includes selecting one or more segments of the evicted cache unit to copy to a second cache unit based on the metadata set of the evicted cache unit, copying the selected one or more segments to the second cache unit, and writing the second cache unit to a storage device. The metadata set may include deletion hints (DH) to indicate valid segments, last access time (LAT) or age based metadata, an access count, or a score for each segment based on the metadata set.

Abstract: Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first non-volatile memory with first data from a first data lane that includes a first volatile memory device, and filling a second plurality of pages of the first non-volatile memory device with second data from a second data lane that includes a second volatile memory device. In certain examples, the first plurality of pages does not include data from the second data lane.

Abstract: A data processing system and methods for performing cache eviction are disclosed. An exemplary method includes maintaining a metadata set for each cache unit of a cache device at a sub-cache unit granularity, wherein the cache device comprises a plurality of cache units, each cache unit having a plurality of segments, wherein the cache device is accessible by a cache client at a segment granularity. The exemplary method further includes in response to determining that a cache eviction is to be performed, selecting a predetermined number of cache units from the plurality of cache units, determining a score for each of the selected cache units based on the respective metadata set maintained at the sub-cache unit granularity, and evicting one or more of the selected predetermined number of cache units based on their scores. The metadata may include, for example, last access time (LAT) metadata, an access count, and hotness metadata, and metadata may be maintained at a segment or a segment group granularity.

Abstract: In accordance with some embodiments, compaction, as contrasted with compression, is used to reduce the footprint of a near memory. In compaction, the density of data storage within a storage device is increased. In compression, the number of bits used to represent information is reduced. Thus you can have compression while still having sparse or non-contiguously arranged storage. As a result, compression may not always reduce the memory footprint. By compacting compressed data, the footprint of the information stored within the memory may be reduced. Compaction may reduce the need for far memory accesses in some cases.

Abstract: A tool for determining eviction of store cache entries based on store pressure. The tool determines, by one or more computer processors, a count value for one or more new store cache entry allocations. The tool determines whether a new store cache entry allocation limit is exceeded. Responsive to determining the new store cache entry allocation limit is exceeded, the tool determines an allocation value for one or more existing store cache entries, the allocation value indicating an allocation class for each of the one or more existing store cache entries. The tool determines based, at least in part, on the allocation value for the one or more existing store cache entries, at least one allocation class for eviction. The tool program determines an eviction request setting for evicting the one or more existing store cache entries.

Abstract: An apparatus having a cache and a controller is disclosed. The controller is configured to (i) gather a plurality of statistics corresponding to a plurality of requests made from one or more hosts to access a memory during an interval, (ii) store data of the requests selectively in the cache in response to a plurality of headers and (iii) adjust one or more parameters in the headers in response to the statistics. The requests and the parameters are recorded in the headers.

Abstract: Data processing systems and methods, according to various embodiments, perform privacy assessments and monitor new versions of computer code for updated features and conditions that relate to compliance with privacy standards. The systems and methods may obtain a copy of computer code (e.g., a software application or a website) that collects and/or uses personal data, and then automatically analyzes the computer code to identify one or more privacy-related attributes that may impact privacy assessment standards. In various embodiments, the system is adapted to monitor one or more locations (e.g., an online software application marketplace, and/or a specified website) to determine whether the application or website has changed. The system may, after analyzing the computer code, display the privacy-related attributes, collect information regarding the attributes, and automatically notify one or more designated individuals (e.g., privacy office representatives) regarding the attributes and information collected.

Abstract: A computer loads a web page, the web page including a first file and a second file. The computer then determines a likelihood of change value for the first and second file. The computer then loads one of the first or second file having a higher likelihood of change value and subsequently loads the other of the first or second file having a lower likelihood of change value.

Abstract: A processor writes input data to a cache line of a shared cache, wherein the input data is ready to be operated on by an accelerator. It then notifies an accelerator that the input data is ready to be processed. The processor then determines that output data of the accelerator is ready to be consumed, the output data being located at the cache line or an additional cache line of the shared cache, wherein the cache line or the additional cache line comprises a set first flag that indicates the cache line or the additional cache line was modified by the accelerator and that prevents the output data from being removed from the cache line or the additional cache line until the output data is read by the processor. The processor reads and processes the output data from the cache line or the additional cache.

Abstract: A method of controlling a cache memory includes receiving location information of one piece of data included in a data block and size information of the data block; mapping the data block onto cache memory by using the location information and the size information; and selecting at least one unit cache out of unit caches included in the cache memory based on the mapping result.

Abstract: In one embodiment, a computer-implemented method executable by a server system to store data in a data cache and refresh the data based on a dynamic schedule is provided. The method includes: receiving, by a processor, data from a first resource; storing, by the processor, the data in a data cache; determining, by the processor, a type of the data, and an access frequency of the data; determining, by the processor, a dynamic schedule based on the type of the data, and the access frequency of the data; and refreshing the data cache with new data from the first resource based on the dynamic schedule.

Abstract: A system includes a cache and a cache-management component. The cache includes a plurality of cache lines that correspond to a plurality of device endpoints. The cache-management component is configured to receive a transfer request block (TRB) for data transfer involving a device endpoint. In response to a determination that the cache both (i) does not include a cache line assigned to the device endpoint and (ii) does not include an empty cache line, the cache-management component assigns, to the device endpoint, a last cache line that includes a most recently received TRB in the cache, and stores the received TRB to the last cache line.

Abstract: The present application provides a method and system for optimal caching of content in the Information Centric Networks (ICN) and a cache replacement based on a content metric value. The method and system comprises requesting for a plurality of content by a user to a nearest local or edge ICN cache router; delivering by the local or edge ICN cache router the requested plurality of content to the user if it is available in its cache; else forwarding the request for the plurality of content to any of intermediate ICN cache router for finding source of the requested plurality of content; downloading the plurality of content in its downstream path; and storing the downloaded plurality of content based on a content metric value derived by a content metric system (CMS) based on a plurality of network parameters for the requested plurality of content.

Abstract: A combination of non-persistent-based and persistent-based schemes are used to effectively manage volatile storages which are conventionally managed solely by using non-persistent schemes (e.g., LRU schemes in cache memory). Generally, the persistent-based schemes can be based on persistent information associated with a non-volatile storage environment (e.g., persistent data temperatures associated with data stored in non-volatile storages). In this context, a persistent-based scheme can, for example, be effectively used in addition or combination with a conventional scheme provided for volatile memory. By way of example, a LRU scheme can be combined with a scheme based on persistent data temperatures in order to more effectively manage cache memory provided to enhance the performance of a system. As another example, a LRU, a LFU aging schemes can be combined with a scheme based on persistent data temperatures.

Abstract: A cache device may include a first cache including a first set and a plurality of ways corresponding to the first set, and a second cache including a second set and a plurality of ways corresponding to the second set. The second set is related with the first set depending on a vacancy of the ways of the first set.

Abstract: A processor includes a processing core, an L1 cache, operatively coupled to the processing core, the L1 cache comprising an L1 cache entry to store a data item, an L2 cache, inclusive with respect to the L1 cache, the L2 cache comprising an L2 cache entry corresponding to the L1 cache entry, an activity flag associated with the L2 cache entry, the activity flag indicating an activity status of the L1 cache entry, and a cache controller to, in response to detecting an access operation with respect to the L1 cache entry, set the flag to an active status.

Abstract: A last-level cache controller includes a system state monitor and a cache partitioning module. The system state monitor is configured to obtain a latency sensitivity factor, off-chip latency factors, and cache miss information for each of the processor cores. The cache partitioning module is configured to: obtain a first weighted latency according to the latency sensitivity factor, the off-chip latency factors and a first entry of the cache miss information that corresponds to a first cache partition configuration for each of the processor cores; obtain a first aggregated weighted latency according to the first weighted latency of each of the processor cores; determine whether a partition criterion is satisfied, where the partition criterion takes the first aggregated weighted latency into consideration; and partition the cache ways of the last-level cache using the first partition configuration when determining that the partition criterion is satisfied.

Abstract: A method, system, and computer-readable medium for evicting cache lines that includes determining that a first cache line is to be evicted from a first Last Level Cache (LLC) partition of a partitioned LLC, and sending, based on the determination, a first notification to a second LLC partition of the partitioned LLC. The method may also include receiving, in response to the first notification, an available indication indicating that the second LLC partition is available as a designated victim cache partition; performing a selection of the second LLC partition as the designated victim cache partition; and evicting the first cache line to the second LLC partition based on the selection.

Abstract: For maintaining consistency for a cache that contains dependent objects in a computing environment, object dependencies for cached objects are managed by defining and maintaining object dependency lists for each one of the cached objects for identifying objects upon which the cached objects are dependent. Maintaining cache consistency for 2 types of cache eviction policies is supported by maintaining an object dependency lists for each one of the cached objects for identifying objects dependent upon the cached object. Each of the objects in an object dependency list is updated when the object is updated.

Abstract: A cache memory system includes a cache memory, which stores cache data corresponding to portions of main data stored in a main memory and priority data respectively corresponding to the cache data; a table storage unit, which stores a priority table including information regarding access frequencies with respect to the main data; and a controller, which, when at least one from among the main data is requested, determines whether cache data corresponding to the request is stored in the cache memory, deletes one from among the cache data based on the priority data, and updates the cache data set with new data, wherein the priority data is determined based on the information regarding access frequencies.

Abstract: Embodiments of the approaches disclosed herein include a subsystem that includes an access tracking mechanism configured to monitor access operations directed to a first memory and a second memory. The access tracking mechanism detects an access operation generated by a processor for accessing a first memory page residing on the second memory. The access tracking mechanism further determines that the first memory page is included in a first subset of memory pages residing on the second memory. The access tracking mechanism further locates, within a reference vector, a reference bit that corresponds to the first memory page, and sets the reference bit. One advantage of the present invention is that memory pages in a hybrid system migrate as needed to increase overall memory performance.

Abstract: Systems and methods for allocation of cache lines in a shared partitioned cache of a multi-threaded processor. A memory management unit is configured to determine attributes associated with an address for a cache entry associated with a processing thread to be allocated in the cache. A configuration register is configured to store cache allocation information based on the determined attributes. A partitioning register is configured to store partitioning information for partitioning the cache into two or more portions. The cache entry is allocated into one of the portions of the cache based on the configuration register and the partitioning register.

Abstract: Methods for optimizing data access in a row-oriented relational database containing data sets having attributes using a computer are presented the method including: causing a computer to analyze a database workload to determine an access frequency for each of the attributes; causing the computer to assign each of the attributes to a priority classes corresponding with the access frequency, where the priority classes include a higher priority class and a lower priority class, and where a higher priority class corresponds with a higher access frequency and a lower priority class corresponds with a lower access frequency; causing the computer to store the attributes in accordance with the classes, where the attributes assigned to the higher priority class are stored in a high priority storage medium, and where the attributes assigned to a lower priority class are stored in a low priority storage medium.

Abstract: In one embodiment, a cache manager releases a list lock during a scan when a track has been identified as a track for cache removal processing such as demoting the track, for example. By releasing the list lock, other processors have access to the list while the identified track is processed for cache removal. In one aspect, the position of the previous entry in the list may be stored in a cursor or pointer so that the pointer value points to the prior entry in the list. Once the cache removal processing of the identified track is completed, the list lock may be reacquired and the scan may be resumed at the list entry identified by the pointer. Other features and aspects may be realized, depending upon the particular application.

Abstract: A method, system and computer program product for dynamic map template discovery and map creation may include determining a frequency of use of a data object in a database and discovering a dynamic map template corresponding to the data object based on the frequency of use of the data object. The method may also include creating a dynamic map from the dynamic map template in response to discovering the dynamic map template.

Abstract: In order to optimize efficiency of serialization, a serialization cache is maintained at an object server. The serialization cache is maintained in conjunction with an object cache and stores serialized forms of objects cached within the object cache. When an object is to be sent from the server to the client, a serialization module determines if a serialized form of the object is stored in the serialization cache. If the object is already serialized within the serialization cache, the serialized form is retrieved and provided to the client. Otherwise, the object is serialized, the object is cached in the object cache and the serialized form of the object is cached in the serialization cache.

Abstract: Described are techniques for controlling access to values and other stored resources, and controlling the ability of processes to modify values. Upon receipt of a request to access a value, a lease may be granted to a process if available. Lease data including identifiers associated with the process and the value may be generated. The connection with the process may be terminated after granting the lease, then reestablished upon receiving a subsequent request from the process to modify the value. The value may be modified responsive to a determination of correspondence between the process identifier determined from the process requesting to modify the value and the process identifier associated with the lease data.

Abstract: Apparatuses, systems, and methods for implementing a virtual machine on a data storage device are disclosed. In one embodiment, a device may comprise a communication interface responsive to a host, a processor, and a housing including the communication interface and the processor such that the device is removable from the host. The processor may be configured to receive a command from the host via the communication interface, process the command using a platform-independent program interface that is not dependent on the architecture of the device, and return results of the command to the host via the communication interface. In another embodiment, a method may comprise receiving at a data storage device a command from a host device, processing the command at the data storage device using a platform-independent program interface, and returning the results of the command from the data storage device to the host.

Abstract: An embodiment of the present disclosure includes a method for compressing data for a translation look aside buffer (TLB). The method includes: receiving an identifier at a content addressable memory (CAM), the identifier having a first bit length; compressing the identifier based on a location within the CAM the identifier is stored, the compressed identifier having a second bit length, the second bit length being smaller than the first bit length; and mapping at least the compressed identifier to a physical address in a buffer.

Abstract: A method for managing a memory is disclosed, the memory including a set of units and a unit comprising a set of pages, wherein a unit of the set of units is erasable as a whole by a unit reclaiming process resulting in a free unit available for writing data to. The method includes maintaining a first pool of units available for reclamation by the unit reclaiming process; maintaining a second pool of units not available for reclamation by the unit reclaiming process; moving a first unit from the first pool to the second pool in response to invalidating a first one of the pages contained in the first unit; returning the first unit from the second pool to the first pool after a defined number of units of the set have been written; and selecting a unit out of the first pool for reclamation by the unit reclaiming process.

Abstract: Exemplary methods, apparatuses, and systems receive a first input/output (I/O) trace including storage addresses that were subject to a plurality of I/O requests from a first workload during a first period of time. The first I/O trace is run through a cache simulation using a plurality of simulated cache sizes. A first state of the cache simulation is stored upon completing the first I/O trace simulation. The first I/O trace is deleted in response to storing the first state. A second I/O trace including storage addresses that were subject to a plurality of I/O requests from the first workload during a second period of time is received. A cumulative miss ratio curve for the first workload is generated by loading the stored first state as a starting point for simulating the second I/O trace and running the second I/O trace through the cache simulation.

Abstract: According to an aspect, management of auxiliary branch prediction in a processing system including a primary branch predictor and an auxiliary branch predictor is provided. A congruence class of the auxiliary branch predictor is located based on receiving a primary branch predictor misprediction indicator corresponding to a mispredicted target address of the primary branch predictor. An entry is identified in the congruence class having an auxiliary usefulness level set to a least useful level with respect to one or more other entries of the congruence class. Auxiliary data corresponding to the mispredicted target address is installed into the entry. The auxiliary usefulness level of the entry is reset to an initial value based on installing the auxiliary data.

Abstract: The inventions disclosed herein provide a crash-proof cache data protection method and system. The cache data backup steps include: when power interruption unexpectedly occur, a preselected central processing unit receiving an interrupt request signal; querying to obtain index nodes of block devices corresponding to logical volume management volumes; according to the index nodes, acquiring a page needing to be stored in a flash memory; acquiring a buffer head in the page, and storing information of the buffer head and buffer data corresponding to the buffer head into the flash memory, and generating backup data.

Abstract: Aspects include apparatuses, systems, and methods for hardware acceleration for inline caches in dynamic languages. An inline cache may be initialized for an instance of a dynamic software operation. A call of an initialized instance of the dynamic software operation may be executed by an inline cache hardware accelerator. The inline cache may be checked to determine that its data is current. When the data is current, the initialized instance of the dynamic software operation may be executed using the related inline cache data. When the data is not current, a new inline cache may be initialized for the instance of the dynamic software operation, including the not current data of a previously initialized instance of the dynamic software operation. The inline cache hardware accelerator may include an inline cache memory, a coprocessor, and/or a functional until one an inline cache pipeline connected to a processor pipeline.

Abstract: A method of and system for opening a data set is disclosed. The method and system may include structuring a storage facility to have address spaces. The address spaces may include a first address space having an open manager. The open manager may be configured and arranged to manage activities associated with an open request in response to receiving the open request. The method and system may include performing pseudo-opens associated with the open request in the address spaces. The method and system may include performing a batch-open utilizing the pseudo-opens and a resource used to complete the open request.

Abstract: For browser cache cleanup, to consider for eviction a data item stored in a cache of a browser application in a device, a probability that the data item will be needed again during a period after the eviction is computed. A type is determined of a network that will be available at the device during the period. A cost is computed of obtaining the data item over a network of the type, from a location of the device during the period. Using the probability and the cost, a weight of the data item is computed. The weight is associated with the data item as a part of associating a set of weights with a set of data items in the cache. The data item is selected for eviction from the cache because the weight is a lowest weight in the set of weights.

Abstract: A technique of processing instructions for execution by a processor includes determining whether a first property of a first instruction and a second property of a second instruction are compatible. The first instruction and the second instruction are grouped in an instruction group in response to the first and second properties being compatible and a feedback value generated by a feedback function indicating the instruction group has been historically beneficial with respect to a benefit metric of the processor. Group formation for the first and second instructions is performed according to another criteria, in response to the first and second properties being incompatible or the feedback value indicating the grouping of the first and second instructions has not been historically beneficial.

Abstract: A workload level associated with an expandable data buffer is determined, where the expandable data buffer and an expandable mapping table cache are stored in internal memory and the expandable mapping table cache is used to store a portion of a mapping table that is stored on external storage. An amount of internal memory allocated to the expandable data buffer and an amount of internal memory allocated to the expandable mapping table cache are adjusted based at least in part on the workload level.

Abstract: A control unit stores data used in a process to a shared cache memory. The control unit provides a shared queue in a memory space of the shared cache memory and performs LRU control with the use of the shared queue. The control unit also provides a local queue in the memory space of the shared cache memory. The control unit enqueues a CBE (management information) for a cache page used by a core in a process to the local queue. The control unit dequeues a plurality of CBEs from the local queue upon satisfaction of a predetermined condition, and enqueues the dequeued CBEs to the shared queue.

Abstract: Hybrid multi-level memory architecture technologies are described. A System on Chip (SOC) includes multiple functional units and a multi-level memory controller (MLMC) coupled to the functional units. The MLMC is coupled to a hybrid multi-level memory architecture including a first-level dynamic random access memory (DRAM) (near memory) that is located on-package of the SOC and a second-level DRAM (far memory) that is located off-package of the SOC. The MLMC presents the first-level DRAM and the second-level DRAM as a contiguous addressable memory space and provides the first-level DRAM to software as additional memory capacity to a memory capacity of the second-level DRAM. The first-level DRAM does not store a copy of contents of the second-level DRAM.

Abstract: Correlating two storage rings based on an access rate for an object. A correlative dual hash ring includes a first ring of storage drives and a second ring of storage drives. Objects and replicas are allocated to either a first ring or a second ring.

Abstract: A set-associative cache memory includes a plurality of congruence classes each including multiple entries for storing cache lines of data. A respective one of a plurality of counters is maintained for each cache line stored in the multiple entries. In response to a memory access request, the cache memory selects a victim cache line stored in a particular entry of a particular congruence class for eviction from the cache memory by reference to at least a counter value of the victim cache line. The cache memory also receives a new cache line of data for insertion into the particular entry and an indication of a coherence state of the new cache line at a data source from which the cache memory received the new cache line. The cache memory installs the new cache line in the particular entry and sets an initial counter value of the counter for the new cache line based on the received indication of the coherence state at the data source.

Abstract: A set-associative cache memory includes a plurality of congruence classes each including multiple entries for storing cache lines of data. A respective one of a plurality of counters is maintained for each cache line stored in the multiple entries. In response to a memory access request, the cache memory selects a victim cache line stored in a particular entry of a particular congruence class for eviction from the cache memory by reference to at least a counter value of the victim cache line. The cache memory also receives a new cache line of data for insertion into the particular entry and an indication of a distance from the cache memory to a data source from which the cache memory received the new cache line. The cache memory installs the new cache line in the particular entry and sets an initial counter value of the counter for the new cache line based on the received indication of the distance.

Abstract: Methods and systems are presented for evicting or copying-forward blocks in a storage system during garbage collection. In one method, a block status is maintained in a first memory to identify if the block is active or inactive, blocks being stored in segments that are configured to be cacheable in a second memory, a read-cache memory. Whenever an operation on a block is detected making the block inactive in one volume, the system determines if the block is still active in any volume, the block being cached in a first segment in the second memory. When the system detects that the first segment is being evicted from the second memory, the system re-caches the block into a second segment in the second memory if the block status of the block is active and the frequency of access to the block is above a predetermined value.

Abstract: Data migration among cloud-based storage networks is described. A method may include analyzing, by a processor, whether data from a data distribution service is consistent with a data payload of a host cloud provider. The method also includes determining, by the processor, in view of the analyzing, whether the data is a replica of the data payload of the host cloud provider. The method further includes determining, by the processor, whether to initiate a transport of the data to a resource associated with a target cloud provider.

Abstract: A data processing system and methods for performing cache eviction are disclosed. An exemplary method includes maintaining a metadata set for each cache unit of a cache device, wherein the cache device comprises a plurality of cache units, each cache unit having a plurality of segments, wherein each metadata set includes deletion hints (DH) metadata indicating whether the plurality of segments of a corresponding cache unit are valid. The exemplary method further includes in response to determining that a cache eviction is to be performed, selecting a predetermined number of cache units from the plurality of cache units, and determining a score for each of the selected cache units based on the DH metadata of the respective metadata set. The DH metadata may include, for example, a validation count for each segment group or cache unit. A deprecated segment can be changed back to being valid, and the score for each of the selected cache units may further be determined based on a determined probability.

Abstract: A file-mapping method and system can better manage the number of items (i.e., files, subdirectories, or a combination of them) within any single directory within a storage medium. The method and system can be used to limit the number of items within the directory, direct content and content components to different directories, and provide an internally recognizable name for the filename. When searching the storage medium, time is not wasted searching what appears to be a seemingly endless list of filenames or subdirectory names within any single directory. A client computer can have requests for content fulfilled quicker, and the network site can reduce the load on hardware or software components. While the method and system can be used for nearly any storage media, the method and system are well suited for cache memories used with web servers.

Abstract: A computing system includes: a memory computing block configured to: identify a partial data computing (PDC) command, a data mask, a partial data, or a combination thereof based on decoding a data packet, compute a computation result for identifying a portion of a read data to be modified according to the PDC command, the data mask, the partial data, or a combination thereof, generate a merge result based on modifying the portion of the read data according to the computation result, and a memory interface, coupled to the memory computing block, configured to transmit the merge result.

Abstract: For reducing lock contention on a Modified Least Recently Used (MLRU) list for metadata tracks, upon a conclusion of an access of a metadata track, if one of the metadata track is located in a predefined lower percentile of the MLRU list, and the metadata track has been accessed, including the access, a predetermined number of times, the metadata track is removed from a current position in the MLRU list and moved to a Most Recently Used (MRU) end of the MLRU list.